drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 bool
  37 intel_ring_initialized(struct intel_engine_cs *ring)
  38 {
  39         struct drm_device *dev = ring->dev;
  40
  41         if (!dev)
  42                 return false;
  43
  44         if (i915.enable_execlists) {
  45                 struct intel_context *dctx = ring->default_context;
  46                 struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
  47
  48                 return ringbuf->obj;
  49         } else
  50                 return ring->buffer && ring->buffer->obj;
  51 }
  52
  53 int __intel_ring_space(int head, int tail, int size)
  54 {
  55         int space = head - (tail + I915_RING_FREE_SPACE);
  56         if (space < 0)
  57                 space += size;
  58         return space;
  59 }
  60
  61 int intel_ring_space(struct intel_ringbuffer *ringbuf)
  62 {
  63         return __intel_ring_space(ringbuf->head & HEAD_ADDR,
  64                                   ringbuf->tail, ringbuf->size);
  65 }
  66
  67 bool intel_ring_stopped(struct intel_engine_cs *ring)
  68 {
  69         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  70         return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring);
  71 }
  72
  73 void __intel_ring_advance(struct intel_engine_cs *ring)
  74 {
  75         struct intel_ringbuffer *ringbuf = ring->buffer;
  76         ringbuf->tail &= ringbuf->size - 1;
  77         if (intel_ring_stopped(ring))
  78                 return;
  79         ring->write_tail(ring, ringbuf->tail);
  80 }
  81
  82 static int
  83 gen2_render_ring_flush(struct intel_engine_cs *ring,
  84                        u32      invalidate_domains,
  85                        u32      flush_domains)
  86 {
  87         u32 cmd;
  88         int ret;
  89
  90         cmd = MI_FLUSH;
  91         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  92                 cmd |= MI_NO_WRITE_FLUSH;
  93
  94         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  95                 cmd |= MI_READ_FLUSH;
  96
  97         ret = intel_ring_begin(ring, 2);
  98         if (ret)
  99                 return ret;
 100
 101         intel_ring_emit(ring, cmd);
 102         intel_ring_emit(ring, MI_NOOP);
 103         intel_ring_advance(ring);
 104
 105         return 0;
 106 }
 107
 108 static int
 109 gen4_render_ring_flush(struct intel_engine_cs *ring,
 110                        u32      invalidate_domains,
 111                        u32      flush_domains)
 112 {
 113         struct drm_device *dev = ring->dev;
 114         u32 cmd;
 115         int ret;
 116
 117         /*
 118          * read/write caches:
 119          *
 120          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 121          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 122          * also flushed at 2d versus 3d pipeline switches.
 123          *
 124          * read-only caches:
 125          *
 126          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 127          * MI_READ_FLUSH is set, and is always flushed on 965.
 128          *
 129          * I915_GEM_DOMAIN_COMMAND may not exist?
 130          *
 131          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 132          * invalidated when MI_EXE_FLUSH is set.
 133          *
 134          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 135          * invalidated with every MI_FLUSH.
 136          *
 137          * TLBs:
 138          *
 139          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 140          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 141          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 142          * are flushed at any MI_FLUSH.
 143          */
 144
 145         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 146         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 147                 cmd &= ~MI_NO_WRITE_FLUSH;
 148         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 149                 cmd |= MI_EXE_FLUSH;
 150
 151         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 152             (IS_G4X(dev) || IS_GEN5(dev)))
 153                 cmd |= MI_INVALIDATE_ISP;
 154
 155         ret = intel_ring_begin(ring, 2);
 156         if (ret)
 157                 return ret;
 158
 159         intel_ring_emit(ring, cmd);
 160         intel_ring_emit(ring, MI_NOOP);
 161         intel_ring_advance(ring);
 162
 163         return 0;
 164 }
 165
 166 /**
 167  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 168  * implementing two workarounds on gen6.  From section 1.4.7.1
 169  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 170  *
 171  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 172  * produced by non-pipelined state commands), software needs to first
 173  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 174  * 0.
 175  *
 176  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 177  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 178  *
 179  * And the workaround for these two requires this workaround first:
 180  *
 181  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 182  * BEFORE the pipe-control with a post-sync op and no write-cache
 183  * flushes.
 184  *
 185  * And this last workaround is tricky because of the requirements on
 186  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 187  * volume 2 part 1:
 188  *
 189  *     "1 of the following must also be set:
 190  *      - Render Target Cache Flush Enable ([12] of DW1)
 191  *      - Depth Cache Flush Enable ([0] of DW1)
 192  *      - Stall at Pixel Scoreboard ([1] of DW1)
 193  *      - Depth Stall ([13] of DW1)
 194  *      - Post-Sync Operation ([13] of DW1)
 195  *      - Notify Enable ([8] of DW1)"
 196  *
 197  * The cache flushes require the workaround flush that triggered this
 198  * one, so we can't use it.  Depth stall would trigger the same.
 199  * Post-sync nonzero is what triggered this second workaround, so we
 200  * can't use that one either.  Notify enable is IRQs, which aren't
 201  * really our business.  That leaves only stall at scoreboard.
 202  */
 203 static int
 204 intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring)
 205 {
 206         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 207         int ret;
 208
 209
 210         ret = intel_ring_begin(ring, 6);
 211         if (ret)
 212                 return ret;
 213
 214         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 215         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 216                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 217         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 218         intel_ring_emit(ring, 0); /* low dword */
 219         intel_ring_emit(ring, 0); /* high dword */
 220         intel_ring_emit(ring, MI_NOOP);
 221         intel_ring_advance(ring);
 222
 223         ret = intel_ring_begin(ring, 6);
 224         if (ret)
 225                 return ret;
 226
 227         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 228         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 229         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 230         intel_ring_emit(ring, 0);
 231         intel_ring_emit(ring, 0);
 232         intel_ring_emit(ring, MI_NOOP);
 233         intel_ring_advance(ring);
 234
 235         return 0;
 236 }
 237
 238 static int
 239 gen6_render_ring_flush(struct intel_engine_cs *ring,
 240                          u32 invalidate_domains, u32 flush_domains)
 241 {
 242         u32 flags = 0;
 243         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 244         int ret;
 245
 246         /* Force SNB workarounds for PIPE_CONTROL flushes */
 247         ret = intel_emit_post_sync_nonzero_flush(ring);
 248         if (ret)
 249                 return ret;
 250
 251         /* Just flush everything.  Experiments have shown that reducing the
 252          * number of bits based on the write domains has little performance
 253          * impact.
 254          */
 255         if (flush_domains) {
 256                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 257                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 258                 /*
 259                  * Ensure that any following seqno writes only happen
 260                  * when the render cache is indeed flushed.
 261                  */
 262                 flags |= PIPE_CONTROL_CS_STALL;
 263         }
 264         if (invalidate_domains) {
 265                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 266                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 267                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 268                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 269                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 270                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 271                 /*
 272                  * TLB invalidate requires a post-sync write.
 273                  */
 274                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 275         }
 276
 277         ret = intel_ring_begin(ring, 4);
 278         if (ret)
 279                 return ret;
 280
 281         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 282         intel_ring_emit(ring, flags);
 283         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 284         intel_ring_emit(ring, 0);
 285         intel_ring_advance(ring);
 286
 287         return 0;
 288 }
 289
 290 static int
 291 gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring)
 292 {
 293         int ret;
 294
 295         ret = intel_ring_begin(ring, 4);
 296         if (ret)
 297                 return ret;
 298
 299         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 300         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 301                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 302         intel_ring_emit(ring, 0);
 303         intel_ring_emit(ring, 0);
 304         intel_ring_advance(ring);
 305
 306         return 0;
 307 }
 308
 309 static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value)
 310 {
 311         int ret;
 312
 313         if (!ring->fbc_dirty)
 314                 return 0;
 315
 316         ret = intel_ring_begin(ring, 6);
 317         if (ret)
 318                 return ret;
 319         /* WaFbcNukeOn3DBlt:ivb/hsw */
 320         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 321         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 322         intel_ring_emit(ring, value);
 323         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 324         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 325         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 326         intel_ring_advance(ring);
 327
 328         ring->fbc_dirty = false;
 329         return 0;
 330 }
 331
 332 static int
 333 gen7_render_ring_flush(struct intel_engine_cs *ring,
 334                        u32 invalidate_domains, u32 flush_domains)
 335 {
 336         u32 flags = 0;
 337         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 338         int ret;
 339
 340         /*
 341          * Ensure that any following seqno writes only happen when the render
 342          * cache is indeed flushed.
 343          *
 344          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 345          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 346          * don't try to be clever and just set it unconditionally.
 347          */
 348         flags |= PIPE_CONTROL_CS_STALL;
 349
 350         /* Just flush everything.  Experiments have shown that reducing the
 351          * number of bits based on the write domains has little performance
 352          * impact.
 353          */
 354         if (flush_domains) {
 355                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 356                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 357         }
 358         if (invalidate_domains) {
 359                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 360                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 361                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 362                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 363                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 364                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 365                 /*
 366                  * TLB invalidate requires a post-sync write.
 367                  */
 368                 flags |= PIPE_CONTROL_QW_WRITE;
 369                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 370
 371                 /* Workaround: we must issue a pipe_control with CS-stall bit
 372                  * set before a pipe_control command that has the state cache
 373                  * invalidate bit set. */
 374                 gen7_render_ring_cs_stall_wa(ring);
 375         }
 376
 377         ret = intel_ring_begin(ring, 4);
 378         if (ret)
 379                 return ret;
 380
 381         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 382         intel_ring_emit(ring, flags);
 383         intel_ring_emit(ring, scratch_addr);
 384         intel_ring_emit(ring, 0);
 385         intel_ring_advance(ring);
 386
 387         if (!invalidate_domains && flush_domains)
 388                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 389
 390         return 0;
 391 }
 392
 393 static int
 394 gen8_emit_pipe_control(struct intel_engine_cs *ring,
 395                        u32 flags, u32 scratch_addr)
 396 {
 397         int ret;
 398
 399         ret = intel_ring_begin(ring, 6);
 400         if (ret)
 401                 return ret;
 402
 403         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 404         intel_ring_emit(ring, flags);
 405         intel_ring_emit(ring, scratch_addr);
 406         intel_ring_emit(ring, 0);
 407         intel_ring_emit(ring, 0);
 408         intel_ring_emit(ring, 0);
 409         intel_ring_advance(ring);
 410
 411         return 0;
 412 }
 413
 414 static int
 415 gen8_render_ring_flush(struct intel_engine_cs *ring,
 416                        u32 invalidate_domains, u32 flush_domains)
 417 {
 418         u32 flags = 0;
 419         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 420         int ret;
 421
 422         flags |= PIPE_CONTROL_CS_STALL;
 423
 424         if (flush_domains) {
 425                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 426                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 427         }
 428         if (invalidate_domains) {
 429                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 430                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 431                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 432                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 433                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 434                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 435                 flags |= PIPE_CONTROL_QW_WRITE;
 436                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 437
 438                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 439                 ret = gen8_emit_pipe_control(ring,
 440                                              PIPE_CONTROL_CS_STALL |
 441                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 442                                              0);
 443                 if (ret)
 444                         return ret;
 445         }
 446
 447         ret = gen8_emit_pipe_control(ring, flags, scratch_addr);
 448         if (ret)
 449                 return ret;
 450
 451         if (!invalidate_domains && flush_domains)
 452                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 453
 454         return 0;
 455 }
 456
 457 static void ring_write_tail(struct intel_engine_cs *ring,
 458                             u32 value)
 459 {
 460         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 461         I915_WRITE_TAIL(ring, value);
 462 }
 463
 464 u64 intel_ring_get_active_head(struct intel_engine_cs *ring)
 465 {
 466         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 467         u64 acthd;
 468
 469         if (INTEL_INFO(ring->dev)->gen >= 8)
 470                 acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base),
 471                                          RING_ACTHD_UDW(ring->mmio_base));
 472         else if (INTEL_INFO(ring->dev)->gen >= 4)
 473                 acthd = I915_READ(RING_ACTHD(ring->mmio_base));
 474         else
 475                 acthd = I915_READ(ACTHD);
 476
 477         return acthd;
 478 }
 479
 480 static void ring_setup_phys_status_page(struct intel_engine_cs *ring)
 481 {
 482         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 483         u32 addr;
 484
 485         addr = dev_priv->status_page_dmah->busaddr;
 486         if (INTEL_INFO(ring->dev)->gen >= 4)
 487                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 488         I915_WRITE(HWS_PGA, addr);
 489 }
 490
 491 static bool stop_ring(struct intel_engine_cs *ring)
 492 {
 493         struct drm_i915_private *dev_priv = to_i915(ring->dev);
 494
 495         if (!IS_GEN2(ring->dev)) {
 496                 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
 497                 if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) {
 498                         DRM_ERROR("%s : timed out trying to stop ring\n", ring->name);
 499                         /* Sometimes we observe that the idle flag is not
 500                          * set even though the ring is empty. So double
 501                          * check before giving up.
 502                          */
 503                         if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring))
 504                                 return false;
 505                 }
 506         }
 507
 508         I915_WRITE_CTL(ring, 0);
 509         I915_WRITE_HEAD(ring, 0);
 510         ring->write_tail(ring, 0);
 511
 512         if (!IS_GEN2(ring->dev)) {
 513                 (void)I915_READ_CTL(ring);
 514                 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING));
 515         }
 516
 517         return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0;
 518 }
 519
 520 static int init_ring_common(struct intel_engine_cs *ring)
 521 {
 522         struct drm_device *dev = ring->dev;
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524         struct intel_ringbuffer *ringbuf = ring->buffer;
 525         struct drm_i915_gem_object *obj = ringbuf->obj;
 526         int ret = 0;
 527
 528         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 529
 530         if (!stop_ring(ring)) {
 531                 /* G45 ring initialization often fails to reset head to zero */
 532                 DRM_DEBUG_KMS("%s head not reset to zero "
 533                               "ctl %08x head %08x tail %08x start %08x\n",
 534                               ring->name,
 535                               I915_READ_CTL(ring),
 536                               I915_READ_HEAD(ring),
 537                               I915_READ_TAIL(ring),
 538                               I915_READ_START(ring));
 539
 540                 if (!stop_ring(ring)) {
 541                         DRM_ERROR("failed to set %s head to zero "
 542                                   "ctl %08x head %08x tail %08x start %08x\n",
 543                                   ring->name,
 544                                   I915_READ_CTL(ring),
 545                                   I915_READ_HEAD(ring),
 546                                   I915_READ_TAIL(ring),
 547                                   I915_READ_START(ring));
 548                         ret = -EIO;
 549                         goto out;
 550                 }
 551         }
 552
 553         if (I915_NEED_GFX_HWS(dev))
 554                 intel_ring_setup_status_page(ring);
 555         else
 556                 ring_setup_phys_status_page(ring);
 557
 558         /* Enforce ordering by reading HEAD register back */
 559         I915_READ_HEAD(ring);
 560
 561         /* Initialize the ring. This must happen _after_ we've cleared the ring
 562          * registers with the above sequence (the readback of the HEAD registers
 563          * also enforces ordering), otherwise the hw might lose the new ring
 564          * register values. */
 565         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 566
 567         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 568         if (I915_READ_HEAD(ring))
 569                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 570                           ring->name, I915_READ_HEAD(ring));
 571         I915_WRITE_HEAD(ring, 0);
 572         (void)I915_READ_HEAD(ring);
 573
 574         I915_WRITE_CTL(ring,
 575                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 576                         | RING_VALID);
 577
 578         /* If the head is still not zero, the ring is dead */
 579         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 580                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 581                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 582                 DRM_ERROR("%s initialization failed "
 583                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 584                           ring->name,
 585                           I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID,
 586                           I915_READ_HEAD(ring), I915_READ_TAIL(ring),
 587                           I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj));
 588                 ret = -EIO;
 589                 goto out;
 590         }
 591
 592         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 593                 i915_kernel_lost_context(ring->dev);
 594         else {
 595                 ringbuf->head = I915_READ_HEAD(ring);
 596                 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 597                 ringbuf->space = intel_ring_space(ringbuf);
 598                 ringbuf->last_retired_head = -1;
 599         }
 600
 601         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 602
 603 out:
 604         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 605
 606         return ret;
 607 }
 608
 609 void
 610 intel_fini_pipe_control(struct intel_engine_cs *ring)
 611 {
 612         struct drm_device *dev = ring->dev;
 613
 614         if (ring->scratch.obj == NULL)
 615                 return;
 616
 617         if (INTEL_INFO(dev)->gen >= 5) {
 618                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 619                 i915_gem_object_ggtt_unpin(ring->scratch.obj);
 620         }
 621
 622         drm_gem_object_unreference(&ring->scratch.obj->base);
 623         ring->scratch.obj = NULL;
 624 }
 625
 626 int
 627 intel_init_pipe_control(struct intel_engine_cs *ring)
 628 {
 629         int ret;
 630
 631         if (ring->scratch.obj)
 632                 return 0;
 633
 634         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 635         if (ring->scratch.obj == NULL) {
 636                 DRM_ERROR("Failed to allocate seqno page\n");
 637                 ret = -ENOMEM;
 638                 goto err;
 639         }
 640
 641         ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 642         if (ret)
 643                 goto err_unref;
 644
 645         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
 646         if (ret)
 647                 goto err_unref;
 648
 649         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 650         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 651         if (ring->scratch.cpu_page == NULL) {
 652                 ret = -ENOMEM;
 653                 goto err_unpin;
 654         }
 655
 656         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 657                          ring->name, ring->scratch.gtt_offset);
 658         return 0;
 659
 660 err_unpin:
 661         i915_gem_object_ggtt_unpin(ring->scratch.obj);
 662 err_unref:
 663         drm_gem_object_unreference(&ring->scratch.obj->base);
 664 err:
 665         return ret;
 666 }
 667
 668 static int intel_ring_workarounds_emit(struct intel_engine_cs *ring)
 669 {
 670         int ret, i;
 671         struct drm_device *dev = ring->dev;
 672         struct drm_i915_private *dev_priv = dev->dev_private;
 673         struct i915_workarounds *w = &dev_priv->workarounds;
 674
 675         if (WARN_ON(w->count == 0))
 676                 return 0;
 677
 678         ring->gpu_caches_dirty = true;
 679         ret = intel_ring_flush_all_caches(ring);
 680         if (ret)
 681                 return ret;
 682
 683         ret = intel_ring_begin(ring, (w->count * 2 + 2));
 684         if (ret)
 685                 return ret;
 686
 687         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
 688         for (i = 0; i < w->count; i++) {
 689                 intel_ring_emit(ring, w->reg[i].addr);
 690                 intel_ring_emit(ring, w->reg[i].value);
 691         }
 692         intel_ring_emit(ring, MI_NOOP);
 693
 694         intel_ring_advance(ring);
 695
 696         ring->gpu_caches_dirty = true;
 697         ret = intel_ring_flush_all_caches(ring);
 698         if (ret)
 699                 return ret;
 700
 701         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 702
 703         return 0;
 704 }
 705
 706 static int wa_add(struct drm_i915_private *dev_priv,
 707                   const u32 addr, const u32 val, const u32 mask)
 708 {
 709         const u32 idx = dev_priv->workarounds.count;
 710
 711         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 712                 return -ENOSPC;
 713
 714         dev_priv->workarounds.reg[idx].addr = addr;
 715         dev_priv->workarounds.reg[idx].value = val;
 716         dev_priv->workarounds.reg[idx].mask = mask;
 717
 718         dev_priv->workarounds.count++;
 719
 720         return 0;
 721 }
 722
 723 #define WA_REG(addr, val, mask) { \
 724                 const int r = wa_add(dev_priv, (addr), (val), (mask)); \
 725                 if (r) \
 726                         return r; \
 727         }
 728
 729 #define WA_SET_BIT_MASKED(addr, mask) \
 730         WA_REG(addr, _MASKED_BIT_ENABLE(mask), (mask) & 0xffff)
 731
 732 #define WA_CLR_BIT_MASKED(addr, mask) \
 733         WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
 734
 735 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
 736 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
 737
 738 #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff)
 739
 740 static int bdw_init_workarounds(struct intel_engine_cs *ring)
 741 {
 742         struct drm_device *dev = ring->dev;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744
 745         /* WaDisablePartialInstShootdown:bdw */
 746         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 747         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 748                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE |
 749                           STALL_DOP_GATING_DISABLE);
 750
 751         /* WaDisableDopClockGating:bdw */
 752         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 753                           DOP_CLOCK_GATING_DISABLE);
 754
 755         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 756                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 757
 758         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 759          * workaround for for a possible hang in the unlikely event a TLB
 760          * invalidation occurs during a PSD flush.
 761          */
 762         /* WaDisableFenceDestinationToSLM:bdw (GT3 pre-production) */
 763         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 764                           HDC_FORCE_NON_COHERENT |
 765                           (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 766
 767         /* Wa4x4STCOptimizationDisable:bdw */
 768         WA_SET_BIT_MASKED(CACHE_MODE_1,
 769                           GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 770
 771         /*
 772          * BSpec recommends 8x4 when MSAA is used,
 773          * however in practice 16x4 seems fastest.
 774          *
 775          * Note that PS/WM thread counts depend on the WIZ hashing
 776          * disable bit, which we don't touch here, but it's good
 777          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 778          */
 779         WA_SET_BIT_MASKED(GEN7_GT_MODE,
 780                           GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
 781
 782         return 0;
 783 }
 784
 785 static int chv_init_workarounds(struct intel_engine_cs *ring)
 786 {
 787         struct drm_device *dev = ring->dev;
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789
 790         /* WaDisablePartialInstShootdown:chv */
 791         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 792                   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 793
 794         /* WaDisableThreadStallDopClockGating:chv */
 795         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 796                   STALL_DOP_GATING_DISABLE);
 797
 798         /* WaDisableDopClockGating:chv (pre-production hw) */
 799         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 800                   DOP_CLOCK_GATING_DISABLE);
 801
 802         /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
 803         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 804                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 805
 806         return 0;
 807 }
 808
 809 static int init_workarounds_ring(struct intel_engine_cs *ring)
 810 {
 811         struct drm_device *dev = ring->dev;
 812         struct drm_i915_private *dev_priv = dev->dev_private;
 813
 814         WARN_ON(ring->id != RCS);
 815
 816         dev_priv->workarounds.count = 0;
 817
 818         if (IS_BROADWELL(dev))
 819                 return bdw_init_workarounds(ring);
 820
 821         if (IS_CHERRYVIEW(dev))
 822                 return chv_init_workarounds(ring);
 823
 824         return 0;
 825 }
 826
 827 static int init_render_ring(struct intel_engine_cs *ring)
 828 {
 829         struct drm_device *dev = ring->dev;
 830         struct drm_i915_private *dev_priv = dev->dev_private;
 831         int ret = init_ring_common(ring);
 832         if (ret)
 833                 return ret;
 834
 835         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 836         if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
 837                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 838
 839         /* We need to disable the AsyncFlip performance optimisations in order
 840          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 841          * programmed to '1' on all products.
 842          *
 843          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
 844          */
 845         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
 846                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 847
 848         /* Required for the hardware to program scanline values for waiting */
 849         /* WaEnableFlushTlbInvalidationMode:snb */
 850         if (INTEL_INFO(dev)->gen == 6)
 851                 I915_WRITE(GFX_MODE,
 852                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 853
 854         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 855         if (IS_GEN7(dev))
 856                 I915_WRITE(GFX_MODE_GEN7,
 857                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 858                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 859
 860         if (INTEL_INFO(dev)->gen >= 5) {
 861                 ret = intel_init_pipe_control(ring);
 862                 if (ret)
 863                         return ret;
 864         }
 865
 866         if (IS_GEN6(dev)) {
 867                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 868                  * "If this bit is set, STCunit will have LRA as replacement
 869                  *  policy. [...] This bit must be reset.  LRA replacement
 870                  *  policy is not supported."
 871                  */
 872                 I915_WRITE(CACHE_MODE_0,
 873                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 874         }
 875
 876         if (INTEL_INFO(dev)->gen >= 6)
 877                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 878
 879         if (HAS_L3_DPF(dev))
 880                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 881
 882         return init_workarounds_ring(ring);
 883 }
 884
 885 static void render_ring_cleanup(struct intel_engine_cs *ring)
 886 {
 887         struct drm_device *dev = ring->dev;
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889
 890         if (dev_priv->semaphore_obj) {
 891                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
 892                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
 893                 dev_priv->semaphore_obj = NULL;
 894         }
 895
 896         intel_fini_pipe_control(ring);
 897 }
 898
 899 static int gen8_rcs_signal(struct intel_engine_cs *signaller,
 900                            unsigned int num_dwords)
 901 {
 902 #define MBOX_UPDATE_DWORDS 8
 903         struct drm_device *dev = signaller->dev;
 904         struct drm_i915_private *dev_priv = dev->dev_private;
 905         struct intel_engine_cs *waiter;
 906         int i, ret, num_rings;
 907
 908         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 909         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 910 #undef MBOX_UPDATE_DWORDS
 911
 912         ret = intel_ring_begin(signaller, num_dwords);
 913         if (ret)
 914                 return ret;
 915
 916         for_each_ring(waiter, dev_priv, i) {
 917                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 918                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 919                         continue;
 920
 921                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
 922                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
 923                                            PIPE_CONTROL_QW_WRITE |
 924                                            PIPE_CONTROL_FLUSH_ENABLE);
 925                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
 926                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 927                 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 928                 intel_ring_emit(signaller, 0);
 929                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 930                                            MI_SEMAPHORE_TARGET(waiter->id));
 931                 intel_ring_emit(signaller, 0);
 932         }
 933
 934         return 0;
 935 }
 936
 937 static int gen8_xcs_signal(struct intel_engine_cs *signaller,
 938                            unsigned int num_dwords)
 939 {
 940 #define MBOX_UPDATE_DWORDS 6
 941         struct drm_device *dev = signaller->dev;
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         struct intel_engine_cs *waiter;
 944         int i, ret, num_rings;
 945
 946         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 947         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
 948 #undef MBOX_UPDATE_DWORDS
 949
 950         ret = intel_ring_begin(signaller, num_dwords);
 951         if (ret)
 952                 return ret;
 953
 954         for_each_ring(waiter, dev_priv, i) {
 955                 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
 956                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
 957                         continue;
 958
 959                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
 960                                            MI_FLUSH_DW_OP_STOREDW);
 961                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
 962                                            MI_FLUSH_DW_USE_GTT);
 963                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
 964                 intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 965                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
 966                                            MI_SEMAPHORE_TARGET(waiter->id));
 967                 intel_ring_emit(signaller, 0);
 968         }
 969
 970         return 0;
 971 }
 972
 973 static int gen6_signal(struct intel_engine_cs *signaller,
 974                        unsigned int num_dwords)
 975 {
 976         struct drm_device *dev = signaller->dev;
 977         struct drm_i915_private *dev_priv = dev->dev_private;
 978         struct intel_engine_cs *useless;
 979         int i, ret, num_rings;
 980
 981 #define MBOX_UPDATE_DWORDS 3
 982         num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
 983         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
 984 #undef MBOX_UPDATE_DWORDS
 985
 986         ret = intel_ring_begin(signaller, num_dwords);
 987         if (ret)
 988                 return ret;
 989
 990         for_each_ring(useless, dev_priv, i) {
 991                 u32 mbox_reg = signaller->semaphore.mbox.signal[i];
 992                 if (mbox_reg != GEN6_NOSYNC) {
 993                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
 994                         intel_ring_emit(signaller, mbox_reg);
 995                         intel_ring_emit(signaller, signaller->outstanding_lazy_seqno);
 996                 }
 997         }
 998
 999         /* If num_dwords was rounded, make sure the tail pointer is correct */
1000         if (num_rings % 2 == 0)
1001                 intel_ring_emit(signaller, MI_NOOP);
1002
1003         return 0;
1004 }
1005
1006 /**
1007  * gen6_add_request - Update the semaphore mailbox registers
1008  *
1009  * @ring - ring that is adding a request
1010  * @seqno - return seqno stuck into the ring
1011  *
1012  * Update the mailbox registers in the *other* rings with the current seqno.
1013  * This acts like a signal in the canonical semaphore.
1014  */
1015 static int
1016 gen6_add_request(struct intel_engine_cs *ring)
1017 {
1018         int ret;
1019
1020         if (ring->semaphore.signal)
1021                 ret = ring->semaphore.signal(ring, 4);
1022         else
1023                 ret = intel_ring_begin(ring, 4);
1024
1025         if (ret)
1026                 return ret;
1027
1028         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1029         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1030         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1031         intel_ring_emit(ring, MI_USER_INTERRUPT);
1032         __intel_ring_advance(ring);
1033
1034         return 0;
1035 }
1036
1037 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1038                                               u32 seqno)
1039 {
1040         struct drm_i915_private *dev_priv = dev->dev_private;
1041         return dev_priv->last_seqno < seqno;
1042 }
1043
1044 /**
1045  * intel_ring_sync - sync the waiter to the signaller on seqno
1046  *
1047  * @waiter - ring that is waiting
1048  * @signaller - ring which has, or will signal
1049  * @seqno - seqno which the waiter will block on
1050  */
1051
1052 static int
1053 gen8_ring_sync(struct intel_engine_cs *waiter,
1054                struct intel_engine_cs *signaller,
1055                u32 seqno)
1056 {
1057         struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1058         int ret;
1059
1060         ret = intel_ring_begin(waiter, 4);
1061         if (ret)
1062                 return ret;
1063
1064         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1065                                 MI_SEMAPHORE_GLOBAL_GTT |
1066                                 MI_SEMAPHORE_POLL |
1067                                 MI_SEMAPHORE_SAD_GTE_SDD);
1068         intel_ring_emit(waiter, seqno);
1069         intel_ring_emit(waiter,
1070                         lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1071         intel_ring_emit(waiter,
1072                         upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1073         intel_ring_advance(waiter);
1074         return 0;
1075 }
1076
1077 static int
1078 gen6_ring_sync(struct intel_engine_cs *waiter,
1079                struct intel_engine_cs *signaller,
1080                u32 seqno)
1081 {
1082         u32 dw1 = MI_SEMAPHORE_MBOX |
1083                   MI_SEMAPHORE_COMPARE |
1084                   MI_SEMAPHORE_REGISTER;
1085         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1086         int ret;
1087
1088         /* Throughout all of the GEM code, seqno passed implies our current
1089          * seqno is >= the last seqno executed. However for hardware the
1090          * comparison is strictly greater than.
1091          */
1092         seqno -= 1;
1093
1094         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1095
1096         ret = intel_ring_begin(waiter, 4);
1097         if (ret)
1098                 return ret;
1099
1100         /* If seqno wrap happened, omit the wait with no-ops */
1101         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
1102                 intel_ring_emit(waiter, dw1 | wait_mbox);
1103                 intel_ring_emit(waiter, seqno);
1104                 intel_ring_emit(waiter, 0);
1105                 intel_ring_emit(waiter, MI_NOOP);
1106         } else {
1107                 intel_ring_emit(waiter, MI_NOOP);
1108                 intel_ring_emit(waiter, MI_NOOP);
1109                 intel_ring_emit(waiter, MI_NOOP);
1110                 intel_ring_emit(waiter, MI_NOOP);
1111         }
1112         intel_ring_advance(waiter);
1113
1114         return 0;
1115 }
1116
1117 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
1118 do {                                                                    \
1119         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
1120                  PIPE_CONTROL_DEPTH_STALL);                             \
1121         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
1122         intel_ring_emit(ring__, 0);                                                     \
1123         intel_ring_emit(ring__, 0);                                                     \
1124 } while (0)
1125
1126 static int
1127 pc_render_add_request(struct intel_engine_cs *ring)
1128 {
1129         u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1130         int ret;
1131
1132         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1133          * incoherent with writes to memory, i.e. completely fubar,
1134          * so we need to use PIPE_NOTIFY instead.
1135          *
1136          * However, we also need to workaround the qword write
1137          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1138          * memory before requesting an interrupt.
1139          */
1140         ret = intel_ring_begin(ring, 32);
1141         if (ret)
1142                 return ret;
1143
1144         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1145                         PIPE_CONTROL_WRITE_FLUSH |
1146                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
1147         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1148         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1149         intel_ring_emit(ring, 0);
1150         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1151         scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
1152         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1153         scratch_addr += 2 * CACHELINE_BYTES;
1154         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1155         scratch_addr += 2 * CACHELINE_BYTES;
1156         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1157         scratch_addr += 2 * CACHELINE_BYTES;
1158         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1159         scratch_addr += 2 * CACHELINE_BYTES;
1160         PIPE_CONTROL_FLUSH(ring, scratch_addr);
1161
1162         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
1163                         PIPE_CONTROL_WRITE_FLUSH |
1164                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1165                         PIPE_CONTROL_NOTIFY);
1166         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1167         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1168         intel_ring_emit(ring, 0);
1169         __intel_ring_advance(ring);
1170
1171         return 0;
1172 }
1173
1174 static u32
1175 gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1176 {
1177         /* Workaround to force correct ordering between irq and seqno writes on
1178          * ivb (and maybe also on snb) by reading from a CS register (like
1179          * ACTHD) before reading the status page. */
1180         if (!lazy_coherency) {
1181                 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1182                 POSTING_READ(RING_ACTHD(ring->mmio_base));
1183         }
1184
1185         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1186 }
1187
1188 static u32
1189 ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1190 {
1191         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
1192 }
1193
1194 static void
1195 ring_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1196 {
1197         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
1198 }
1199
1200 static u32
1201 pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency)
1202 {
1203         return ring->scratch.cpu_page[0];
1204 }
1205
1206 static void
1207 pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno)
1208 {
1209         ring->scratch.cpu_page[0] = seqno;
1210 }
1211
1212 static bool
1213 gen5_ring_get_irq(struct intel_engine_cs *ring)
1214 {
1215         struct drm_device *dev = ring->dev;
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         unsigned long flags;
1218
1219         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1220                 return false;
1221
1222         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1223         if (ring->irq_refcount++ == 0)
1224                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1225         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1226
1227         return true;
1228 }
1229
1230 static void
1231 gen5_ring_put_irq(struct intel_engine_cs *ring)
1232 {
1233         struct drm_device *dev = ring->dev;
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         unsigned long flags;
1236
1237         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1238         if (--ring->irq_refcount == 0)
1239                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1240         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1241 }
1242
1243 static bool
1244 i9xx_ring_get_irq(struct intel_engine_cs *ring)
1245 {
1246         struct drm_device *dev = ring->dev;
1247         struct drm_i915_private *dev_priv = dev->dev_private;
1248         unsigned long flags;
1249
1250         if (!intel_irqs_enabled(dev_priv))
1251                 return false;
1252
1253         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1254         if (ring->irq_refcount++ == 0) {
1255                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1256                 I915_WRITE(IMR, dev_priv->irq_mask);
1257                 POSTING_READ(IMR);
1258         }
1259         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1260
1261         return true;
1262 }
1263
1264 static void
1265 i9xx_ring_put_irq(struct intel_engine_cs *ring)
1266 {
1267         struct drm_device *dev = ring->dev;
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269         unsigned long flags;
1270
1271         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1272         if (--ring->irq_refcount == 0) {
1273                 dev_priv->irq_mask |= ring->irq_enable_mask;
1274                 I915_WRITE(IMR, dev_priv->irq_mask);
1275                 POSTING_READ(IMR);
1276         }
1277         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1278 }
1279
1280 static bool
1281 i8xx_ring_get_irq(struct intel_engine_cs *ring)
1282 {
1283         struct drm_device *dev = ring->dev;
1284         struct drm_i915_private *dev_priv = dev->dev_private;
1285         unsigned long flags;
1286
1287         if (!intel_irqs_enabled(dev_priv))
1288                 return false;
1289
1290         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1291         if (ring->irq_refcount++ == 0) {
1292                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
1293                 I915_WRITE16(IMR, dev_priv->irq_mask);
1294                 POSTING_READ16(IMR);
1295         }
1296         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1297
1298         return true;
1299 }
1300
1301 static void
1302 i8xx_ring_put_irq(struct intel_engine_cs *ring)
1303 {
1304         struct drm_device *dev = ring->dev;
1305         struct drm_i915_private *dev_priv = dev->dev_private;
1306         unsigned long flags;
1307
1308         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1309         if (--ring->irq_refcount == 0) {
1310                 dev_priv->irq_mask |= ring->irq_enable_mask;
1311                 I915_WRITE16(IMR, dev_priv->irq_mask);
1312                 POSTING_READ16(IMR);
1313         }
1314         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1315 }
1316
1317 void intel_ring_setup_status_page(struct intel_engine_cs *ring)
1318 {
1319         struct drm_device *dev = ring->dev;
1320         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1321         u32 mmio = 0;
1322
1323         /* The ring status page addresses are no longer next to the rest of
1324          * the ring registers as of gen7.
1325          */
1326         if (IS_GEN7(dev)) {
1327                 switch (ring->id) {
1328                 case RCS:
1329                         mmio = RENDER_HWS_PGA_GEN7;
1330                         break;
1331                 case BCS:
1332                         mmio = BLT_HWS_PGA_GEN7;
1333                         break;
1334                 /*
1335                  * VCS2 actually doesn't exist on Gen7. Only shut up
1336                  * gcc switch check warning
1337                  */
1338                 case VCS2:
1339                 case VCS:
1340                         mmio = BSD_HWS_PGA_GEN7;
1341                         break;
1342                 case VECS:
1343                         mmio = VEBOX_HWS_PGA_GEN7;
1344                         break;
1345                 }
1346         } else if (IS_GEN6(ring->dev)) {
1347                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
1348         } else {
1349                 /* XXX: gen8 returns to sanity */
1350                 mmio = RING_HWS_PGA(ring->mmio_base);
1351         }
1352
1353         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
1354         POSTING_READ(mmio);
1355
1356         /*
1357          * Flush the TLB for this page
1358          *
1359          * FIXME: These two bits have disappeared on gen8, so a question
1360          * arises: do we still need this and if so how should we go about
1361          * invalidating the TLB?
1362          */
1363         if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
1364                 u32 reg = RING_INSTPM(ring->mmio_base);
1365
1366                 /* ring should be idle before issuing a sync flush*/
1367                 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0);
1368
1369                 I915_WRITE(reg,
1370                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
1371                                               INSTPM_SYNC_FLUSH));
1372                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
1373                              1000))
1374                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
1375                                   ring->name);
1376         }
1377 }
1378
1379 static int
1380 bsd_ring_flush(struct intel_engine_cs *ring,
1381                u32     invalidate_domains,
1382                u32     flush_domains)
1383 {
1384         int ret;
1385
1386         ret = intel_ring_begin(ring, 2);
1387         if (ret)
1388                 return ret;
1389
1390         intel_ring_emit(ring, MI_FLUSH);
1391         intel_ring_emit(ring, MI_NOOP);
1392         intel_ring_advance(ring);
1393         return 0;
1394 }
1395
1396 static int
1397 i9xx_add_request(struct intel_engine_cs *ring)
1398 {
1399         int ret;
1400
1401         ret = intel_ring_begin(ring, 4);
1402         if (ret)
1403                 return ret;
1404
1405         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1406         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1407         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1408         intel_ring_emit(ring, MI_USER_INTERRUPT);
1409         __intel_ring_advance(ring);
1410
1411         return 0;
1412 }
1413
1414 static bool
1415 gen6_ring_get_irq(struct intel_engine_cs *ring)
1416 {
1417         struct drm_device *dev = ring->dev;
1418         struct drm_i915_private *dev_priv = dev->dev_private;
1419         unsigned long flags;
1420
1421         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1422                 return false;
1423
1424         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1425         if (ring->irq_refcount++ == 0) {
1426                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1427                         I915_WRITE_IMR(ring,
1428                                        ~(ring->irq_enable_mask |
1429                                          GT_PARITY_ERROR(dev)));
1430                 else
1431                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1432                 gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1433         }
1434         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1435
1436         return true;
1437 }
1438
1439 static void
1440 gen6_ring_put_irq(struct intel_engine_cs *ring)
1441 {
1442         struct drm_device *dev = ring->dev;
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         unsigned long flags;
1445
1446         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1447         if (--ring->irq_refcount == 0) {
1448                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1449                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1450                 else
1451                         I915_WRITE_IMR(ring, ~0);
1452                 gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1453         }
1454         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1455 }
1456
1457 static bool
1458 hsw_vebox_get_irq(struct intel_engine_cs *ring)
1459 {
1460         struct drm_device *dev = ring->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         unsigned long flags;
1463
1464         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1465                 return false;
1466
1467         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1468         if (ring->irq_refcount++ == 0) {
1469                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1470                 gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1471         }
1472         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1473
1474         return true;
1475 }
1476
1477 static void
1478 hsw_vebox_put_irq(struct intel_engine_cs *ring)
1479 {
1480         struct drm_device *dev = ring->dev;
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         unsigned long flags;
1483
1484         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1485         if (--ring->irq_refcount == 0) {
1486                 I915_WRITE_IMR(ring, ~0);
1487                 gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1488         }
1489         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1490 }
1491
1492 static bool
1493 gen8_ring_get_irq(struct intel_engine_cs *ring)
1494 {
1495         struct drm_device *dev = ring->dev;
1496         struct drm_i915_private *dev_priv = dev->dev_private;
1497         unsigned long flags;
1498
1499         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1500                 return false;
1501
1502         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1503         if (ring->irq_refcount++ == 0) {
1504                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1505                         I915_WRITE_IMR(ring,
1506                                        ~(ring->irq_enable_mask |
1507                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1508                 } else {
1509                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1510                 }
1511                 POSTING_READ(RING_IMR(ring->mmio_base));
1512         }
1513         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1514
1515         return true;
1516 }
1517
1518 static void
1519 gen8_ring_put_irq(struct intel_engine_cs *ring)
1520 {
1521         struct drm_device *dev = ring->dev;
1522         struct drm_i915_private *dev_priv = dev->dev_private;
1523         unsigned long flags;
1524
1525         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1526         if (--ring->irq_refcount == 0) {
1527                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1528                         I915_WRITE_IMR(ring,
1529                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1530                 } else {
1531                         I915_WRITE_IMR(ring, ~0);
1532                 }
1533                 POSTING_READ(RING_IMR(ring->mmio_base));
1534         }
1535         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1536 }
1537
1538 static int
1539 i965_dispatch_execbuffer(struct intel_engine_cs *ring,
1540                          u64 offset, u32 length,
1541                          unsigned flags)
1542 {
1543         int ret;
1544
1545         ret = intel_ring_begin(ring, 2);
1546         if (ret)
1547                 return ret;
1548
1549         intel_ring_emit(ring,
1550                         MI_BATCH_BUFFER_START |
1551                         MI_BATCH_GTT |
1552                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1553         intel_ring_emit(ring, offset);
1554         intel_ring_advance(ring);
1555
1556         return 0;
1557 }
1558
1559 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1560 #define I830_BATCH_LIMIT (256*1024)
1561 #define I830_TLB_ENTRIES (2)
1562 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1563 static int
1564 i830_dispatch_execbuffer(struct intel_engine_cs *ring,
1565                                 u64 offset, u32 len,
1566                                 unsigned flags)
1567 {
1568         u32 cs_offset = ring->scratch.gtt_offset;
1569         int ret;
1570
1571         ret = intel_ring_begin(ring, 6);
1572         if (ret)
1573                 return ret;
1574
1575         /* Evict the invalid PTE TLBs */
1576         intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1577         intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1578         intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1579         intel_ring_emit(ring, cs_offset);
1580         intel_ring_emit(ring, 0xdeadbeef);
1581         intel_ring_emit(ring, MI_NOOP);
1582         intel_ring_advance(ring);
1583
1584         if ((flags & I915_DISPATCH_PINNED) == 0) {
1585                 if (len > I830_BATCH_LIMIT)
1586                         return -ENOSPC;
1587
1588                 ret = intel_ring_begin(ring, 6 + 2);
1589                 if (ret)
1590                         return ret;
1591
1592                 /* Blit the batch (which has now all relocs applied) to the
1593                  * stable batch scratch bo area (so that the CS never
1594                  * stumbles over its tlb invalidation bug) ...
1595                  */
1596                 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1597                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1598                 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1599                 intel_ring_emit(ring, cs_offset);
1600                 intel_ring_emit(ring, 4096);
1601                 intel_ring_emit(ring, offset);
1602
1603                 intel_ring_emit(ring, MI_FLUSH);
1604                 intel_ring_emit(ring, MI_NOOP);
1605                 intel_ring_advance(ring);
1606
1607                 /* ... and execute it. */
1608                 offset = cs_offset;
1609         }
1610
1611         ret = intel_ring_begin(ring, 4);
1612         if (ret)
1613                 return ret;
1614
1615         intel_ring_emit(ring, MI_BATCH_BUFFER);
1616         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1617         intel_ring_emit(ring, offset + len - 8);
1618         intel_ring_emit(ring, MI_NOOP);
1619         intel_ring_advance(ring);
1620
1621         return 0;
1622 }
1623
1624 static int
1625 i915_dispatch_execbuffer(struct intel_engine_cs *ring,
1626                          u64 offset, u32 len,
1627                          unsigned flags)
1628 {
1629         int ret;
1630
1631         ret = intel_ring_begin(ring, 2);
1632         if (ret)
1633                 return ret;
1634
1635         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1636         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1637         intel_ring_advance(ring);
1638
1639         return 0;
1640 }
1641
1642 static void cleanup_status_page(struct intel_engine_cs *ring)
1643 {
1644         struct drm_i915_gem_object *obj;
1645
1646         obj = ring->status_page.obj;
1647         if (obj == NULL)
1648                 return;
1649
1650         kunmap(sg_page(obj->pages->sgl));
1651         i915_gem_object_ggtt_unpin(obj);
1652         drm_gem_object_unreference(&obj->base);
1653         ring->status_page.obj = NULL;
1654 }
1655
1656 static int init_status_page(struct intel_engine_cs *ring)
1657 {
1658         struct drm_i915_gem_object *obj;
1659
1660         if ((obj = ring->status_page.obj) == NULL) {
1661                 unsigned flags;
1662                 int ret;
1663
1664                 obj = i915_gem_alloc_object(ring->dev, 4096);
1665                 if (obj == NULL) {
1666                         DRM_ERROR("Failed to allocate status page\n");
1667                         return -ENOMEM;
1668                 }
1669
1670                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1671                 if (ret)
1672                         goto err_unref;
1673
1674                 flags = 0;
1675                 if (!HAS_LLC(ring->dev))
1676                         /* On g33, we cannot place HWS above 256MiB, so
1677                          * restrict its pinning to the low mappable arena.
1678                          * Though this restriction is not documented for
1679                          * gen4, gen5, or byt, they also behave similarly
1680                          * and hang if the HWS is placed at the top of the
1681                          * GTT. To generalise, it appears that all !llc
1682                          * platforms have issues with us placing the HWS
1683                          * above the mappable region (even though we never
1684                          * actualy map it).
1685                          */
1686                         flags |= PIN_MAPPABLE;
1687                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1688                 if (ret) {
1689 err_unref:
1690                         drm_gem_object_unreference(&obj->base);
1691                         return ret;
1692                 }
1693
1694                 ring->status_page.obj = obj;
1695         }
1696
1697         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1698         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1699         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1700
1701         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1702                         ring->name, ring->status_page.gfx_addr);
1703
1704         return 0;
1705 }
1706
1707 static int init_phys_status_page(struct intel_engine_cs *ring)
1708 {
1709         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1710
1711         if (!dev_priv->status_page_dmah) {
1712                 dev_priv->status_page_dmah =
1713                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1714                 if (!dev_priv->status_page_dmah)
1715                         return -ENOMEM;
1716         }
1717
1718         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1719         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1720
1721         return 0;
1722 }
1723
1724 void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1725 {
1726         if (!ringbuf->obj)
1727                 return;
1728
1729         iounmap(ringbuf->virtual_start);
1730         i915_gem_object_ggtt_unpin(ringbuf->obj);
1731         drm_gem_object_unreference(&ringbuf->obj->base);
1732         ringbuf->obj = NULL;
1733 }
1734
1735 int intel_alloc_ringbuffer_obj(struct drm_device *dev,
1736                                struct intel_ringbuffer *ringbuf)
1737 {
1738         struct drm_i915_private *dev_priv = to_i915(dev);
1739         struct drm_i915_gem_object *obj;
1740         int ret;
1741
1742         if (ringbuf->obj)
1743                 return 0;
1744
1745         obj = NULL;
1746         if (!HAS_LLC(dev))
1747                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
1748         if (obj == NULL)
1749                 obj = i915_gem_alloc_object(dev, ringbuf->size);
1750         if (obj == NULL)
1751                 return -ENOMEM;
1752
1753         /* mark ring buffers as read-only from GPU side by default */
1754         obj->gt_ro = 1;
1755
1756         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1757         if (ret)
1758                 goto err_unref;
1759
1760         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1761         if (ret)
1762                 goto err_unpin;
1763
1764         ringbuf->virtual_start =
1765                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1766                                 ringbuf->size);
1767         if (ringbuf->virtual_start == NULL) {
1768                 ret = -EINVAL;
1769                 goto err_unpin;
1770         }
1771
1772         ringbuf->obj = obj;
1773         return 0;
1774
1775 err_unpin:
1776         i915_gem_object_ggtt_unpin(obj);
1777 err_unref:
1778         drm_gem_object_unreference(&obj->base);
1779         return ret;
1780 }
1781
1782 static int intel_init_ring_buffer(struct drm_device *dev,
1783                                   struct intel_engine_cs *ring)
1784 {
1785         struct intel_ringbuffer *ringbuf = ring->buffer;
1786         int ret;
1787
1788         if (ringbuf == NULL) {
1789                 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
1790                 if (!ringbuf)
1791                         return -ENOMEM;
1792                 ring->buffer = ringbuf;
1793         }
1794
1795         ring->dev = dev;
1796         INIT_LIST_HEAD(&ring->active_list);
1797         INIT_LIST_HEAD(&ring->request_list);
1798         INIT_LIST_HEAD(&ring->execlist_queue);
1799         ringbuf->size = 32 * PAGE_SIZE;
1800         ringbuf->ring = ring;
1801         memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
1802
1803         init_waitqueue_head(&ring->irq_queue);
1804
1805         if (I915_NEED_GFX_HWS(dev)) {
1806                 ret = init_status_page(ring);
1807                 if (ret)
1808                         goto error;
1809         } else {
1810                 BUG_ON(ring->id != RCS);
1811                 ret = init_phys_status_page(ring);
1812                 if (ret)
1813                         goto error;
1814         }
1815
1816         ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
1817         if (ret) {
1818                 DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", ring->name, ret);
1819                 goto error;
1820         }
1821
1822         /* Workaround an erratum on the i830 which causes a hang if
1823          * the TAIL pointer points to within the last 2 cachelines
1824          * of the buffer.
1825          */
1826         ringbuf->effective_size = ringbuf->size;
1827         if (IS_I830(dev) || IS_845G(dev))
1828                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
1829
1830         ret = i915_cmd_parser_init_ring(ring);
1831         if (ret)
1832                 goto error;
1833
1834         ret = ring->init(ring);
1835         if (ret)
1836                 goto error;
1837
1838         return 0;
1839
1840 error:
1841         kfree(ringbuf);
1842         ring->buffer = NULL;
1843         return ret;
1844 }
1845
1846 void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
1847 {
1848         struct drm_i915_private *dev_priv;
1849         struct intel_ringbuffer *ringbuf;
1850
1851         if (!intel_ring_initialized(ring))
1852                 return;
1853
1854         dev_priv = to_i915(ring->dev);
1855         ringbuf = ring->buffer;
1856
1857         intel_stop_ring_buffer(ring);
1858         WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0);
1859
1860         intel_destroy_ringbuffer_obj(ringbuf);
1861         ring->preallocated_lazy_request = NULL;
1862         ring->outstanding_lazy_seqno = 0;
1863
1864         if (ring->cleanup)
1865                 ring->cleanup(ring);
1866
1867         cleanup_status_page(ring);
1868
1869         i915_cmd_parser_fini_ring(ring);
1870
1871         kfree(ringbuf);
1872         ring->buffer = NULL;
1873 }
1874
1875 static int intel_ring_wait_request(struct intel_engine_cs *ring, int n)
1876 {
1877         struct intel_ringbuffer *ringbuf = ring->buffer;
1878         struct drm_i915_gem_request *request;
1879         u32 seqno = 0;
1880         int ret;
1881
1882         if (ringbuf->last_retired_head != -1) {
1883                 ringbuf->head = ringbuf->last_retired_head;
1884                 ringbuf->last_retired_head = -1;
1885
1886                 ringbuf->space = intel_ring_space(ringbuf);
1887                 if (ringbuf->space >= n)
1888                         return 0;
1889         }
1890
1891         list_for_each_entry(request, &ring->request_list, list) {
1892                 if (__intel_ring_space(request->tail, ringbuf->tail,
1893                                        ringbuf->size) >= n) {
1894                         seqno = request->seqno;
1895                         break;
1896                 }
1897         }
1898
1899         if (seqno == 0)
1900                 return -ENOSPC;
1901
1902         ret = i915_wait_seqno(ring, seqno);
1903         if (ret)
1904                 return ret;
1905
1906         i915_gem_retire_requests_ring(ring);
1907         ringbuf->head = ringbuf->last_retired_head;
1908         ringbuf->last_retired_head = -1;
1909
1910         ringbuf->space = intel_ring_space(ringbuf);
1911         return 0;
1912 }
1913
1914 static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
1915 {
1916         struct drm_device *dev = ring->dev;
1917         struct drm_i915_private *dev_priv = dev->dev_private;
1918         struct intel_ringbuffer *ringbuf = ring->buffer;
1919         unsigned long end;
1920         int ret;
1921
1922         ret = intel_ring_wait_request(ring, n);
1923         if (ret != -ENOSPC)
1924                 return ret;
1925
1926         /* force the tail write in case we have been skipping them */
1927         __intel_ring_advance(ring);
1928
1929         /* With GEM the hangcheck timer should kick us out of the loop,
1930          * leaving it early runs the risk of corrupting GEM state (due
1931          * to running on almost untested codepaths). But on resume
1932          * timers don't work yet, so prevent a complete hang in that
1933          * case by choosing an insanely large timeout. */
1934         end = jiffies + 60 * HZ;
1935
1936         trace_i915_ring_wait_begin(ring);
1937         do {
1938                 ringbuf->head = I915_READ_HEAD(ring);
1939                 ringbuf->space = intel_ring_space(ringbuf);
1940                 if (ringbuf->space >= n) {
1941                         ret = 0;
1942                         break;
1943                 }
1944
1945                 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1946                     dev->primary->master) {
1947                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1948                         if (master_priv->sarea_priv)
1949                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1950                 }
1951
1952                 msleep(1);
1953
1954                 if (dev_priv->mm.interruptible && signal_pending(current)) {
1955                         ret = -ERESTARTSYS;
1956                         break;
1957                 }
1958
1959                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1960                                            dev_priv->mm.interruptible);
1961                 if (ret)
1962                         break;
1963
1964                 if (time_after(jiffies, end)) {
1965                         ret = -EBUSY;
1966                         break;
1967                 }
1968         } while (1);
1969         trace_i915_ring_wait_end(ring);
1970         return ret;
1971 }
1972
1973 static int intel_wrap_ring_buffer(struct intel_engine_cs *ring)
1974 {
1975         uint32_t __iomem *virt;
1976         struct intel_ringbuffer *ringbuf = ring->buffer;
1977         int rem = ringbuf->size - ringbuf->tail;
1978
1979         if (ringbuf->space < rem) {
1980                 int ret = ring_wait_for_space(ring, rem);
1981                 if (ret)
1982                         return ret;
1983         }
1984
1985         virt = ringbuf->virtual_start + ringbuf->tail;
1986         rem /= 4;
1987         while (rem--)
1988                 iowrite32(MI_NOOP, virt++);
1989
1990         ringbuf->tail = 0;
1991         ringbuf->space = intel_ring_space(ringbuf);
1992
1993         return 0;
1994 }
1995
1996 int intel_ring_idle(struct intel_engine_cs *ring)
1997 {
1998         u32 seqno;
1999         int ret;
2000
2001         /* We need to add any requests required to flush the objects and ring */
2002         if (ring->outstanding_lazy_seqno) {
2003                 ret = i915_add_request(ring, NULL);
2004                 if (ret)
2005                         return ret;
2006         }
2007
2008         /* Wait upon the last request to be completed */
2009         if (list_empty(&ring->request_list))
2010                 return 0;
2011
2012         seqno = list_entry(ring->request_list.prev,
2013                            struct drm_i915_gem_request,
2014                            list)->seqno;
2015
2016         return i915_wait_seqno(ring, seqno);
2017 }
2018
2019 static int
2020 intel_ring_alloc_seqno(struct intel_engine_cs *ring)
2021 {
2022         if (ring->outstanding_lazy_seqno)
2023                 return 0;
2024
2025         if (ring->preallocated_lazy_request == NULL) {
2026                 struct drm_i915_gem_request *request;
2027
2028                 request = kmalloc(sizeof(*request), GFP_KERNEL);
2029                 if (request == NULL)
2030                         return -ENOMEM;
2031
2032                 ring->preallocated_lazy_request = request;
2033         }
2034
2035         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
2036 }
2037
2038 static int __intel_ring_prepare(struct intel_engine_cs *ring,
2039                                 int bytes)
2040 {
2041         struct intel_ringbuffer *ringbuf = ring->buffer;
2042         int ret;
2043
2044         if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) {
2045                 ret = intel_wrap_ring_buffer(ring);
2046                 if (unlikely(ret))
2047                         return ret;
2048         }
2049
2050         if (unlikely(ringbuf->space < bytes)) {
2051                 ret = ring_wait_for_space(ring, bytes);
2052                 if (unlikely(ret))
2053                         return ret;
2054         }
2055
2056         return 0;
2057 }
2058
2059 int intel_ring_begin(struct intel_engine_cs *ring,
2060                      int num_dwords)
2061 {
2062         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2063         int ret;
2064
2065         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2066                                    dev_priv->mm.interruptible);
2067         if (ret)
2068                 return ret;
2069
2070         ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
2071         if (ret)
2072                 return ret;
2073
2074         /* Preallocate the olr before touching the ring */
2075         ret = intel_ring_alloc_seqno(ring);
2076         if (ret)
2077                 return ret;
2078
2079         ring->buffer->space -= num_dwords * sizeof(uint32_t);
2080         return 0;
2081 }
2082
2083 /* Align the ring tail to a cacheline boundary */
2084 int intel_ring_cacheline_align(struct intel_engine_cs *ring)
2085 {
2086         int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2087         int ret;
2088
2089         if (num_dwords == 0)
2090                 return 0;
2091
2092         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2093         ret = intel_ring_begin(ring, num_dwords);
2094         if (ret)
2095                 return ret;
2096
2097         while (num_dwords--)
2098                 intel_ring_emit(ring, MI_NOOP);
2099
2100         intel_ring_advance(ring);
2101
2102         return 0;
2103 }
2104
2105 void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno)
2106 {
2107         struct drm_device *dev = ring->dev;
2108         struct drm_i915_private *dev_priv = dev->dev_private;
2109
2110         BUG_ON(ring->outstanding_lazy_seqno);
2111
2112         if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
2113                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
2114                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
2115                 if (HAS_VEBOX(dev))
2116                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
2117         }
2118
2119         ring->set_seqno(ring, seqno);
2120         ring->hangcheck.seqno = seqno;
2121 }
2122
2123 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
2124                                      u32 value)
2125 {
2126         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2127
2128        /* Every tail move must follow the sequence below */
2129
2130         /* Disable notification that the ring is IDLE. The GT
2131          * will then assume that it is busy and bring it out of rc6.
2132          */
2133         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2134                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2135
2136         /* Clear the context id. Here be magic! */
2137         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
2138
2139         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2140         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
2141                       GEN6_BSD_SLEEP_INDICATOR) == 0,
2142                      50))
2143                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2144
2145         /* Now that the ring is fully powered up, update the tail */
2146         I915_WRITE_TAIL(ring, value);
2147         POSTING_READ(RING_TAIL(ring->mmio_base));
2148
2149         /* Let the ring send IDLE messages to the GT again,
2150          * and so let it sleep to conserve power when idle.
2151          */
2152         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
2153                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2154 }
2155
2156 static int gen6_bsd_ring_flush(struct intel_engine_cs *ring,
2157                                u32 invalidate, u32 flush)
2158 {
2159         uint32_t cmd;
2160         int ret;
2161
2162         ret = intel_ring_begin(ring, 4);
2163         if (ret)
2164                 return ret;
2165
2166         cmd = MI_FLUSH_DW;
2167         if (INTEL_INFO(ring->dev)->gen >= 8)
2168                 cmd += 1;
2169         /*
2170          * Bspec vol 1c.5 - video engine command streamer:
2171          * "If ENABLED, all TLBs will be invalidated once the flush
2172          * operation is complete. This bit is only valid when the
2173          * Post-Sync Operation field is a value of 1h or 3h."
2174          */
2175         if (invalidate & I915_GEM_GPU_DOMAINS)
2176                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
2177                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2178         intel_ring_emit(ring, cmd);
2179         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2180         if (INTEL_INFO(ring->dev)->gen >= 8) {
2181                 intel_ring_emit(ring, 0); /* upper addr */
2182                 intel_ring_emit(ring, 0); /* value */
2183         } else  {
2184                 intel_ring_emit(ring, 0);
2185                 intel_ring_emit(ring, MI_NOOP);
2186         }
2187         intel_ring_advance(ring);
2188         return 0;
2189 }
2190
2191 static int
2192 gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2193                               u64 offset, u32 len,
2194                               unsigned flags)
2195 {
2196         bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE);
2197         int ret;
2198
2199         ret = intel_ring_begin(ring, 4);
2200         if (ret)
2201                 return ret;
2202
2203         /* FIXME(BDW): Address space and security selectors. */
2204         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
2205         intel_ring_emit(ring, lower_32_bits(offset));
2206         intel_ring_emit(ring, upper_32_bits(offset));
2207         intel_ring_emit(ring, MI_NOOP);
2208         intel_ring_advance(ring);
2209
2210         return 0;
2211 }
2212
2213 static int
2214 hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2215                               u64 offset, u32 len,
2216                               unsigned flags)
2217 {
2218         int ret;
2219
2220         ret = intel_ring_begin(ring, 2);
2221         if (ret)
2222                 return ret;
2223
2224         intel_ring_emit(ring,
2225                         MI_BATCH_BUFFER_START |
2226                         (flags & I915_DISPATCH_SECURE ?
2227                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
2228         /* bit0-7 is the length on GEN6+ */
2229         intel_ring_emit(ring, offset);
2230         intel_ring_advance(ring);
2231
2232         return 0;
2233 }
2234
2235 static int
2236 gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
2237                               u64 offset, u32 len,
2238                               unsigned flags)
2239 {
2240         int ret;
2241
2242         ret = intel_ring_begin(ring, 2);
2243         if (ret)
2244                 return ret;
2245
2246         intel_ring_emit(ring,
2247                         MI_BATCH_BUFFER_START |
2248                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
2249         /* bit0-7 is the length on GEN6+ */
2250         intel_ring_emit(ring, offset);
2251         intel_ring_advance(ring);
2252
2253         return 0;
2254 }
2255
2256 /* Blitter support (SandyBridge+) */
2257
2258 static int gen6_ring_flush(struct intel_engine_cs *ring,
2259                            u32 invalidate, u32 flush)
2260 {
2261         struct drm_device *dev = ring->dev;
2262         struct drm_i915_private *dev_priv = dev->dev_private;
2263         uint32_t cmd;
2264         int ret;
2265
2266         ret = intel_ring_begin(ring, 4);
2267         if (ret)
2268                 return ret;
2269
2270         cmd = MI_FLUSH_DW;
2271         if (INTEL_INFO(ring->dev)->gen >= 8)
2272                 cmd += 1;
2273         /*
2274          * Bspec vol 1c.3 - blitter engine command streamer:
2275          * "If ENABLED, all TLBs will be invalidated once the flush
2276          * operation is complete. This bit is only valid when the
2277          * Post-Sync Operation field is a value of 1h or 3h."
2278          */
2279         if (invalidate & I915_GEM_DOMAIN_RENDER)
2280                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
2281                         MI_FLUSH_DW_OP_STOREDW;
2282         intel_ring_emit(ring, cmd);
2283         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2284         if (INTEL_INFO(ring->dev)->gen >= 8) {
2285                 intel_ring_emit(ring, 0); /* upper addr */
2286                 intel_ring_emit(ring, 0); /* value */
2287         } else  {
2288                 intel_ring_emit(ring, 0);
2289                 intel_ring_emit(ring, MI_NOOP);
2290         }
2291         intel_ring_advance(ring);
2292
2293         if (!invalidate && flush) {
2294                 if (IS_GEN7(dev))
2295                         return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
2296                 else if (IS_BROADWELL(dev))
2297                         dev_priv->fbc.need_sw_cache_clean = true;
2298         }
2299
2300         return 0;
2301 }
2302
2303 int intel_init_render_ring_buffer(struct drm_device *dev)
2304 {
2305         struct drm_i915_private *dev_priv = dev->dev_private;
2306         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2307         struct drm_i915_gem_object *obj;
2308         int ret;
2309
2310         ring->name = "render ring";
2311         ring->id = RCS;
2312         ring->mmio_base = RENDER_RING_BASE;
2313
2314         if (INTEL_INFO(dev)->gen >= 8) {
2315                 if (i915_semaphore_is_enabled(dev)) {
2316                         obj = i915_gem_alloc_object(dev, 4096);
2317                         if (obj == NULL) {
2318                                 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2319                                 i915.semaphores = 0;
2320                         } else {
2321                                 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2322                                 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2323                                 if (ret != 0) {
2324                                         drm_gem_object_unreference(&obj->base);
2325                                         DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2326                                         i915.semaphores = 0;
2327                                 } else
2328                                         dev_priv->semaphore_obj = obj;
2329                         }
2330                 }
2331
2332                 ring->init_context = intel_ring_workarounds_emit;
2333                 ring->add_request = gen6_add_request;
2334                 ring->flush = gen8_render_ring_flush;
2335                 ring->irq_get = gen8_ring_get_irq;
2336                 ring->irq_put = gen8_ring_put_irq;
2337                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2338                 ring->get_seqno = gen6_ring_get_seqno;
2339                 ring->set_seqno = ring_set_seqno;
2340                 if (i915_semaphore_is_enabled(dev)) {
2341                         WARN_ON(!dev_priv->semaphore_obj);
2342                         ring->semaphore.sync_to = gen8_ring_sync;
2343                         ring->semaphore.signal = gen8_rcs_signal;
2344                         GEN8_RING_SEMAPHORE_INIT;
2345                 }
2346         } else if (INTEL_INFO(dev)->gen >= 6) {
2347                 ring->add_request = gen6_add_request;
2348                 ring->flush = gen7_render_ring_flush;
2349                 if (INTEL_INFO(dev)->gen == 6)
2350                         ring->flush = gen6_render_ring_flush;
2351                 ring->irq_get = gen6_ring_get_irq;
2352                 ring->irq_put = gen6_ring_put_irq;
2353                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2354                 ring->get_seqno = gen6_ring_get_seqno;
2355                 ring->set_seqno = ring_set_seqno;
2356                 if (i915_semaphore_is_enabled(dev)) {
2357                         ring->semaphore.sync_to = gen6_ring_sync;
2358                         ring->semaphore.signal = gen6_signal;
2359                         /*
2360                          * The current semaphore is only applied on pre-gen8
2361                          * platform.  And there is no VCS2 ring on the pre-gen8
2362                          * platform. So the semaphore between RCS and VCS2 is
2363                          * initialized as INVALID.  Gen8 will initialize the
2364                          * sema between VCS2 and RCS later.
2365                          */
2366                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2367                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2368                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2369                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2370                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2371                         ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2372                         ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2373                         ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2374                         ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2375                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2376                 }
2377         } else if (IS_GEN5(dev)) {
2378                 ring->add_request = pc_render_add_request;
2379                 ring->flush = gen4_render_ring_flush;
2380                 ring->get_seqno = pc_render_get_seqno;
2381                 ring->set_seqno = pc_render_set_seqno;
2382                 ring->irq_get = gen5_ring_get_irq;
2383                 ring->irq_put = gen5_ring_put_irq;
2384                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
2385                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
2386         } else {
2387                 ring->add_request = i9xx_add_request;
2388                 if (INTEL_INFO(dev)->gen < 4)
2389                         ring->flush = gen2_render_ring_flush;
2390                 else
2391                         ring->flush = gen4_render_ring_flush;
2392                 ring->get_seqno = ring_get_seqno;
2393                 ring->set_seqno = ring_set_seqno;
2394                 if (IS_GEN2(dev)) {
2395                         ring->irq_get = i8xx_ring_get_irq;
2396                         ring->irq_put = i8xx_ring_put_irq;
2397                 } else {
2398                         ring->irq_get = i9xx_ring_get_irq;
2399                         ring->irq_put = i9xx_ring_put_irq;
2400                 }
2401                 ring->irq_enable_mask = I915_USER_INTERRUPT;
2402         }
2403         ring->write_tail = ring_write_tail;
2404
2405         if (IS_HASWELL(dev))
2406                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2407         else if (IS_GEN8(dev))
2408                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2409         else if (INTEL_INFO(dev)->gen >= 6)
2410                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2411         else if (INTEL_INFO(dev)->gen >= 4)
2412                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2413         else if (IS_I830(dev) || IS_845G(dev))
2414                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2415         else
2416                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2417         ring->init = init_render_ring;
2418         ring->cleanup = render_ring_cleanup;
2419
2420         /* Workaround batchbuffer to combat CS tlb bug. */
2421         if (HAS_BROKEN_CS_TLB(dev)) {
2422                 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
2423                 if (obj == NULL) {
2424                         DRM_ERROR("Failed to allocate batch bo\n");
2425                         return -ENOMEM;
2426                 }
2427
2428                 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
2429                 if (ret != 0) {
2430                         drm_gem_object_unreference(&obj->base);
2431                         DRM_ERROR("Failed to ping batch bo\n");
2432                         return ret;
2433                 }
2434
2435                 ring->scratch.obj = obj;
2436                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
2437         }
2438
2439         return intel_init_ring_buffer(dev, ring);
2440 }
2441
2442 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
2443 {
2444         struct drm_i915_private *dev_priv = dev->dev_private;
2445         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
2446         struct intel_ringbuffer *ringbuf = ring->buffer;
2447         int ret;
2448
2449         if (ringbuf == NULL) {
2450                 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
2451                 if (!ringbuf)
2452                         return -ENOMEM;
2453                 ring->buffer = ringbuf;
2454         }
2455
2456         ring->name = "render ring";
2457         ring->id = RCS;
2458         ring->mmio_base = RENDER_RING_BASE;
2459
2460         if (INTEL_INFO(dev)->gen >= 6) {
2461                 /* non-kms not supported on gen6+ */
2462                 ret = -ENODEV;
2463                 goto err_ringbuf;
2464         }
2465
2466         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
2467          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
2468          * the special gen5 functions. */
2469         ring->add_request = i9xx_add_request;
2470         if (INTEL_INFO(dev)->gen < 4)
2471                 ring->flush = gen2_render_ring_flush;
2472         else
2473                 ring->flush = gen4_render_ring_flush;
2474         ring->get_seqno = ring_get_seqno;
2475         ring->set_seqno = ring_set_seqno;
2476         if (IS_GEN2(dev)) {
2477                 ring->irq_get = i8xx_ring_get_irq;
2478                 ring->irq_put = i8xx_ring_put_irq;
2479         } else {
2480                 ring->irq_get = i9xx_ring_get_irq;
2481                 ring->irq_put = i9xx_ring_put_irq;
2482         }
2483         ring->irq_enable_mask = I915_USER_INTERRUPT;
2484         ring->write_tail = ring_write_tail;
2485         if (INTEL_INFO(dev)->gen >= 4)
2486                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2487         else if (IS_I830(dev) || IS_845G(dev))
2488                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
2489         else
2490                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
2491         ring->init = init_render_ring;
2492         ring->cleanup = render_ring_cleanup;
2493
2494         ring->dev = dev;
2495         INIT_LIST_HEAD(&ring->active_list);
2496         INIT_LIST_HEAD(&ring->request_list);
2497
2498         ringbuf->size = size;
2499         ringbuf->effective_size = ringbuf->size;
2500         if (IS_I830(ring->dev) || IS_845G(ring->dev))
2501                 ringbuf->effective_size -= 2 * CACHELINE_BYTES;
2502
2503         ringbuf->virtual_start = ioremap_wc(start, size);
2504         if (ringbuf->virtual_start == NULL) {
2505                 DRM_ERROR("can not ioremap virtual address for"
2506                           " ring buffer\n");
2507                 ret = -ENOMEM;
2508                 goto err_ringbuf;
2509         }
2510
2511         if (!I915_NEED_GFX_HWS(dev)) {
2512                 ret = init_phys_status_page(ring);
2513                 if (ret)
2514                         goto err_vstart;
2515         }
2516
2517         return 0;
2518
2519 err_vstart:
2520         iounmap(ringbuf->virtual_start);
2521 err_ringbuf:
2522         kfree(ringbuf);
2523         ring->buffer = NULL;
2524         return ret;
2525 }
2526
2527 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2528 {
2529         struct drm_i915_private *dev_priv = dev->dev_private;
2530         struct intel_engine_cs *ring = &dev_priv->ring[VCS];
2531
2532         ring->name = "bsd ring";
2533         ring->id = VCS;
2534
2535         ring->write_tail = ring_write_tail;
2536         if (INTEL_INFO(dev)->gen >= 6) {
2537                 ring->mmio_base = GEN6_BSD_RING_BASE;
2538                 /* gen6 bsd needs a special wa for tail updates */
2539                 if (IS_GEN6(dev))
2540                         ring->write_tail = gen6_bsd_ring_write_tail;
2541                 ring->flush = gen6_bsd_ring_flush;
2542                 ring->add_request = gen6_add_request;
2543                 ring->get_seqno = gen6_ring_get_seqno;
2544                 ring->set_seqno = ring_set_seqno;
2545                 if (INTEL_INFO(dev)->gen >= 8) {
2546                         ring->irq_enable_mask =
2547                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2548                         ring->irq_get = gen8_ring_get_irq;
2549                         ring->irq_put = gen8_ring_put_irq;
2550                         ring->dispatch_execbuffer =
2551                                 gen8_ring_dispatch_execbuffer;
2552                         if (i915_semaphore_is_enabled(dev)) {
2553                                 ring->semaphore.sync_to = gen8_ring_sync;
2554                                 ring->semaphore.signal = gen8_xcs_signal;
2555                                 GEN8_RING_SEMAPHORE_INIT;
2556                         }
2557                 } else {
2558                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2559                         ring->irq_get = gen6_ring_get_irq;
2560                         ring->irq_put = gen6_ring_put_irq;
2561                         ring->dispatch_execbuffer =
2562                                 gen6_ring_dispatch_execbuffer;
2563                         if (i915_semaphore_is_enabled(dev)) {
2564                                 ring->semaphore.sync_to = gen6_ring_sync;
2565                                 ring->semaphore.signal = gen6_signal;
2566                                 ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2567                                 ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2568                                 ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2569                                 ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2570                                 ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2571                                 ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2572                                 ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2573                                 ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2574                                 ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2575                                 ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2576                         }
2577                 }
2578         } else {
2579                 ring->mmio_base = BSD_RING_BASE;
2580                 ring->flush = bsd_ring_flush;
2581                 ring->add_request = i9xx_add_request;
2582                 ring->get_seqno = ring_get_seqno;
2583                 ring->set_seqno = ring_set_seqno;
2584                 if (IS_GEN5(dev)) {
2585                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2586                         ring->irq_get = gen5_ring_get_irq;
2587                         ring->irq_put = gen5_ring_put_irq;
2588                 } else {
2589                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2590                         ring->irq_get = i9xx_ring_get_irq;
2591                         ring->irq_put = i9xx_ring_put_irq;
2592                 }
2593                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2594         }
2595         ring->init = init_ring_common;
2596
2597         return intel_init_ring_buffer(dev, ring);
2598 }
2599
2600 /**
2601  * Initialize the second BSD ring for Broadwell GT3.
2602  * It is noted that this only exists on Broadwell GT3.
2603  */
2604 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2605 {
2606         struct drm_i915_private *dev_priv = dev->dev_private;
2607         struct intel_engine_cs *ring = &dev_priv->ring[VCS2];
2608
2609         if ((INTEL_INFO(dev)->gen != 8)) {
2610                 DRM_ERROR("No dual-BSD ring on non-BDW machine\n");
2611                 return -EINVAL;
2612         }
2613
2614         ring->name = "bsd2 ring";
2615         ring->id = VCS2;
2616
2617         ring->write_tail = ring_write_tail;
2618         ring->mmio_base = GEN8_BSD2_RING_BASE;
2619         ring->flush = gen6_bsd_ring_flush;
2620         ring->add_request = gen6_add_request;
2621         ring->get_seqno = gen6_ring_get_seqno;
2622         ring->set_seqno = ring_set_seqno;
2623         ring->irq_enable_mask =
2624                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2625         ring->irq_get = gen8_ring_get_irq;
2626         ring->irq_put = gen8_ring_put_irq;
2627         ring->dispatch_execbuffer =
2628                         gen8_ring_dispatch_execbuffer;
2629         if (i915_semaphore_is_enabled(dev)) {
2630                 ring->semaphore.sync_to = gen8_ring_sync;
2631                 ring->semaphore.signal = gen8_xcs_signal;
2632                 GEN8_RING_SEMAPHORE_INIT;
2633         }
2634         ring->init = init_ring_common;
2635
2636         return intel_init_ring_buffer(dev, ring);
2637 }
2638
2639 int intel_init_blt_ring_buffer(struct drm_device *dev)
2640 {
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_engine_cs *ring = &dev_priv->ring[BCS];
2643
2644         ring->name = "blitter ring";
2645         ring->id = BCS;
2646
2647         ring->mmio_base = BLT_RING_BASE;
2648         ring->write_tail = ring_write_tail;
2649         ring->flush = gen6_ring_flush;
2650         ring->add_request = gen6_add_request;
2651         ring->get_seqno = gen6_ring_get_seqno;
2652         ring->set_seqno = ring_set_seqno;
2653         if (INTEL_INFO(dev)->gen >= 8) {
2654                 ring->irq_enable_mask =
2655                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2656                 ring->irq_get = gen8_ring_get_irq;
2657                 ring->irq_put = gen8_ring_put_irq;
2658                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2659                 if (i915_semaphore_is_enabled(dev)) {
2660                         ring->semaphore.sync_to = gen8_ring_sync;
2661                         ring->semaphore.signal = gen8_xcs_signal;
2662                         GEN8_RING_SEMAPHORE_INIT;
2663                 }
2664         } else {
2665                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2666                 ring->irq_get = gen6_ring_get_irq;
2667                 ring->irq_put = gen6_ring_put_irq;
2668                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2669                 if (i915_semaphore_is_enabled(dev)) {
2670                         ring->semaphore.signal = gen6_signal;
2671                         ring->semaphore.sync_to = gen6_ring_sync;
2672                         /*
2673                          * The current semaphore is only applied on pre-gen8
2674                          * platform.  And there is no VCS2 ring on the pre-gen8
2675                          * platform. So the semaphore between BCS and VCS2 is
2676                          * initialized as INVALID.  Gen8 will initialize the
2677                          * sema between BCS and VCS2 later.
2678                          */
2679                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
2680                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
2681                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2682                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
2683                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2684                         ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
2685                         ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
2686                         ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
2687                         ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
2688                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2689                 }
2690         }
2691         ring->init = init_ring_common;
2692
2693         return intel_init_ring_buffer(dev, ring);
2694 }
2695
2696 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2697 {
2698         struct drm_i915_private *dev_priv = dev->dev_private;
2699         struct intel_engine_cs *ring = &dev_priv->ring[VECS];
2700
2701         ring->name = "video enhancement ring";
2702         ring->id = VECS;
2703
2704         ring->mmio_base = VEBOX_RING_BASE;
2705         ring->write_tail = ring_write_tail;
2706         ring->flush = gen6_ring_flush;
2707         ring->add_request = gen6_add_request;
2708         ring->get_seqno = gen6_ring_get_seqno;
2709         ring->set_seqno = ring_set_seqno;
2710
2711         if (INTEL_INFO(dev)->gen >= 8) {
2712                 ring->irq_enable_mask =
2713                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2714                 ring->irq_get = gen8_ring_get_irq;
2715                 ring->irq_put = gen8_ring_put_irq;
2716                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2717                 if (i915_semaphore_is_enabled(dev)) {
2718                         ring->semaphore.sync_to = gen8_ring_sync;
2719                         ring->semaphore.signal = gen8_xcs_signal;
2720                         GEN8_RING_SEMAPHORE_INIT;
2721                 }
2722         } else {
2723                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2724                 ring->irq_get = hsw_vebox_get_irq;
2725                 ring->irq_put = hsw_vebox_put_irq;
2726                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2727                 if (i915_semaphore_is_enabled(dev)) {
2728                         ring->semaphore.sync_to = gen6_ring_sync;
2729                         ring->semaphore.signal = gen6_signal;
2730                         ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
2731                         ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
2732                         ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
2733                         ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2734                         ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2735                         ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
2736                         ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
2737                         ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
2738                         ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
2739                         ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
2740                 }
2741         }
2742         ring->init = init_ring_common;
2743
2744         return intel_init_ring_buffer(dev, ring);
2745 }
2746
2747 int
2748 intel_ring_flush_all_caches(struct intel_engine_cs *ring)
2749 {
2750         int ret;
2751
2752         if (!ring->gpu_caches_dirty)
2753                 return 0;
2754
2755         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2756         if (ret)
2757                 return ret;
2758
2759         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2760
2761         ring->gpu_caches_dirty = false;
2762         return 0;
2763 }
2764
2765 int
2766 intel_ring_invalidate_all_caches(struct intel_engine_cs *ring)
2767 {
2768         uint32_t flush_domains;
2769         int ret;
2770
2771         flush_domains = 0;
2772         if (ring->gpu_caches_dirty)
2773                 flush_domains = I915_GEM_GPU_DOMAINS;
2774
2775         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2776         if (ret)
2777                 return ret;
2778
2779         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2780
2781         ring->gpu_caches_dirty = false;
2782         return 0;
2783 }
2784
2785 void
2786 intel_stop_ring_buffer(struct intel_engine_cs *ring)
2787 {
2788         int ret;
2789
2790         if (!intel_ring_initialized(ring))
2791                 return;
2792
2793         ret = intel_ring_idle(ring);
2794         if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error))
2795                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
2796                           ring->name, ret);
2797
2798         stop_ring(ring);
2799 }