2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __ADRENO_GPU_H__
19 #define __ADRENO_GPU_H__
21 #include <linux/firmware.h>
25 #include "adreno_common.xml.h"
26 #include "adreno_pm4.xml.h"
35 #define ADRENO_REV(core, major, minor, patchid) \
36 ((struct adreno_rev){ core, major, minor, patchid })
38 struct adreno_gpu_funcs {
39 struct msm_gpu_funcs base;
43 struct adreno_rev rev;
46 const char *pm4fw, *pfpfw;
48 struct msm_gpu *(*init)(struct drm_device *dev);
51 const struct adreno_info *adreno_info(struct adreno_rev rev);
53 struct adreno_rbmemptrs {
54 volatile uint32_t rptr;
55 volatile uint32_t wptr;
56 volatile uint32_t fence;
61 struct adreno_rev rev;
62 const struct adreno_info *info;
63 uint32_t gmem; /* actual gmem size */
64 uint32_t revn; /* numeric revision name */
65 const struct adreno_gpu_funcs *funcs;
67 /* interesting register offsets to dump: */
68 const unsigned int *registers;
71 const struct firmware *pm4, *pfp;
73 /* ringbuffer rptr/wptr: */
74 // TODO should this be in msm_ringbuffer? I think it would be
75 // different for z180..
76 struct adreno_rbmemptrs *memptrs;
77 struct drm_gem_object *memptrs_bo;
78 uint32_t memptrs_iova;
80 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
82 /* platform config data (ie. from DT, or pdata) */
83 struct adreno_platform_config {
84 struct adreno_rev rev;
85 uint32_t fast_rate, slow_rate, bus_freq;
86 #ifdef CONFIG_MSM_BUS_SCALING
87 struct msm_bus_scale_pdata *bus_scale_table;
91 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
93 #define spin_until(X) ({ \
94 int __ret = -ETIMEDOUT; \
95 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
101 } while (time_before(jiffies, __t)); \
106 static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
108 return (gpu->revn >= 300) && (gpu->revn < 400);
111 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
113 return gpu->revn == 305;
116 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
118 return gpu->revn == 320;
121 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
123 return gpu->revn == 330;
126 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
128 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
131 int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
132 int adreno_hw_init(struct msm_gpu *gpu);
133 uint32_t adreno_last_fence(struct msm_gpu *gpu);
134 void adreno_recover(struct msm_gpu *gpu);
135 int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
136 struct msm_file_private *ctx);
137 void adreno_flush(struct msm_gpu *gpu);
138 void adreno_idle(struct msm_gpu *gpu);
139 #ifdef CONFIG_DEBUG_FS
140 void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
142 void adreno_dump(struct msm_gpu *gpu);
143 void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
145 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
146 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
147 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
150 /* ringbuffer helpers (the parts that are adreno specific) */
153 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
155 adreno_wait_ring(ring->gpu, cnt+1);
156 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
161 OUT_PKT2(struct msm_ringbuffer *ring)
163 adreno_wait_ring(ring->gpu, 1);
164 OUT_RING(ring, CP_TYPE2_PKT);
168 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
170 adreno_wait_ring(ring->gpu, cnt+1);
171 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
175 #endif /* __ADRENO_GPU_H__ */