drivers/gpu/drm/msm/dsi/dsi.xml.h

   1 #ifndef DSI_XML
   2 #define DSI_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/msm.xml                 (    676 bytes, from 2014-12-05 15:34:49)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml            (  20915 bytes, from 2015-03-24 22:05:22)
  14 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml      (   2352 bytes, from 2015-04-12 15:02:42)
  15 - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml            (  35083 bytes, from 2015-04-12 15:04:03)
  16 - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml             (  22094 bytes, from 2015-05-12 12:45:23)
  17 - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml            (    344 bytes, from 2013-08-11 19:26:32)
  18 - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml         (   1686 bytes, from 2014-10-31 16:48:57)
  19 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml         (    600 bytes, from 2013-07-05 19:21:12)
  20 - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml           (  29012 bytes, from 2015-05-12 12:45:23)
  21 - /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml             (  10416 bytes, from 2015-05-12 12:45:23)
  22
  23 Copyright (C) 2013-2015 by the following authors:
  24 - Rob Clark <robdclark@gmail.com> (robclark)
  25
  26 Permission is hereby granted, free of charge, to any person obtaining
  27 a copy of this software and associated documentation files (the
  28 "Software"), to deal in the Software without restriction, including
  29 without limitation the rights to use, copy, modify, merge, publish,
  30 distribute, sublicense, and/or sell copies of the Software, and to
  31 permit persons to whom the Software is furnished to do so, subject to
  32 the following conditions:
  33
  34 The above copyright notice and this permission notice (including the
  35 next paragraph) shall be included in all copies or substantial
  36 portions of the Software.
  37
  38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  40 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  41 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  42 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  43 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  44 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  45 */
  46
  47
  48 enum dsi_traffic_mode {
  49         NON_BURST_SYNCH_PULSE = 0,
  50         NON_BURST_SYNCH_EVENT = 1,
  51         BURST_MODE = 2,
  52 };
  53
  54 enum dsi_vid_dst_format {
  55         VID_DST_FORMAT_RGB565 = 0,
  56         VID_DST_FORMAT_RGB666 = 1,
  57         VID_DST_FORMAT_RGB666_LOOSE = 2,
  58         VID_DST_FORMAT_RGB888 = 3,
  59 };
  60
  61 enum dsi_rgb_swap {
  62         SWAP_RGB = 0,
  63         SWAP_RBG = 1,
  64         SWAP_BGR = 2,
  65         SWAP_BRG = 3,
  66         SWAP_GRB = 4,
  67         SWAP_GBR = 5,
  68 };
  69
  70 enum dsi_cmd_trigger {
  71         TRIGGER_NONE = 0,
  72         TRIGGER_SEOF = 1,
  73         TRIGGER_TE = 2,
  74         TRIGGER_SW = 4,
  75         TRIGGER_SW_SEOF = 5,
  76         TRIGGER_SW_TE = 6,
  77 };
  78
  79 enum dsi_cmd_dst_format {
  80         CMD_DST_FORMAT_RGB111 = 0,
  81         CMD_DST_FORMAT_RGB332 = 3,
  82         CMD_DST_FORMAT_RGB444 = 4,
  83         CMD_DST_FORMAT_RGB565 = 6,
  84         CMD_DST_FORMAT_RGB666 = 7,
  85         CMD_DST_FORMAT_RGB888 = 8,
  86 };
  87
  88 enum dsi_lane_swap {
  89         LANE_SWAP_0123 = 0,
  90         LANE_SWAP_3012 = 1,
  91         LANE_SWAP_2301 = 2,
  92         LANE_SWAP_1230 = 3,
  93         LANE_SWAP_0321 = 4,
  94         LANE_SWAP_1032 = 5,
  95         LANE_SWAP_2103 = 6,
  96         LANE_SWAP_3210 = 7,
  97 };
  98
  99 #define DSI_IRQ_CMD_DMA_DONE                                    0x00000001
 100 #define DSI_IRQ_MASK_CMD_DMA_DONE                               0x00000002
 101 #define DSI_IRQ_CMD_MDP_DONE                                    0x00000100
 102 #define DSI_IRQ_MASK_CMD_MDP_DONE                               0x00000200
 103 #define DSI_IRQ_VIDEO_DONE                                      0x00010000
 104 #define DSI_IRQ_MASK_VIDEO_DONE                                 0x00020000
 105 #define DSI_IRQ_BTA_DONE                                        0x00100000
 106 #define DSI_IRQ_MASK_BTA_DONE                                   0x00200000
 107 #define DSI_IRQ_ERROR                                           0x01000000
 108 #define DSI_IRQ_MASK_ERROR                                      0x02000000
 109 #define REG_DSI_6G_HW_VERSION                                   0x00000000
 110 #define DSI_6G_HW_VERSION_MAJOR__MASK                           0xf0000000
 111 #define DSI_6G_HW_VERSION_MAJOR__SHIFT                          28
 112 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)
 113 {
 114         return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK;
 115 }
 116 #define DSI_6G_HW_VERSION_MINOR__MASK                           0x0fff0000
 117 #define DSI_6G_HW_VERSION_MINOR__SHIFT                          16
 118 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)
 119 {
 120         return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK;
 121 }
 122 #define DSI_6G_HW_VERSION_STEP__MASK                            0x0000ffff
 123 #define DSI_6G_HW_VERSION_STEP__SHIFT                           0
 124 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
 125 {
 126         return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK;
 127 }
 128
 129 #define REG_DSI_CTRL                                            0x00000000
 130 #define DSI_CTRL_ENABLE                                         0x00000001
 131 #define DSI_CTRL_VID_MODE_EN                                    0x00000002
 132 #define DSI_CTRL_CMD_MODE_EN                                    0x00000004
 133 #define DSI_CTRL_LANE0                                          0x00000010
 134 #define DSI_CTRL_LANE1                                          0x00000020
 135 #define DSI_CTRL_LANE2                                          0x00000040
 136 #define DSI_CTRL_LANE3                                          0x00000080
 137 #define DSI_CTRL_CLK_EN                                         0x00000100
 138 #define DSI_CTRL_ECC_CHECK                                      0x00100000
 139 #define DSI_CTRL_CRC_CHECK                                      0x01000000
 140
 141 #define REG_DSI_STATUS0                                         0x00000004
 142 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY                        0x00000001
 143 #define DSI_STATUS0_CMD_MODE_DMA_BUSY                           0x00000002
 144 #define DSI_STATUS0_CMD_MODE_MDP_BUSY                           0x00000004
 145 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY                      0x00000008
 146 #define DSI_STATUS0_DSI_BUSY                                    0x00000010
 147 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION                    0x80000000
 148
 149 #define REG_DSI_FIFO_STATUS                                     0x00000008
 150 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW                  0x00000080
 151
 152 #define REG_DSI_VID_CFG0                                        0x0000000c
 153 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK                         0x00000003
 154 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT                        0
 155 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
 156 {
 157         return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
 158 }
 159 #define DSI_VID_CFG0_DST_FORMAT__MASK                           0x00000030
 160 #define DSI_VID_CFG0_DST_FORMAT__SHIFT                          4
 161 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)
 162 {
 163         return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
 164 }
 165 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK                         0x00000300
 166 #define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT                        8
 167 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
 168 {
 169         return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
 170 }
 171 #define DSI_VID_CFG0_BLLP_POWER_STOP                            0x00001000
 172 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP                        0x00008000
 173 #define DSI_VID_CFG0_HSA_POWER_STOP                             0x00010000
 174 #define DSI_VID_CFG0_HBP_POWER_STOP                             0x00100000
 175 #define DSI_VID_CFG0_HFP_POWER_STOP                             0x01000000
 176 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE                          0x10000000
 177
 178 #define REG_DSI_VID_CFG1                                        0x0000001c
 179 #define DSI_VID_CFG1_R_SEL                                      0x00000001
 180 #define DSI_VID_CFG1_G_SEL                                      0x00000010
 181 #define DSI_VID_CFG1_B_SEL                                      0x00000100
 182 #define DSI_VID_CFG1_RGB_SWAP__MASK                             0x00007000
 183 #define DSI_VID_CFG1_RGB_SWAP__SHIFT                            12
 184 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
 185 {
 186         return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
 187 }
 188
 189 #define REG_DSI_ACTIVE_H                                        0x00000020
 190 #define DSI_ACTIVE_H_START__MASK                                0x00000fff
 191 #define DSI_ACTIVE_H_START__SHIFT                               0
 192 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
 193 {
 194         return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
 195 }
 196 #define DSI_ACTIVE_H_END__MASK                                  0x0fff0000
 197 #define DSI_ACTIVE_H_END__SHIFT                                 16
 198 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
 199 {
 200         return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
 201 }
 202
 203 #define REG_DSI_ACTIVE_V                                        0x00000024
 204 #define DSI_ACTIVE_V_START__MASK                                0x00000fff
 205 #define DSI_ACTIVE_V_START__SHIFT                               0
 206 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
 207 {
 208         return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
 209 }
 210 #define DSI_ACTIVE_V_END__MASK                                  0x0fff0000
 211 #define DSI_ACTIVE_V_END__SHIFT                                 16
 212 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
 213 {
 214         return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
 215 }
 216
 217 #define REG_DSI_TOTAL                                           0x00000028
 218 #define DSI_TOTAL_H_TOTAL__MASK                                 0x00000fff
 219 #define DSI_TOTAL_H_TOTAL__SHIFT                                0
 220 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
 221 {
 222         return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
 223 }
 224 #define DSI_TOTAL_V_TOTAL__MASK                                 0x0fff0000
 225 #define DSI_TOTAL_V_TOTAL__SHIFT                                16
 226 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
 227 {
 228         return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
 229 }
 230
 231 #define REG_DSI_ACTIVE_HSYNC                                    0x0000002c
 232 #define DSI_ACTIVE_HSYNC_START__MASK                            0x00000fff
 233 #define DSI_ACTIVE_HSYNC_START__SHIFT                           0
 234 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
 235 {
 236         return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
 237 }
 238 #define DSI_ACTIVE_HSYNC_END__MASK                              0x0fff0000
 239 #define DSI_ACTIVE_HSYNC_END__SHIFT                             16
 240 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
 241 {
 242         return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
 243 }
 244
 245 #define REG_DSI_ACTIVE_VSYNC_HPOS                               0x00000030
 246 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK                       0x00000fff
 247 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT                      0
 248 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)
 249 {
 250         return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK;
 251 }
 252 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK                         0x0fff0000
 253 #define DSI_ACTIVE_VSYNC_HPOS_END__SHIFT                        16
 254 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)
 255 {
 256         return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK;
 257 }
 258
 259 #define REG_DSI_ACTIVE_VSYNC_VPOS                               0x00000034
 260 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK                       0x00000fff
 261 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT                      0
 262 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)
 263 {
 264         return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK;
 265 }
 266 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK                         0x0fff0000
 267 #define DSI_ACTIVE_VSYNC_VPOS_END__SHIFT                        16
 268 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)
 269 {
 270         return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK;
 271 }
 272
 273 #define REG_DSI_CMD_DMA_CTRL                                    0x00000038
 274 #define DSI_CMD_DMA_CTRL_BROADCAST_EN                           0x80000000
 275 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER                      0x10000000
 276 #define DSI_CMD_DMA_CTRL_LOW_POWER                              0x04000000
 277
 278 #define REG_DSI_CMD_CFG0                                        0x0000003c
 279 #define DSI_CMD_CFG0_DST_FORMAT__MASK                           0x0000000f
 280 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT                          0
 281 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)
 282 {
 283         return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK;
 284 }
 285 #define DSI_CMD_CFG0_R_SEL                                      0x00000010
 286 #define DSI_CMD_CFG0_G_SEL                                      0x00000100
 287 #define DSI_CMD_CFG0_B_SEL                                      0x00001000
 288 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK                       0x00f00000
 289 #define DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT                      20
 290 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)
 291 {
 292         return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK;
 293 }
 294 #define DSI_CMD_CFG0_RGB_SWAP__MASK                             0x00070000
 295 #define DSI_CMD_CFG0_RGB_SWAP__SHIFT                            16
 296 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)
 297 {
 298         return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK;
 299 }
 300
 301 #define REG_DSI_CMD_CFG1                                        0x00000040
 302 #define DSI_CMD_CFG1_WR_MEM_START__MASK                         0x000000ff
 303 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT                        0
 304 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)
 305 {
 306         return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK;
 307 }
 308 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK                      0x0000ff00
 309 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT                     8
 310 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
 311 {
 312         return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK;
 313 }
 314 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND                         0x00010000
 315
 316 #define REG_DSI_DMA_BASE                                        0x00000044
 317
 318 #define REG_DSI_DMA_LEN                                         0x00000048
 319
 320 #define REG_DSI_CMD_MDP_STREAM_CTRL                             0x00000054
 321 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK                 0x0000003f
 322 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT                0
 323 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
 324 {
 325         return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
 326 }
 327 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK           0x00000300
 328 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT          8
 329 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
 330 {
 331         return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
 332 }
 333 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK                0xffff0000
 334 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT               16
 335 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
 336 {
 337         return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
 338 }
 339
 340 #define REG_DSI_CMD_MDP_STREAM_TOTAL                            0x00000058
 341 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK                  0x00000fff
 342 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT                 0
 343 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
 344 {
 345         return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
 346 }
 347 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK                  0x0fff0000
 348 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT                 16
 349 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
 350 {
 351         return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
 352 }
 353
 354 #define REG_DSI_ACK_ERR_STATUS                                  0x00000064
 355
 356 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
 357
 358 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
 359
 360 #define REG_DSI_TRIG_CTRL                                       0x00000080
 361 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK                         0x00000007
 362 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT                        0
 363 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
 364 {
 365         return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
 366 }
 367 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK                         0x00000070
 368 #define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT                        4
 369 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
 370 {
 371         return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
 372 }
 373 #define DSI_TRIG_CTRL_STREAM__MASK                              0x00000300
 374 #define DSI_TRIG_CTRL_STREAM__SHIFT                             8
 375 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
 376 {
 377         return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK;
 378 }
 379 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME                    0x00001000
 380 #define DSI_TRIG_CTRL_TE                                        0x80000000
 381
 382 #define REG_DSI_TRIG_DMA                                        0x0000008c
 383
 384 #define REG_DSI_DLN0_PHY_ERR                                    0x000000b0
 385
 386 #define REG_DSI_TIMEOUT_STATUS                                  0x000000bc
 387
 388 #define REG_DSI_CLKOUT_TIMING_CTRL                              0x000000c0
 389 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK                  0x0000003f
 390 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT                 0
 391 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
 392 {
 393         return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
 394 }
 395 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK                 0x00003f00
 396 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT                8
 397 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
 398 {
 399         return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
 400 }
 401
 402 #define REG_DSI_EOT_PACKET_CTRL                                 0x000000c8
 403 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND                       0x00000001
 404 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE                       0x00000010
 405
 406 #define REG_DSI_LANE_CTRL                                       0x000000a8
 407 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST                    0x10000000
 408
 409 #define REG_DSI_LANE_SWAP_CTRL                                  0x000000ac
 410 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK                   0x00000007
 411 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT                  0
 412 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
 413 {
 414         return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK;
 415 }
 416
 417 #define REG_DSI_ERR_INT_MASK0                                   0x00000108
 418
 419 #define REG_DSI_INTR_CTRL                                       0x0000010c
 420
 421 #define REG_DSI_RESET                                           0x00000114
 422
 423 #define REG_DSI_CLK_CTRL                                        0x00000118
 424 #define DSI_CLK_CTRL_AHBS_HCLK_ON                               0x00000001
 425 #define DSI_CLK_CTRL_AHBM_SCLK_ON                               0x00000002
 426 #define DSI_CLK_CTRL_PCLK_ON                                    0x00000004
 427 #define DSI_CLK_CTRL_DSICLK_ON                                  0x00000008
 428 #define DSI_CLK_CTRL_BYTECLK_ON                                 0x00000010
 429 #define DSI_CLK_CTRL_ESCCLK_ON                                  0x00000020
 430 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK                     0x00000200
 431
 432 #define REG_DSI_CLK_STATUS                                      0x0000011c
 433 #define DSI_CLK_STATUS_PLL_UNLOCKED                             0x00010000
 434
 435 #define REG_DSI_PHY_RESET                                       0x00000128
 436 #define DSI_PHY_RESET_RESET                                     0x00000001
 437
 438 #define REG_DSI_RDBK_DATA_CTRL                                  0x000001d0
 439 #define DSI_RDBK_DATA_CTRL_COUNT__MASK                          0x00ff0000
 440 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT                         16
 441 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)
 442 {
 443         return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK;
 444 }
 445 #define DSI_RDBK_DATA_CTRL_CLR                                  0x00000001
 446
 447 #define REG_DSI_VERSION                                         0x000001f0
 448 #define DSI_VERSION_MAJOR__MASK                                 0xff000000
 449 #define DSI_VERSION_MAJOR__SHIFT                                24
 450 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
 451 {
 452         return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK;
 453 }
 454
 455 #define REG_DSI_PHY_PLL_CTRL_0                                  0x00000200
 456 #define DSI_PHY_PLL_CTRL_0_ENABLE                               0x00000001
 457
 458 #define REG_DSI_PHY_PLL_CTRL_1                                  0x00000204
 459
 460 #define REG_DSI_PHY_PLL_CTRL_2                                  0x00000208
 461
 462 #define REG_DSI_PHY_PLL_CTRL_3                                  0x0000020c
 463
 464 #define REG_DSI_PHY_PLL_CTRL_4                                  0x00000210
 465
 466 #define REG_DSI_PHY_PLL_CTRL_5                                  0x00000214
 467
 468 #define REG_DSI_PHY_PLL_CTRL_6                                  0x00000218
 469
 470 #define REG_DSI_PHY_PLL_CTRL_7                                  0x0000021c
 471
 472 #define REG_DSI_PHY_PLL_CTRL_8                                  0x00000220
 473
 474 #define REG_DSI_PHY_PLL_CTRL_9                                  0x00000224
 475
 476 #define REG_DSI_PHY_PLL_CTRL_10                                 0x00000228
 477
 478 #define REG_DSI_PHY_PLL_CTRL_11                                 0x0000022c
 479
 480 #define REG_DSI_PHY_PLL_CTRL_12                                 0x00000230
 481
 482 #define REG_DSI_PHY_PLL_CTRL_13                                 0x00000234
 483
 484 #define REG_DSI_PHY_PLL_CTRL_14                                 0x00000238
 485
 486 #define REG_DSI_PHY_PLL_CTRL_15                                 0x0000023c
 487
 488 #define REG_DSI_PHY_PLL_CTRL_16                                 0x00000240
 489
 490 #define REG_DSI_PHY_PLL_CTRL_17                                 0x00000244
 491
 492 #define REG_DSI_PHY_PLL_CTRL_18                                 0x00000248
 493
 494 #define REG_DSI_PHY_PLL_CTRL_19                                 0x0000024c
 495
 496 #define REG_DSI_PHY_PLL_CTRL_20                                 0x00000250
 497
 498 #define REG_DSI_PHY_PLL_STATUS                                  0x00000280
 499 #define DSI_PHY_PLL_STATUS_PLL_BUSY                             0x00000001
 500
 501 #define REG_DSI_8x60_PHY_TPA_CTRL_1                             0x00000258
 502
 503 #define REG_DSI_8x60_PHY_TPA_CTRL_2                             0x0000025c
 504
 505 #define REG_DSI_8x60_PHY_TIMING_CTRL_0                          0x00000260
 506
 507 #define REG_DSI_8x60_PHY_TIMING_CTRL_1                          0x00000264
 508
 509 #define REG_DSI_8x60_PHY_TIMING_CTRL_2                          0x00000268
 510
 511 #define REG_DSI_8x60_PHY_TIMING_CTRL_3                          0x0000026c
 512
 513 #define REG_DSI_8x60_PHY_TIMING_CTRL_4                          0x00000270
 514
 515 #define REG_DSI_8x60_PHY_TIMING_CTRL_5                          0x00000274
 516
 517 #define REG_DSI_8x60_PHY_TIMING_CTRL_6                          0x00000278
 518
 519 #define REG_DSI_8x60_PHY_TIMING_CTRL_7                          0x0000027c
 520
 521 #define REG_DSI_8x60_PHY_TIMING_CTRL_8                          0x00000280
 522
 523 #define REG_DSI_8x60_PHY_TIMING_CTRL_9                          0x00000284
 524
 525 #define REG_DSI_8x60_PHY_TIMING_CTRL_10                         0x00000288
 526
 527 #define REG_DSI_8x60_PHY_TIMING_CTRL_11                         0x0000028c
 528
 529 #define REG_DSI_8x60_PHY_CTRL_0                                 0x00000290
 530
 531 #define REG_DSI_8x60_PHY_CTRL_1                                 0x00000294
 532
 533 #define REG_DSI_8x60_PHY_CTRL_2                                 0x00000298
 534
 535 #define REG_DSI_8x60_PHY_CTRL_3                                 0x0000029c
 536
 537 #define REG_DSI_8x60_PHY_STRENGTH_0                             0x000002a0
 538
 539 #define REG_DSI_8x60_PHY_STRENGTH_1                             0x000002a4
 540
 541 #define REG_DSI_8x60_PHY_STRENGTH_2                             0x000002a8
 542
 543 #define REG_DSI_8x60_PHY_STRENGTH_3                             0x000002ac
 544
 545 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0                       0x000002cc
 546
 547 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1                       0x000002d0
 548
 549 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2                       0x000002d4
 550
 551 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3                       0x000002d8
 552
 553 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4                       0x000002dc
 554
 555 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER                         0x000000f0
 556
 557 #define REG_DSI_8x60_PHY_CAL_CTRL                               0x000000f4
 558
 559 #define REG_DSI_8x60_PHY_CAL_STATUS                             0x000000fc
 560 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY                        0x10000000
 561
 562 static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; }
 563
 564 static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; }
 565
 566 static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; }
 567
 568 static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; }
 569
 570 static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; }
 571
 572 static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; }
 573
 574 static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; }
 575
 576 #define REG_DSI_8960_PHY_LNCK_CFG_0                             0x00000400
 577
 578 #define REG_DSI_8960_PHY_LNCK_CFG_1                             0x00000404
 579
 580 #define REG_DSI_8960_PHY_LNCK_CFG_2                             0x00000408
 581
 582 #define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH                     0x0000040c
 583
 584 #define REG_DSI_8960_PHY_LNCK_TEST_STR0                         0x00000414
 585
 586 #define REG_DSI_8960_PHY_LNCK_TEST_STR1                         0x00000418
 587
 588 #define REG_DSI_8960_PHY_TIMING_CTRL_0                          0x00000440
 589
 590 #define REG_DSI_8960_PHY_TIMING_CTRL_1                          0x00000444
 591
 592 #define REG_DSI_8960_PHY_TIMING_CTRL_2                          0x00000448
 593
 594 #define REG_DSI_8960_PHY_TIMING_CTRL_3                          0x0000044c
 595
 596 #define REG_DSI_8960_PHY_TIMING_CTRL_4                          0x00000450
 597
 598 #define REG_DSI_8960_PHY_TIMING_CTRL_5                          0x00000454
 599
 600 #define REG_DSI_8960_PHY_TIMING_CTRL_6                          0x00000458
 601
 602 #define REG_DSI_8960_PHY_TIMING_CTRL_7                          0x0000045c
 603
 604 #define REG_DSI_8960_PHY_TIMING_CTRL_8                          0x00000460
 605
 606 #define REG_DSI_8960_PHY_TIMING_CTRL_9                          0x00000464
 607
 608 #define REG_DSI_8960_PHY_TIMING_CTRL_10                         0x00000468
 609
 610 #define REG_DSI_8960_PHY_TIMING_CTRL_11                         0x0000046c
 611
 612 #define REG_DSI_8960_PHY_CTRL_0                                 0x00000470
 613
 614 #define REG_DSI_8960_PHY_CTRL_1                                 0x00000474
 615
 616 #define REG_DSI_8960_PHY_CTRL_2                                 0x00000478
 617
 618 #define REG_DSI_8960_PHY_CTRL_3                                 0x0000047c
 619
 620 #define REG_DSI_8960_PHY_STRENGTH_0                             0x00000480
 621
 622 #define REG_DSI_8960_PHY_STRENGTH_1                             0x00000484
 623
 624 #define REG_DSI_8960_PHY_STRENGTH_2                             0x00000488
 625
 626 #define REG_DSI_8960_PHY_BIST_CTRL_0                            0x0000048c
 627
 628 #define REG_DSI_8960_PHY_BIST_CTRL_1                            0x00000490
 629
 630 #define REG_DSI_8960_PHY_BIST_CTRL_2                            0x00000494
 631
 632 #define REG_DSI_8960_PHY_BIST_CTRL_3                            0x00000498
 633
 634 #define REG_DSI_8960_PHY_BIST_CTRL_4                            0x0000049c
 635
 636 #define REG_DSI_8960_PHY_LDO_CTRL                               0x000004b0
 637
 638 #define REG_DSI_8960_PHY_REGULATOR_CTRL_0                       0x00000500
 639
 640 #define REG_DSI_8960_PHY_REGULATOR_CTRL_1                       0x00000504
 641
 642 #define REG_DSI_8960_PHY_REGULATOR_CTRL_2                       0x00000508
 643
 644 #define REG_DSI_8960_PHY_REGULATOR_CTRL_3                       0x0000050c
 645
 646 #define REG_DSI_8960_PHY_REGULATOR_CTRL_4                       0x00000510
 647
 648 #define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG                  0x00000518
 649
 650 #define REG_DSI_8960_PHY_CAL_HW_TRIGGER                         0x00000528
 651
 652 #define REG_DSI_8960_PHY_CAL_SW_CFG_0                           0x0000052c
 653
 654 #define REG_DSI_8960_PHY_CAL_SW_CFG_1                           0x00000530
 655
 656 #define REG_DSI_8960_PHY_CAL_SW_CFG_2                           0x00000534
 657
 658 #define REG_DSI_8960_PHY_CAL_HW_CFG_0                           0x00000538
 659
 660 #define REG_DSI_8960_PHY_CAL_HW_CFG_1                           0x0000053c
 661
 662 #define REG_DSI_8960_PHY_CAL_HW_CFG_2                           0x00000540
 663
 664 #define REG_DSI_8960_PHY_CAL_HW_CFG_3                           0x00000544
 665
 666 #define REG_DSI_8960_PHY_CAL_HW_CFG_4                           0x00000548
 667
 668 #define REG_DSI_8960_PHY_CAL_STATUS                             0x00000550
 669 #define DSI_8960_PHY_CAL_STATUS_CAL_BUSY                        0x00000010
 670
 671 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
 672
 673 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
 674
 675 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
 676
 677 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
 678
 679 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
 680
 681 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
 682
 683 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
 684
 685 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
 686
 687 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
 688
 689 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
 690
 691 #define REG_DSI_28nm_PHY_LNCK_CFG_0                             0x00000100
 692
 693 #define REG_DSI_28nm_PHY_LNCK_CFG_1                             0x00000104
 694
 695 #define REG_DSI_28nm_PHY_LNCK_CFG_2                             0x00000108
 696
 697 #define REG_DSI_28nm_PHY_LNCK_CFG_3                             0x0000010c
 698
 699 #define REG_DSI_28nm_PHY_LNCK_CFG_4                             0x00000110
 700
 701 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH                     0x00000114
 702
 703 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL                         0x00000118
 704
 705 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0                         0x0000011c
 706
 707 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1                         0x00000120
 708
 709 #define REG_DSI_28nm_PHY_TIMING_CTRL_0                          0x00000140
 710 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK               0x000000ff
 711 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT              0
 712 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
 713 {
 714         return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
 715 }
 716
 717 #define REG_DSI_28nm_PHY_TIMING_CTRL_1                          0x00000144
 718 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK              0x000000ff
 719 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT             0
 720 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
 721 {
 722         return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
 723 }
 724
 725 #define REG_DSI_28nm_PHY_TIMING_CTRL_2                          0x00000148
 726 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK            0x000000ff
 727 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT           0
 728 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
 729 {
 730         return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
 731 }
 732
 733 #define REG_DSI_28nm_PHY_TIMING_CTRL_3                          0x0000014c
 734 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8                   0x00000001
 735
 736 #define REG_DSI_28nm_PHY_TIMING_CTRL_4                          0x00000150
 737 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK                0x000000ff
 738 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT               0
 739 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
 740 {
 741         return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
 742 }
 743
 744 #define REG_DSI_28nm_PHY_TIMING_CTRL_5                          0x00000154
 745 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK                0x000000ff
 746 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT               0
 747 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
 748 {
 749         return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
 750 }
 751
 752 #define REG_DSI_28nm_PHY_TIMING_CTRL_6                          0x00000158
 753 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK             0x000000ff
 754 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT            0
 755 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
 756 {
 757         return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
 758 }
 759
 760 #define REG_DSI_28nm_PHY_TIMING_CTRL_7                          0x0000015c
 761 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK               0x000000ff
 762 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT              0
 763 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
 764 {
 765         return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
 766 }
 767
 768 #define REG_DSI_28nm_PHY_TIMING_CTRL_8                          0x00000160
 769 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK                0x000000ff
 770 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT               0
 771 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
 772 {
 773         return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
 774 }
 775
 776 #define REG_DSI_28nm_PHY_TIMING_CTRL_9                          0x00000164
 777 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK                  0x00000007
 778 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT                 0
 779 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
 780 {
 781         return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
 782 }
 783 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK                0x00000070
 784 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT               4
 785 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
 786 {
 787         return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
 788 }
 789
 790 #define REG_DSI_28nm_PHY_TIMING_CTRL_10                         0x00000168
 791 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK                0x00000007
 792 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT               0
 793 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
 794 {
 795         return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
 796 }
 797
 798 #define REG_DSI_28nm_PHY_TIMING_CTRL_11                         0x0000016c
 799 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK             0x000000ff
 800 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT            0
 801 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 802 {
 803         return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
 804 }
 805
 806 #define REG_DSI_28nm_PHY_CTRL_0                                 0x00000170
 807
 808 #define REG_DSI_28nm_PHY_CTRL_1                                 0x00000174
 809
 810 #define REG_DSI_28nm_PHY_CTRL_2                                 0x00000178
 811
 812 #define REG_DSI_28nm_PHY_CTRL_3                                 0x0000017c
 813
 814 #define REG_DSI_28nm_PHY_CTRL_4                                 0x00000180
 815
 816 #define REG_DSI_28nm_PHY_STRENGTH_0                             0x00000184
 817
 818 #define REG_DSI_28nm_PHY_STRENGTH_1                             0x00000188
 819
 820 #define REG_DSI_28nm_PHY_BIST_CTRL_0                            0x000001b4
 821
 822 #define REG_DSI_28nm_PHY_BIST_CTRL_1                            0x000001b8
 823
 824 #define REG_DSI_28nm_PHY_BIST_CTRL_2                            0x000001bc
 825
 826 #define REG_DSI_28nm_PHY_BIST_CTRL_3                            0x000001c0
 827
 828 #define REG_DSI_28nm_PHY_BIST_CTRL_4                            0x000001c4
 829
 830 #define REG_DSI_28nm_PHY_BIST_CTRL_5                            0x000001c8
 831
 832 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL                         0x000001d4
 833
 834 #define REG_DSI_28nm_PHY_LDO_CNTRL                              0x000001dc
 835
 836 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0                       0x00000000
 837
 838 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1                       0x00000004
 839
 840 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2                       0x00000008
 841
 842 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3                       0x0000000c
 843
 844 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4                       0x00000010
 845
 846 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5                       0x00000014
 847
 848 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG                  0x00000018
 849
 850 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG                         0x00000000
 851 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR                        0x00000001
 852
 853 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG                       0x00000004
 854
 855 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG                        0x00000008
 856
 857 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG                         0x0000000c
 858
 859 #define REG_DSI_28nm_PHY_PLL_VREG_CFG                           0x00000010
 860 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B             0x00000002
 861
 862 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG                         0x00000014
 863
 864 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG                           0x00000018
 865
 866 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG                           0x0000001c
 867
 868 #define REG_DSI_28nm_PHY_PLL_GLB_CFG                            0x00000020
 869 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B                    0x00000001
 870 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B                0x00000002
 871 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B             0x00000004
 872 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE                     0x00000008
 873
 874 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG                       0x00000024
 875
 876 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG                       0x00000028
 877
 878 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG                           0x0000002c
 879
 880 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG                          0x00000030
 881
 882 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG                          0x00000034
 883
 884 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0                           0x00000038
 885 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK                 0x0000003f
 886 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT                0
 887 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)
 888 {
 889         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK;
 890 }
 891 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP                           0x00000040
 892
 893 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1                           0x0000003c
 894 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK               0x0000003f
 895 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT              0
 896 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)
 897 {
 898         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK;
 899 }
 900 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK               0x00000040
 901 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT              6
 902 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)
 903 {
 904         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK;
 905 }
 906
 907 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2                           0x00000040
 908 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK           0x000000ff
 909 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT          0
 910 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)
 911 {
 912         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK;
 913 }
 914
 915 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3                           0x00000044
 916 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK          0x000000ff
 917 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT         0
 918 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)
 919 {
 920         return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK;
 921 }
 922
 923 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4                           0x00000048
 924
 925 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0                           0x0000004c
 926
 927 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1                           0x00000050
 928
 929 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2                           0x00000054
 930
 931 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3                           0x00000058
 932
 933 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0                         0x0000005c
 934
 935 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1                         0x00000060
 936
 937 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2                         0x00000064
 938
 939 #define REG_DSI_28nm_PHY_PLL_TEST_CFG                           0x00000068
 940 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET                  0x00000001
 941
 942 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0                           0x0000006c
 943
 944 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1                           0x00000070
 945
 946 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2                           0x00000074
 947
 948 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3                           0x00000078
 949
 950 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4                           0x0000007c
 951
 952 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5                           0x00000080
 953
 954 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6                           0x00000084
 955
 956 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7                           0x00000088
 957
 958 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8                           0x0000008c
 959
 960 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9                           0x00000090
 961
 962 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10                          0x00000094
 963
 964 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11                          0x00000098
 965
 966 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG                          0x0000009c
 967
 968 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL                      0x000000a0
 969
 970 #define REG_DSI_28nm_PHY_PLL_CTRL_42                            0x000000a4
 971
 972 #define REG_DSI_28nm_PHY_PLL_CTRL_43                            0x000000a8
 973
 974 #define REG_DSI_28nm_PHY_PLL_CTRL_44                            0x000000ac
 975
 976 #define REG_DSI_28nm_PHY_PLL_CTRL_45                            0x000000b0
 977
 978 #define REG_DSI_28nm_PHY_PLL_CTRL_46                            0x000000b4
 979
 980 #define REG_DSI_28nm_PHY_PLL_CTRL_47                            0x000000b8
 981
 982 #define REG_DSI_28nm_PHY_PLL_CTRL_48                            0x000000bc
 983
 984 #define REG_DSI_28nm_PHY_PLL_STATUS                             0x000000c0
 985 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY                         0x00000001
 986
 987 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0                         0x000000c4
 988
 989 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1                         0x000000c8
 990
 991 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2                         0x000000cc
 992
 993 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3                         0x000000d0
 994
 995 #define REG_DSI_28nm_PHY_PLL_CTRL_54                            0x000000d4
 996
 997
 998 #endif /* DSI_XML */