2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
20 struct hdmi_phy_8x74 {
25 #define to_hdmi_phy_8x74(x) container_of(x, struct hdmi_phy_8x74, base)
28 static void phy_write(struct hdmi_phy_8x74 *phy, u32 reg, u32 data)
30 msm_writel(data, phy->mmio + reg);
33 //static u32 phy_read(struct hdmi_phy_8x74 *phy, u32 reg)
35 // return msm_readl(phy->mmio + reg);
38 static void hdmi_phy_8x74_destroy(struct hdmi_phy *phy)
40 struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
44 static void hdmi_phy_8x74_reset(struct hdmi_phy *phy)
46 struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
47 struct hdmi *hdmi = phy_8x74->hdmi;
50 /* NOTE that HDMI_PHY_CTL is in core mmio, not phy mmio: */
52 val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL);
54 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
56 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
57 val & ~HDMI_PHY_CTRL_SW_RESET);
60 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
61 val | HDMI_PHY_CTRL_SW_RESET);
64 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
66 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
67 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
70 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
71 val | HDMI_PHY_CTRL_SW_RESET_PLL);
76 if (val & HDMI_PHY_CTRL_SW_RESET_LOW) {
78 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
79 val | HDMI_PHY_CTRL_SW_RESET);
82 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
83 val & ~HDMI_PHY_CTRL_SW_RESET);
86 if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) {
88 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
89 val | HDMI_PHY_CTRL_SW_RESET_PLL);
92 hdmi_write(hdmi, REG_HDMI_PHY_CTRL,
93 val & ~HDMI_PHY_CTRL_SW_RESET_PLL);
97 static void hdmi_phy_8x74_powerup(struct hdmi_phy *phy,
98 unsigned long int pixclock)
100 struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
102 phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG0, 0x1b);
103 phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG1, 0xf2);
104 phy_write(phy_8x74, REG_HDMI_8x74_BIST_CFG0, 0x0);
105 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN0, 0x0);
106 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN1, 0x0);
107 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN2, 0x0);
108 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN3, 0x0);
109 phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL1, 0x20);
112 static void hdmi_phy_8x74_powerdown(struct hdmi_phy *phy)
114 struct hdmi_phy_8x74 *phy_8x74 = to_hdmi_phy_8x74(phy);
115 phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL0, 0x7f);
118 static const struct hdmi_phy_funcs hdmi_phy_8x74_funcs = {
119 .destroy = hdmi_phy_8x74_destroy,
120 .reset = hdmi_phy_8x74_reset,
121 .powerup = hdmi_phy_8x74_powerup,
122 .powerdown = hdmi_phy_8x74_powerdown,
125 struct hdmi_phy *hdmi_phy_8x74_init(struct hdmi *hdmi)
127 struct hdmi_phy_8x74 *phy_8x74;
128 struct hdmi_phy *phy = NULL;
131 phy_8x74 = kzalloc(sizeof(*phy_8x74), GFP_KERNEL);
137 phy = &phy_8x74->base;
139 phy->funcs = &hdmi_phy_8x74_funcs;
141 phy_8x74->hdmi = hdmi;
143 /* for 8x74, the phy mmio is mapped separately: */
144 phy_8x74->mmio = msm_ioremap(hdmi->pdev,
145 "phy_physical", "HDMI_8x74");
146 if (IS_ERR(phy_8x74->mmio)) {
147 ret = PTR_ERR(phy_8x74->mmio);
155 hdmi_phy_8x74_destroy(phy);