drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "mdp4_kms.h"
  19
  20 #include <drm/drm_mode.h>
  21 #include "drm_crtc.h"
  22 #include "drm_crtc_helper.h"
  23 #include "drm_flip_work.h"
  24
  25 struct mdp4_crtc {
  26         struct drm_crtc base;
  27         char name[8];
  28         struct drm_plane *plane;
  29         struct drm_plane *planes[8];
  30         int id;
  31         int ovlp;
  32         enum mdp4_dma dma;
  33         bool enabled;
  34
  35         /* which mixer/encoder we route output to: */
  36         int mixer;
  37
  38         struct {
  39                 spinlock_t lock;
  40                 bool stale;
  41                 uint32_t width, height;
  42                 uint32_t x, y;
  43
  44                 /* next cursor to scan-out: */
  45                 uint32_t next_iova;
  46                 struct drm_gem_object *next_bo;
  47
  48                 /* current cursor being scanned out: */
  49                 struct drm_gem_object *scanout_bo;
  50         } cursor;
  51
  52
  53         /* if there is a pending flip, these will be non-null: */
  54         struct drm_pending_vblank_event *event;
  55         struct msm_fence_cb pageflip_cb;
  56
  57 #define PENDING_CURSOR 0x1
  58 #define PENDING_FLIP   0x2
  59         atomic_t pending;
  60
  61         /* the fb that we logically (from PoV of KMS API) hold a ref
  62          * to.  Which we may not yet be scanning out (we may still
  63          * be scanning out previous in case of page_flip while waiting
  64          * for gpu rendering to complete:
  65          */
  66         struct drm_framebuffer *fb;
  67
  68         /* the fb that we currently hold a scanout ref to: */
  69         struct drm_framebuffer *scanout_fb;
  70
  71         /* for unref'ing framebuffers after scanout completes: */
  72         struct drm_flip_work unref_fb_work;
  73
  74         /* for unref'ing cursor bo's after scanout completes: */
  75         struct drm_flip_work unref_cursor_work;
  76
  77         struct mdp_irq vblank;
  78         struct mdp_irq err;
  79 };
  80 #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base)
  81
  82 static struct mdp4_kms *get_kms(struct drm_crtc *crtc)
  83 {
  84         struct msm_drm_private *priv = crtc->dev->dev_private;
  85         return to_mdp4_kms(to_mdp_kms(priv->kms));
  86 }
  87
  88 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  89 {
  90         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  91
  92         atomic_or(pending, &mdp4_crtc->pending);
  93         mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank);
  94 }
  95
  96 static void crtc_flush(struct drm_crtc *crtc)
  97 {
  98         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
  99         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 100         uint32_t i, flush = 0;
 101
 102         for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
 103                 struct drm_plane *plane = mdp4_crtc->planes[i];
 104                 if (plane) {
 105                         enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
 106                         flush |= pipe2flush(pipe_id);
 107                 }
 108         }
 109         flush |= ovlp2flush(mdp4_crtc->ovlp);
 110
 111         DBG("%s: flush=%08x", mdp4_crtc->name, flush);
 112
 113         mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush);
 114 }
 115
 116 static void update_fb(struct drm_crtc *crtc, struct drm_framebuffer *new_fb)
 117 {
 118         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 119         struct drm_framebuffer *old_fb = mdp4_crtc->fb;
 120
 121         /* grab reference to incoming scanout fb: */
 122         drm_framebuffer_reference(new_fb);
 123         mdp4_crtc->base.primary->fb = new_fb;
 124         mdp4_crtc->fb = new_fb;
 125
 126         if (old_fb)
 127                 drm_flip_work_queue(&mdp4_crtc->unref_fb_work, old_fb);
 128 }
 129
 130 /* unlike update_fb(), take a ref to the new scanout fb *before* updating
 131  * plane, then call this.  Needed to ensure we don't unref the buffer that
 132  * is actually still being scanned out.
 133  *
 134  * Note that this whole thing goes away with atomic.. since we can defer
 135  * calling into driver until rendering is done.
 136  */
 137 static void update_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 138 {
 139         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 140
 141         /* flush updates, to make sure hw is updated to new scanout fb,
 142          * so that we can safely queue unref to current fb (ie. next
 143          * vblank we know hw is done w/ previous scanout_fb).
 144          */
 145         crtc_flush(crtc);
 146
 147         if (mdp4_crtc->scanout_fb)
 148                 drm_flip_work_queue(&mdp4_crtc->unref_fb_work,
 149                                 mdp4_crtc->scanout_fb);
 150
 151         mdp4_crtc->scanout_fb = fb;
 152
 153         /* enable vblank to complete flip: */
 154         request_pending(crtc, PENDING_FLIP);
 155 }
 156
 157 /* if file!=NULL, this is preclose potential cancel-flip path */
 158 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 159 {
 160         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 161         struct drm_device *dev = crtc->dev;
 162         struct drm_pending_vblank_event *event;
 163         unsigned long flags;
 164
 165         spin_lock_irqsave(&dev->event_lock, flags);
 166         event = mdp4_crtc->event;
 167         if (event) {
 168                 /* if regular vblank case (!file) or if cancel-flip from
 169                  * preclose on file that requested flip, then send the
 170                  * event:
 171                  */
 172                 if (!file || (event->base.file_priv == file)) {
 173                         mdp4_crtc->event = NULL;
 174                         drm_send_vblank_event(dev, mdp4_crtc->id, event);
 175                 }
 176         }
 177         spin_unlock_irqrestore(&dev->event_lock, flags);
 178 }
 179
 180 static void pageflip_cb(struct msm_fence_cb *cb)
 181 {
 182         struct mdp4_crtc *mdp4_crtc =
 183                 container_of(cb, struct mdp4_crtc, pageflip_cb);
 184         struct drm_crtc *crtc = &mdp4_crtc->base;
 185         struct drm_framebuffer *fb = crtc->primary->fb;
 186
 187         if (!fb)
 188                 return;
 189
 190         drm_framebuffer_reference(fb);
 191         mdp4_plane_set_scanout(mdp4_crtc->plane, fb);
 192         update_scanout(crtc, fb);
 193 }
 194
 195 static void unref_fb_worker(struct drm_flip_work *work, void *val)
 196 {
 197         struct mdp4_crtc *mdp4_crtc =
 198                 container_of(work, struct mdp4_crtc, unref_fb_work);
 199         struct drm_device *dev = mdp4_crtc->base.dev;
 200
 201         mutex_lock(&dev->mode_config.mutex);
 202         drm_framebuffer_unreference(val);
 203         mutex_unlock(&dev->mode_config.mutex);
 204 }
 205
 206 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 207 {
 208         struct mdp4_crtc *mdp4_crtc =
 209                 container_of(work, struct mdp4_crtc, unref_cursor_work);
 210         struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base);
 211
 212         msm_gem_put_iova(val, mdp4_kms->id);
 213         drm_gem_object_unreference_unlocked(val);
 214 }
 215
 216 static void mdp4_crtc_destroy(struct drm_crtc *crtc)
 217 {
 218         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 219
 220         drm_crtc_cleanup(crtc);
 221         drm_flip_work_cleanup(&mdp4_crtc->unref_fb_work);
 222         drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work);
 223
 224         kfree(mdp4_crtc);
 225 }
 226
 227 static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode)
 228 {
 229         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 230         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 231         bool enabled = (mode == DRM_MODE_DPMS_ON);
 232
 233         DBG("%s: mode=%d", mdp4_crtc->name, mode);
 234
 235         if (enabled != mdp4_crtc->enabled) {
 236                 if (enabled) {
 237                         mdp4_enable(mdp4_kms);
 238                         mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err);
 239                 } else {
 240                         mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err);
 241                         mdp4_disable(mdp4_kms);
 242                 }
 243                 mdp4_crtc->enabled = enabled;
 244         }
 245 }
 246
 247 static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc,
 248                 const struct drm_display_mode *mode,
 249                 struct drm_display_mode *adjusted_mode)
 250 {
 251         return true;
 252 }
 253
 254 static void blend_setup(struct drm_crtc *crtc)
 255 {
 256         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 257         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 258         int i, ovlp = mdp4_crtc->ovlp;
 259         uint32_t mixer_cfg = 0;
 260         static const enum mdp_mixer_stage_id stages[] = {
 261                         STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
 262         };
 263         /* statically (for now) map planes to mixer stage (z-order): */
 264         static const int idxs[] = {
 265                         [VG1]  = 1,
 266                         [VG2]  = 2,
 267                         [RGB1] = 0,
 268                         [RGB2] = 0,
 269                         [RGB3] = 0,
 270                         [VG3]  = 3,
 271                         [VG4]  = 4,
 272
 273         };
 274         bool alpha[4]= { false, false, false, false };
 275
 276         /* Don't rely on value read back from hw, but instead use our
 277          * own shadowed value.  Possibly disable/reenable looses the
 278          * previous value and goes back to power-on default?
 279          */
 280         mixer_cfg = mdp4_kms->mixer_cfg;
 281
 282         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0);
 283         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0);
 284         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0);
 285         mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0);
 286
 287         for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) {
 288                 struct drm_plane *plane = mdp4_crtc->planes[i];
 289                 if (plane) {
 290                         enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane);
 291                         int idx = idxs[pipe_id];
 292                         if (idx > 0) {
 293                                 const struct mdp_format *format =
 294                                         to_mdp_format(msm_framebuffer_format(plane->fb));
 295                                 alpha[idx-1] = format->alpha_enable;
 296                         }
 297                         mixer_cfg = mixercfg(mixer_cfg, mdp4_crtc->mixer,
 298                                         pipe_id, stages[idx]);
 299                 }
 300         }
 301
 302         /* this shouldn't happen.. and seems to cause underflow: */
 303         WARN_ON(!mixer_cfg);
 304
 305         for (i = 0; i < 4; i++) {
 306                 uint32_t op;
 307
 308                 if (alpha[i]) {
 309                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) |
 310                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) |
 311                                         MDP4_OVLP_STAGE_OP_BG_INV_ALPHA;
 312                 } else {
 313                         op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) |
 314                                         MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST);
 315                 }
 316
 317                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff);
 318                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00);
 319                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op);
 320                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1);
 321                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0);
 322                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0);
 323                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0);
 324                 mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0);
 325         }
 326
 327         mdp4_kms->mixer_cfg = mixer_cfg;
 328         mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg);
 329 }
 330
 331 static int mdp4_crtc_mode_set(struct drm_crtc *crtc,
 332                 struct drm_display_mode *mode,
 333                 struct drm_display_mode *adjusted_mode,
 334                 int x, int y,
 335                 struct drm_framebuffer *old_fb)
 336 {
 337         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 338         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 339         enum mdp4_dma dma = mdp4_crtc->dma;
 340         int ret, ovlp = mdp4_crtc->ovlp;
 341
 342         mode = adjusted_mode;
 343
 344         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 345                         mdp4_crtc->name, mode->base.id, mode->name,
 346                         mode->vrefresh, mode->clock,
 347                         mode->hdisplay, mode->hsync_start,
 348                         mode->hsync_end, mode->htotal,
 349                         mode->vdisplay, mode->vsync_start,
 350                         mode->vsync_end, mode->vtotal,
 351                         mode->type, mode->flags);
 352
 353         /* grab extra ref for update_scanout() */
 354         drm_framebuffer_reference(crtc->primary->fb);
 355
 356         ret = mdp4_plane_mode_set(mdp4_crtc->plane, crtc, crtc->primary->fb,
 357                         0, 0, mode->hdisplay, mode->vdisplay,
 358                         x << 16, y << 16,
 359                         mode->hdisplay << 16, mode->vdisplay << 16);
 360         if (ret) {
 361                 drm_framebuffer_unreference(crtc->primary->fb);
 362                 dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n",
 363                                 mdp4_crtc->name, ret);
 364                 return ret;
 365         }
 366
 367         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma),
 368                         MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) |
 369                         MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay));
 370
 371         /* take data from pipe: */
 372         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0);
 373         mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma),
 374                         crtc->primary->fb->pitches[0]);
 375         mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma),
 376                         MDP4_DMA_DST_SIZE_WIDTH(0) |
 377                         MDP4_DMA_DST_SIZE_HEIGHT(0));
 378
 379         mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0);
 380         mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp),
 381                         MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) |
 382                         MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay));
 383         mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp),
 384                         crtc->primary->fb->pitches[0]);
 385
 386         mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1);
 387
 388         if (dma == DMA_E) {
 389                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000);
 390                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000);
 391                 mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000);
 392         }
 393
 394         update_fb(crtc, crtc->primary->fb);
 395         update_scanout(crtc, crtc->primary->fb);
 396
 397         return 0;
 398 }
 399
 400 static void mdp4_crtc_prepare(struct drm_crtc *crtc)
 401 {
 402         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 403         DBG("%s", mdp4_crtc->name);
 404         /* make sure we hold a ref to mdp clks while setting up mode: */
 405         drm_crtc_vblank_get(crtc);
 406         mdp4_enable(get_kms(crtc));
 407         mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 408 }
 409
 410 static void mdp4_crtc_commit(struct drm_crtc *crtc)
 411 {
 412         mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 413         crtc_flush(crtc);
 414         /* drop the ref to mdp clk's that we got in prepare: */
 415         mdp4_disable(get_kms(crtc));
 416         drm_crtc_vblank_put(crtc);
 417 }
 418
 419 static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 420                 struct drm_framebuffer *old_fb)
 421 {
 422         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 423         struct drm_plane *plane = mdp4_crtc->plane;
 424         struct drm_display_mode *mode = &crtc->mode;
 425         int ret;
 426
 427         /* grab extra ref for update_scanout() */
 428         drm_framebuffer_reference(crtc->primary->fb);
 429
 430         ret = mdp4_plane_mode_set(plane, crtc, crtc->primary->fb,
 431                         0, 0, mode->hdisplay, mode->vdisplay,
 432                         x << 16, y << 16,
 433                         mode->hdisplay << 16, mode->vdisplay << 16);
 434         if (ret) {
 435                 drm_framebuffer_unreference(crtc->primary->fb);
 436                 return ret;
 437         }
 438
 439         update_fb(crtc, crtc->primary->fb);
 440         update_scanout(crtc, crtc->primary->fb);
 441
 442         return 0;
 443 }
 444
 445 static void mdp4_crtc_load_lut(struct drm_crtc *crtc)
 446 {
 447 }
 448
 449 static int mdp4_crtc_page_flip(struct drm_crtc *crtc,
 450                 struct drm_framebuffer *new_fb,
 451                 struct drm_pending_vblank_event *event,
 452                 uint32_t page_flip_flags)
 453 {
 454         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 455         struct drm_device *dev = crtc->dev;
 456         struct drm_gem_object *obj;
 457         unsigned long flags;
 458
 459         if (mdp4_crtc->event) {
 460                 dev_err(dev->dev, "already pending flip!\n");
 461                 return -EBUSY;
 462         }
 463
 464         obj = msm_framebuffer_bo(new_fb, 0);
 465
 466         spin_lock_irqsave(&dev->event_lock, flags);
 467         mdp4_crtc->event = event;
 468         spin_unlock_irqrestore(&dev->event_lock, flags);
 469
 470         update_fb(crtc, new_fb);
 471
 472         return msm_gem_queue_inactive_cb(obj, &mdp4_crtc->pageflip_cb);
 473 }
 474
 475 static int mdp4_crtc_set_property(struct drm_crtc *crtc,
 476                 struct drm_property *property, uint64_t val)
 477 {
 478         // XXX
 479         return -EINVAL;
 480 }
 481
 482 #define CURSOR_WIDTH 64
 483 #define CURSOR_HEIGHT 64
 484
 485 /* called from IRQ to update cursor related registers (if needed).  The
 486  * cursor registers, other than x/y position, appear not to be double
 487  * buffered, and changing them other than from vblank seems to trigger
 488  * underflow.
 489  */
 490 static void update_cursor(struct drm_crtc *crtc)
 491 {
 492         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 493         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 494         enum mdp4_dma dma = mdp4_crtc->dma;
 495         unsigned long flags;
 496
 497         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 498         if (mdp4_crtc->cursor.stale) {
 499                 struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;
 500                 struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;
 501                 uint32_t iova = mdp4_crtc->cursor.next_iova;
 502
 503                 if (next_bo) {
 504                         /* take a obj ref + iova ref when we start scanning out: */
 505                         drm_gem_object_reference(next_bo);
 506                         msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova);
 507
 508                         /* enable cursor: */
 509                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma),
 510                                         MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) |
 511                                         MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height));
 512                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova);
 513                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma),
 514                                         MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) |
 515                                         MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN);
 516                 } else {
 517                         /* disable cursor: */
 518                         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma),
 519                                         mdp4_kms->blank_cursor_iova);
 520                 }
 521
 522                 /* and drop the iova ref + obj rev when done scanning out: */
 523                 if (prev_bo)
 524                         drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo);
 525
 526                 mdp4_crtc->cursor.scanout_bo = next_bo;
 527                 mdp4_crtc->cursor.stale = false;
 528         }
 529
 530         mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma),
 531                         MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) |
 532                         MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y));
 533
 534         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 535 }
 536
 537 static int mdp4_crtc_cursor_set(struct drm_crtc *crtc,
 538                 struct drm_file *file_priv, uint32_t handle,
 539                 uint32_t width, uint32_t height)
 540 {
 541         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 542         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 543         struct drm_device *dev = crtc->dev;
 544         struct drm_gem_object *cursor_bo, *old_bo;
 545         unsigned long flags;
 546         uint32_t iova;
 547         int ret;
 548
 549         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 550                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 551                 return -EINVAL;
 552         }
 553
 554         if (handle) {
 555                 cursor_bo = drm_gem_object_lookup(dev, file_priv, handle);
 556                 if (!cursor_bo)
 557                         return -ENOENT;
 558         } else {
 559                 cursor_bo = NULL;
 560         }
 561
 562         if (cursor_bo) {
 563                 ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova);
 564                 if (ret)
 565                         goto fail;
 566         } else {
 567                 iova = 0;
 568         }
 569
 570         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 571         old_bo = mdp4_crtc->cursor.next_bo;
 572         mdp4_crtc->cursor.next_bo   = cursor_bo;
 573         mdp4_crtc->cursor.next_iova = iova;
 574         mdp4_crtc->cursor.width     = width;
 575         mdp4_crtc->cursor.height    = height;
 576         mdp4_crtc->cursor.stale     = true;
 577         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 578
 579         if (old_bo) {
 580                 /* drop our previous reference: */
 581                 drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, old_bo);
 582         }
 583
 584         request_pending(crtc, PENDING_CURSOR);
 585
 586         return 0;
 587
 588 fail:
 589         drm_gem_object_unreference_unlocked(cursor_bo);
 590         return ret;
 591 }
 592
 593 static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 594 {
 595         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 596         unsigned long flags;
 597
 598         spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags);
 599         mdp4_crtc->cursor.x = x;
 600         mdp4_crtc->cursor.y = y;
 601         spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags);
 602
 603         crtc_flush(crtc);
 604         request_pending(crtc, PENDING_CURSOR);
 605
 606         return 0;
 607 }
 608
 609 static const struct drm_crtc_funcs mdp4_crtc_funcs = {
 610         .set_config = drm_crtc_helper_set_config,
 611         .destroy = mdp4_crtc_destroy,
 612         .page_flip = mdp4_crtc_page_flip,
 613         .set_property = mdp4_crtc_set_property,
 614         .cursor_set = mdp4_crtc_cursor_set,
 615         .cursor_move = mdp4_crtc_cursor_move,
 616 };
 617
 618 static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = {
 619         .dpms = mdp4_crtc_dpms,
 620         .mode_fixup = mdp4_crtc_mode_fixup,
 621         .mode_set = mdp4_crtc_mode_set,
 622         .prepare = mdp4_crtc_prepare,
 623         .commit = mdp4_crtc_commit,
 624         .mode_set_base = mdp4_crtc_mode_set_base,
 625         .load_lut = mdp4_crtc_load_lut,
 626 };
 627
 628 static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 629 {
 630         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank);
 631         struct drm_crtc *crtc = &mdp4_crtc->base;
 632         struct msm_drm_private *priv = crtc->dev->dev_private;
 633         unsigned pending;
 634
 635         mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank);
 636
 637         pending = atomic_xchg(&mdp4_crtc->pending, 0);
 638
 639         if (pending & PENDING_FLIP) {
 640                 complete_flip(crtc, NULL);
 641                 drm_flip_work_commit(&mdp4_crtc->unref_fb_work, priv->wq);
 642         }
 643
 644         if (pending & PENDING_CURSOR) {
 645                 update_cursor(crtc);
 646                 drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq);
 647         }
 648 }
 649
 650 static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 651 {
 652         struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err);
 653         struct drm_crtc *crtc = &mdp4_crtc->base;
 654         DBG("%s: error: %08x", mdp4_crtc->name, irqstatus);
 655         crtc_flush(crtc);
 656 }
 657
 658 uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc)
 659 {
 660         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 661         return mdp4_crtc->vblank.irqmask;
 662 }
 663
 664 void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
 665 {
 666         DBG("cancel: %p", file);
 667         complete_flip(crtc, file);
 668 }
 669
 670 /* set dma config, ie. the format the encoder wants. */
 671 void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config)
 672 {
 673         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 674         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 675
 676         mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config);
 677 }
 678
 679 /* set interface for routing crtc->encoder: */
 680 void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer)
 681 {
 682         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 683         struct mdp4_kms *mdp4_kms = get_kms(crtc);
 684         uint32_t intf_sel;
 685
 686         intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL);
 687
 688         switch (mdp4_crtc->dma) {
 689         case DMA_P:
 690                 intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK;
 691                 intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf);
 692                 break;
 693         case DMA_S:
 694                 intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK;
 695                 intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf);
 696                 break;
 697         case DMA_E:
 698                 intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK;
 699                 intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf);
 700                 break;
 701         }
 702
 703         if (intf == INTF_DSI_VIDEO) {
 704                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD;
 705                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO;
 706         } else if (intf == INTF_DSI_CMD) {
 707                 intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO;
 708                 intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD;
 709         }
 710
 711         mdp4_crtc->mixer = mixer;
 712
 713         blend_setup(crtc);
 714
 715         DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel);
 716
 717         mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel);
 718 }
 719
 720 static void set_attach(struct drm_crtc *crtc, enum mdp4_pipe pipe_id,
 721                 struct drm_plane *plane)
 722 {
 723         struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc);
 724
 725         BUG_ON(pipe_id >= ARRAY_SIZE(mdp4_crtc->planes));
 726
 727         if (mdp4_crtc->planes[pipe_id] == plane)
 728                 return;
 729
 730         mdp4_crtc->planes[pipe_id] = plane;
 731         blend_setup(crtc);
 732         if (mdp4_crtc->enabled && (plane != mdp4_crtc->plane))
 733                 crtc_flush(crtc);
 734 }
 735
 736 void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane)
 737 {
 738         set_attach(crtc, mdp4_plane_pipe(plane), plane);
 739 }
 740
 741 void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane)
 742 {
 743         /* don't actually detatch our primary plane: */
 744         if (to_mdp4_crtc(crtc)->plane == plane)
 745                 return;
 746         set_attach(crtc, mdp4_plane_pipe(plane), NULL);
 747 }
 748
 749 static const char *dma_names[] = {
 750                 "DMA_P", "DMA_S", "DMA_E",
 751 };
 752
 753 /* initialize crtc */
 754 struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
 755                 struct drm_plane *plane, int id, int ovlp_id,
 756                 enum mdp4_dma dma_id)
 757 {
 758         struct drm_crtc *crtc = NULL;
 759         struct mdp4_crtc *mdp4_crtc;
 760         int ret;
 761
 762         mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL);
 763         if (!mdp4_crtc) {
 764                 ret = -ENOMEM;
 765                 goto fail;
 766         }
 767
 768         crtc = &mdp4_crtc->base;
 769
 770         mdp4_crtc->plane = plane;
 771         mdp4_crtc->id = id;
 772
 773         mdp4_crtc->ovlp = ovlp_id;
 774         mdp4_crtc->dma = dma_id;
 775
 776         mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma);
 777         mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq;
 778
 779         mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma);
 780         mdp4_crtc->err.irq = mdp4_crtc_err_irq;
 781
 782         snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d",
 783                         dma_names[dma_id], ovlp_id);
 784
 785         spin_lock_init(&mdp4_crtc->cursor.lock);
 786
 787         ret = drm_flip_work_init(&mdp4_crtc->unref_fb_work, 16,
 788                         "unref fb", unref_fb_worker);
 789         if (ret)
 790                 goto fail;
 791
 792         ret = drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 64,
 793                         "unref cursor", unref_cursor_worker);
 794
 795         INIT_FENCE_CB(&mdp4_crtc->pageflip_cb, pageflip_cb);
 796
 797         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs);
 798         drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs);
 799
 800         mdp4_plane_install_properties(mdp4_crtc->plane, &crtc->base);
 801
 802         return crtc;
 803
 804 fail:
 805         if (crtc)
 806                 mdp4_crtc_destroy(crtc);
 807
 808         return ERR_PTR(ret);
 809 }