drivers/gpu/drm/msm/mdp/mdp4/mdp4_dtv_encoder.c

   1 /*
   2  * Copyright (C) 2013 Red Hat
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "mdp4_kms.h"
  19
  20 #include "drm_crtc.h"
  21 #include "drm_crtc_helper.h"
  22
  23
  24 struct mdp4_dtv_encoder {
  25         struct drm_encoder base;
  26         struct clk *hdmi_clk;
  27         struct clk *mdp_clk;
  28         unsigned long int pixclock;
  29         bool enabled;
  30         uint32_t bsc;
  31 };
  32 #define to_mdp4_dtv_encoder(x) container_of(x, struct mdp4_dtv_encoder, base)
  33
  34 static struct mdp4_kms *get_kms(struct drm_encoder *encoder)
  35 {
  36         struct msm_drm_private *priv = encoder->dev->dev_private;
  37         return to_mdp4_kms(to_mdp_kms(priv->kms));
  38 }
  39
  40 #ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
  41 #include <mach/board.h>
  42 /* not ironically named at all.. no, really.. */
  43 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
  44 {
  45         struct drm_device *dev = mdp4_dtv_encoder->base.dev;
  46         struct lcdc_platform_data *dtv_pdata = mdp4_find_pdata("dtv.0");
  47
  48         if (!dtv_pdata) {
  49                 dev_err(dev->dev, "could not find dtv pdata\n");
  50                 return;
  51         }
  52
  53         if (dtv_pdata->bus_scale_table) {
  54                 mdp4_dtv_encoder->bsc = msm_bus_scale_register_client(
  55                                 dtv_pdata->bus_scale_table);
  56                 DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc);
  57                 DBG("lcdc_power_save: %p", dtv_pdata->lcdc_power_save);
  58                 if (dtv_pdata->lcdc_power_save)
  59                         dtv_pdata->lcdc_power_save(1);
  60         }
  61 }
  62
  63 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder)
  64 {
  65         if (mdp4_dtv_encoder->bsc) {
  66                 msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc);
  67                 mdp4_dtv_encoder->bsc = 0;
  68         }
  69 }
  70
  71 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx)
  72 {
  73         if (mdp4_dtv_encoder->bsc) {
  74                 DBG("set bus scaling: %d", idx);
  75                 msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx);
  76         }
  77 }
  78 #else
  79 static void bs_init(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
  80 static void bs_fini(struct mdp4_dtv_encoder *mdp4_dtv_encoder) {}
  81 static void bs_set(struct mdp4_dtv_encoder *mdp4_dtv_encoder, int idx) {}
  82 #endif
  83
  84 static void mdp4_dtv_encoder_destroy(struct drm_encoder *encoder)
  85 {
  86         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
  87         bs_fini(mdp4_dtv_encoder);
  88         drm_encoder_cleanup(encoder);
  89         kfree(mdp4_dtv_encoder);
  90 }
  91
  92 static const struct drm_encoder_funcs mdp4_dtv_encoder_funcs = {
  93         .destroy = mdp4_dtv_encoder_destroy,
  94 };
  95
  96 static void mdp4_dtv_encoder_mode_set(struct drm_encoder *encoder,
  97                 struct drm_display_mode *mode,
  98                 struct drm_display_mode *adjusted_mode)
  99 {
 100         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 101         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 102         uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
 103         uint32_t display_v_start, display_v_end;
 104         uint32_t hsync_start_x, hsync_end_x;
 105
 106         mode = adjusted_mode;
 107
 108         DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 109                         mode->base.id, mode->name,
 110                         mode->vrefresh, mode->clock,
 111                         mode->hdisplay, mode->hsync_start,
 112                         mode->hsync_end, mode->htotal,
 113                         mode->vdisplay, mode->vsync_start,
 114                         mode->vsync_end, mode->vtotal,
 115                         mode->type, mode->flags);
 116
 117         mdp4_dtv_encoder->pixclock = mode->clock * 1000;
 118
 119         DBG("pixclock=%lu", mdp4_dtv_encoder->pixclock);
 120
 121         ctrl_pol = 0;
 122         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 123                 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_HSYNC_LOW;
 124         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 125                 ctrl_pol |= MDP4_DTV_CTRL_POLARITY_VSYNC_LOW;
 126         /* probably need to get DATA_EN polarity from panel.. */
 127
 128         dtv_hsync_skew = 0;  /* get this from panel? */
 129
 130         hsync_start_x = (mode->htotal - mode->hsync_start);
 131         hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
 132
 133         vsync_period = mode->vtotal * mode->htotal;
 134         vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
 135         display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
 136         display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
 137
 138         mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_CTRL,
 139                         MDP4_DTV_HSYNC_CTRL_PULSEW(mode->hsync_end - mode->hsync_start) |
 140                         MDP4_DTV_HSYNC_CTRL_PERIOD(mode->htotal));
 141         mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_PERIOD, vsync_period);
 142         mdp4_write(mdp4_kms, REG_MDP4_DTV_VSYNC_LEN, vsync_len);
 143         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_HCTRL,
 144                         MDP4_DTV_DISPLAY_HCTRL_START(hsync_start_x) |
 145                         MDP4_DTV_DISPLAY_HCTRL_END(hsync_end_x));
 146         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VSTART, display_v_start);
 147         mdp4_write(mdp4_kms, REG_MDP4_DTV_DISPLAY_VEND, display_v_end);
 148         mdp4_write(mdp4_kms, REG_MDP4_DTV_BORDER_CLR, 0);
 149         mdp4_write(mdp4_kms, REG_MDP4_DTV_UNDERFLOW_CLR,
 150                         MDP4_DTV_UNDERFLOW_CLR_ENABLE_RECOVERY |
 151                         MDP4_DTV_UNDERFLOW_CLR_COLOR(0xff));
 152         mdp4_write(mdp4_kms, REG_MDP4_DTV_HSYNC_SKEW, dtv_hsync_skew);
 153         mdp4_write(mdp4_kms, REG_MDP4_DTV_CTRL_POLARITY, ctrl_pol);
 154         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_HCTL,
 155                         MDP4_DTV_ACTIVE_HCTL_START(0) |
 156                         MDP4_DTV_ACTIVE_HCTL_END(0));
 157         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VSTART, 0);
 158         mdp4_write(mdp4_kms, REG_MDP4_DTV_ACTIVE_VEND, 0);
 159 }
 160
 161 static void mdp4_dtv_encoder_disable(struct drm_encoder *encoder)
 162 {
 163         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 164         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 165
 166         if (WARN_ON(!mdp4_dtv_encoder->enabled))
 167                 return;
 168
 169         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
 170
 171         /*
 172          * Wait for a vsync so we know the ENABLE=0 latched before
 173          * the (connector) source of the vsync's gets disabled,
 174          * otherwise we end up in a funny state if we re-enable
 175          * before the disable latches, which results that some of
 176          * the settings changes for the new modeset (like new
 177          * scanout buffer) don't latch properly..
 178          */
 179         mdp_irq_wait(&mdp4_kms->base, MDP4_IRQ_EXTERNAL_VSYNC);
 180
 181         clk_disable_unprepare(mdp4_dtv_encoder->hdmi_clk);
 182         clk_disable_unprepare(mdp4_dtv_encoder->mdp_clk);
 183
 184         bs_set(mdp4_dtv_encoder, 0);
 185
 186         mdp4_dtv_encoder->enabled = false;
 187 }
 188
 189 static void mdp4_dtv_encoder_enable(struct drm_encoder *encoder)
 190 {
 191         struct drm_device *dev = encoder->dev;
 192         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 193         struct mdp4_kms *mdp4_kms = get_kms(encoder);
 194         unsigned long pc = mdp4_dtv_encoder->pixclock;
 195         int ret;
 196
 197         if (WARN_ON(mdp4_dtv_encoder->enabled))
 198                 return;
 199
 200         mdp4_crtc_set_config(encoder->crtc,
 201                         MDP4_DMA_CONFIG_R_BPC(BPC8) |
 202                         MDP4_DMA_CONFIG_G_BPC(BPC8) |
 203                         MDP4_DMA_CONFIG_B_BPC(BPC8) |
 204                         MDP4_DMA_CONFIG_PACK(0x21));
 205         mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 1);
 206
 207         bs_set(mdp4_dtv_encoder, 1);
 208
 209         DBG("setting mdp_clk=%lu", pc);
 210
 211         ret = clk_set_rate(mdp4_dtv_encoder->mdp_clk, pc);
 212         if (ret)
 213                 dev_err(dev->dev, "failed to set mdp_clk to %lu: %d\n",
 214                         pc, ret);
 215
 216         ret = clk_prepare_enable(mdp4_dtv_encoder->mdp_clk);
 217         if (ret)
 218                 dev_err(dev->dev, "failed to enabled mdp_clk: %d\n", ret);
 219
 220         ret = clk_prepare_enable(mdp4_dtv_encoder->hdmi_clk);
 221         if (ret)
 222                 dev_err(dev->dev, "failed to enable hdmi_clk: %d\n", ret);
 223
 224         mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 1);
 225
 226         mdp4_dtv_encoder->enabled = true;
 227 }
 228
 229 static const struct drm_encoder_helper_funcs mdp4_dtv_encoder_helper_funcs = {
 230         .mode_set = mdp4_dtv_encoder_mode_set,
 231         .enable = mdp4_dtv_encoder_enable,
 232         .disable = mdp4_dtv_encoder_disable,
 233 };
 234
 235 long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate)
 236 {
 237         struct mdp4_dtv_encoder *mdp4_dtv_encoder = to_mdp4_dtv_encoder(encoder);
 238         return clk_round_rate(mdp4_dtv_encoder->mdp_clk, rate);
 239 }
 240
 241 /* initialize encoder */
 242 struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev)
 243 {
 244         struct drm_encoder *encoder = NULL;
 245         struct mdp4_dtv_encoder *mdp4_dtv_encoder;
 246         int ret;
 247
 248         mdp4_dtv_encoder = kzalloc(sizeof(*mdp4_dtv_encoder), GFP_KERNEL);
 249         if (!mdp4_dtv_encoder) {
 250                 ret = -ENOMEM;
 251                 goto fail;
 252         }
 253
 254         encoder = &mdp4_dtv_encoder->base;
 255
 256         drm_encoder_init(dev, encoder, &mdp4_dtv_encoder_funcs,
 257                          DRM_MODE_ENCODER_TMDS, NULL);
 258         drm_encoder_helper_add(encoder, &mdp4_dtv_encoder_helper_funcs);
 259
 260         mdp4_dtv_encoder->hdmi_clk = devm_clk_get(dev->dev, "hdmi_clk");
 261         if (IS_ERR(mdp4_dtv_encoder->hdmi_clk)) {
 262                 dev_err(dev->dev, "failed to get hdmi_clk\n");
 263                 ret = PTR_ERR(mdp4_dtv_encoder->hdmi_clk);
 264                 goto fail;
 265         }
 266
 267         mdp4_dtv_encoder->mdp_clk = devm_clk_get(dev->dev, "tv_clk");
 268         if (IS_ERR(mdp4_dtv_encoder->mdp_clk)) {
 269                 dev_err(dev->dev, "failed to get tv_clk\n");
 270                 ret = PTR_ERR(mdp4_dtv_encoder->mdp_clk);
 271                 goto fail;
 272         }
 273
 274         bs_init(mdp4_dtv_encoder);
 275
 276         return encoder;
 277
 278 fail:
 279         if (encoder)
 280                 mdp4_dtv_encoder_destroy(encoder);
 281
 282         return ERR_PTR(ret);
 283 }