drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

   1 /*
   2  * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "mdp5_kms.h"
  20
  21 #include <linux/sort.h>
  22 #include <drm/drm_mode.h>
  23 #include "drm_crtc.h"
  24 #include "drm_crtc_helper.h"
  25 #include "drm_flip_work.h"
  26
  27 #define CURSOR_WIDTH    64
  28 #define CURSOR_HEIGHT   64
  29
  30 #define SSPP_MAX        (SSPP_RGB3 + 1) /* TODO: Add SSPP_MAX in mdp5.xml.h */
  31
  32 struct mdp5_crtc {
  33         struct drm_crtc base;
  34         char name[8];
  35         int id;
  36         bool enabled;
  37
  38         /* layer mixer used for this CRTC (+ its lock): */
  39 #define GET_LM_ID(crtc_id)      ((crtc_id == 3) ? 5 : crtc_id)
  40         int lm;
  41         spinlock_t lm_lock;     /* protect REG_MDP5_LM_* registers */
  42
  43         /* CTL used for this CRTC: */
  44         struct mdp5_ctl *ctl;
  45
  46         /* if there is a pending flip, these will be non-null: */
  47         struct drm_pending_vblank_event *event;
  48
  49         /* Bits have been flushed at the last commit,
  50          * used to decide if a vsync has happened since last commit.
  51          */
  52         u32 flushed_mask;
  53
  54 #define PENDING_CURSOR 0x1
  55 #define PENDING_FLIP   0x2
  56         atomic_t pending;
  57
  58         /* for unref'ing cursor bo's after scanout completes: */
  59         struct drm_flip_work unref_cursor_work;
  60
  61         struct mdp_irq vblank;
  62         struct mdp_irq err;
  63         struct mdp_irq pp_done;
  64
  65         struct completion pp_completion;
  66
  67         bool cmd_mode;
  68
  69         struct {
  70                 /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/
  71                 spinlock_t lock;
  72
  73                 /* current cursor being scanned out: */
  74                 struct drm_gem_object *scanout_bo;
  75                 uint32_t width, height;
  76                 uint32_t x, y;
  77         } cursor;
  78 };
  79 #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base)
  80
  81 static struct mdp5_kms *get_kms(struct drm_crtc *crtc)
  82 {
  83         struct msm_drm_private *priv = crtc->dev->dev_private;
  84         return to_mdp5_kms(to_mdp_kms(priv->kms));
  85 }
  86
  87 static void request_pending(struct drm_crtc *crtc, uint32_t pending)
  88 {
  89         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  90
  91         atomic_or(pending, &mdp5_crtc->pending);
  92         mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank);
  93 }
  94
  95 static void request_pp_done_pending(struct drm_crtc *crtc)
  96 {
  97         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
  98         reinit_completion(&mdp5_crtc->pp_completion);
  99 }
 100
 101 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask)
 102 {
 103         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 104
 105         DBG("%s: flush=%08x", mdp5_crtc->name, flush_mask);
 106         return mdp5_ctl_commit(mdp5_crtc->ctl, flush_mask);
 107 }
 108
 109 /*
 110  * flush updates, to make sure hw is updated to new scanout fb,
 111  * so that we can safely queue unref to current fb (ie. next
 112  * vblank we know hw is done w/ previous scanout_fb).
 113  */
 114 static u32 crtc_flush_all(struct drm_crtc *crtc)
 115 {
 116         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 117         struct drm_plane *plane;
 118         uint32_t flush_mask = 0;
 119
 120         /* this should not happen: */
 121         if (WARN_ON(!mdp5_crtc->ctl))
 122                 return 0;
 123
 124         drm_atomic_crtc_for_each_plane(plane, crtc) {
 125                 flush_mask |= mdp5_plane_get_flush(plane);
 126         }
 127
 128         flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm);
 129
 130         return crtc_flush(crtc, flush_mask);
 131 }
 132
 133 /* if file!=NULL, this is preclose potential cancel-flip path */
 134 static void complete_flip(struct drm_crtc *crtc, struct drm_file *file)
 135 {
 136         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 137         struct drm_device *dev = crtc->dev;
 138         struct drm_pending_vblank_event *event;
 139         struct drm_plane *plane;
 140         unsigned long flags;
 141
 142         spin_lock_irqsave(&dev->event_lock, flags);
 143         event = mdp5_crtc->event;
 144         if (event) {
 145                 /* if regular vblank case (!file) or if cancel-flip from
 146                  * preclose on file that requested flip, then send the
 147                  * event:
 148                  */
 149                 if (!file || (event->base.file_priv == file)) {
 150                         mdp5_crtc->event = NULL;
 151                         DBG("%s: send event: %p", mdp5_crtc->name, event);
 152                         drm_send_vblank_event(dev, mdp5_crtc->id, event);
 153                 }
 154         }
 155         spin_unlock_irqrestore(&dev->event_lock, flags);
 156
 157         drm_atomic_crtc_for_each_plane(plane, crtc) {
 158                 mdp5_plane_complete_flip(plane);
 159         }
 160
 161         if (mdp5_crtc->ctl && !crtc->state->enable) {
 162                 /* set STAGE_UNUSED for all layers */
 163                 mdp5_ctl_blend(mdp5_crtc->ctl, mdp5_crtc->lm, 0x00000000);
 164                 mdp5_ctl_release(mdp5_crtc->ctl);
 165                 mdp5_crtc->ctl = NULL;
 166         }
 167 }
 168
 169 static void unref_cursor_worker(struct drm_flip_work *work, void *val)
 170 {
 171         struct mdp5_crtc *mdp5_crtc =
 172                 container_of(work, struct mdp5_crtc, unref_cursor_work);
 173         struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base);
 174
 175         msm_gem_put_iova(val, mdp5_kms->id);
 176         drm_gem_object_unreference_unlocked(val);
 177 }
 178
 179 static void mdp5_crtc_destroy(struct drm_crtc *crtc)
 180 {
 181         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 182
 183         drm_crtc_cleanup(crtc);
 184         drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work);
 185
 186         kfree(mdp5_crtc);
 187 }
 188
 189 static bool mdp5_crtc_mode_fixup(struct drm_crtc *crtc,
 190                 const struct drm_display_mode *mode,
 191                 struct drm_display_mode *adjusted_mode)
 192 {
 193         return true;
 194 }
 195
 196 /*
 197  * blend_setup() - blend all the planes of a CRTC
 198  *
 199  * When border is enabled, the border color will ALWAYS be the base layer.
 200  * Therefore, the first plane (private RGB pipe) will start at STAGE0.
 201  * If disabled, the first plane starts at STAGE_BASE.
 202  *
 203  * Note:
 204  * Border is not enabled here because the private plane is exactly
 205  * the CRTC resolution.
 206  */
 207 static void blend_setup(struct drm_crtc *crtc)
 208 {
 209         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 210         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 211         struct drm_plane *plane;
 212         const struct mdp5_cfg_hw *hw_cfg;
 213         uint32_t lm = mdp5_crtc->lm, blend_cfg = 0;
 214         unsigned long flags;
 215 #define blender(stage)  ((stage) - STAGE_BASE)
 216
 217         hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
 218
 219         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 220
 221         /* ctl could be released already when we are shutting down: */
 222         if (!mdp5_crtc->ctl)
 223                 goto out;
 224
 225         drm_atomic_crtc_for_each_plane(plane, crtc) {
 226                 enum mdp_mixer_stage_id stage =
 227                         to_mdp5_plane_state(plane->state)->stage;
 228
 229                 /*
 230                  * Note: This cannot happen with current implementation but
 231                  * we need to check this condition once z property is added
 232                  */
 233                 BUG_ON(stage > hw_cfg->lm.nb_stages);
 234
 235                 /* LM */
 236                 mdp5_write(mdp5_kms,
 237                                 REG_MDP5_LM_BLEND_OP_MODE(lm, blender(stage)),
 238                                 MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) |
 239                                 MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST));
 240                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm,
 241                                 blender(stage)), 0xff);
 242                 mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm,
 243                                 blender(stage)), 0x00);
 244                 /* CTL */
 245                 blend_cfg |= mdp_ctl_blend_mask(mdp5_plane_pipe(plane), stage);
 246                 DBG("%s: blending pipe %s on stage=%d", mdp5_crtc->name,
 247                                 pipe2name(mdp5_plane_pipe(plane)), stage);
 248         }
 249
 250         DBG("%s: lm%d: blend config = 0x%08x", mdp5_crtc->name, lm, blend_cfg);
 251         mdp5_ctl_blend(mdp5_crtc->ctl, lm, blend_cfg);
 252
 253 out:
 254         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 255 }
 256
 257 static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc)
 258 {
 259         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 260         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 261         unsigned long flags;
 262         struct drm_display_mode *mode;
 263
 264         if (WARN_ON(!crtc->state))
 265                 return;
 266
 267         mode = &crtc->state->adjusted_mode;
 268
 269         DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
 270                         mdp5_crtc->name, mode->base.id, mode->name,
 271                         mode->vrefresh, mode->clock,
 272                         mode->hdisplay, mode->hsync_start,
 273                         mode->hsync_end, mode->htotal,
 274                         mode->vdisplay, mode->vsync_start,
 275                         mode->vsync_end, mode->vtotal,
 276                         mode->type, mode->flags);
 277
 278         spin_lock_irqsave(&mdp5_crtc->lm_lock, flags);
 279         mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(mdp5_crtc->lm),
 280                         MDP5_LM_OUT_SIZE_WIDTH(mode->hdisplay) |
 281                         MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay));
 282         spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags);
 283 }
 284
 285 static void mdp5_crtc_disable(struct drm_crtc *crtc)
 286 {
 287         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 288         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 289
 290         DBG("%s", mdp5_crtc->name);
 291
 292         if (WARN_ON(!mdp5_crtc->enabled))
 293                 return;
 294
 295         if (mdp5_crtc->cmd_mode)
 296                 mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done);
 297
 298         mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err);
 299         mdp5_disable(mdp5_kms);
 300
 301         mdp5_crtc->enabled = false;
 302 }
 303
 304 static void mdp5_crtc_enable(struct drm_crtc *crtc)
 305 {
 306         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 307         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 308
 309         DBG("%s", mdp5_crtc->name);
 310
 311         if (WARN_ON(mdp5_crtc->enabled))
 312                 return;
 313
 314         mdp5_enable(mdp5_kms);
 315         mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err);
 316
 317         if (mdp5_crtc->cmd_mode)
 318                 mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done);
 319
 320         mdp5_crtc->enabled = true;
 321 }
 322
 323 struct plane_state {
 324         struct drm_plane *plane;
 325         struct mdp5_plane_state *state;
 326 };
 327
 328 static int pstate_cmp(const void *a, const void *b)
 329 {
 330         struct plane_state *pa = (struct plane_state *)a;
 331         struct plane_state *pb = (struct plane_state *)b;
 332         return pa->state->zpos - pb->state->zpos;
 333 }
 334
 335 static int mdp5_crtc_atomic_check(struct drm_crtc *crtc,
 336                 struct drm_crtc_state *state)
 337 {
 338         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 339         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 340         struct drm_plane *plane;
 341         struct drm_device *dev = crtc->dev;
 342         struct plane_state pstates[STAGE3 + 1];
 343         int cnt = 0, i;
 344
 345         DBG("%s: check", mdp5_crtc->name);
 346
 347         /* request a free CTL, if none is already allocated for this CRTC */
 348         if (state->enable && !mdp5_crtc->ctl) {
 349                 mdp5_crtc->ctl = mdp5_ctlm_request(mdp5_kms->ctlm, crtc);
 350                 if (WARN_ON(!mdp5_crtc->ctl))
 351                         return -EINVAL;
 352         }
 353
 354         /* verify that there are not too many planes attached to crtc
 355          * and that we don't have conflicting mixer stages:
 356          */
 357         drm_atomic_crtc_state_for_each_plane(plane, state) {
 358                 struct drm_plane_state *pstate;
 359
 360                 if (cnt >= ARRAY_SIZE(pstates)) {
 361                         dev_err(dev->dev, "too many planes!\n");
 362                         return -EINVAL;
 363                 }
 364
 365                 pstate = state->state->plane_states[drm_plane_index(plane)];
 366
 367                 /* plane might not have changed, in which case take
 368                  * current state:
 369                  */
 370                 if (!pstate)
 371                         pstate = plane->state;
 372
 373                 pstates[cnt].plane = plane;
 374                 pstates[cnt].state = to_mdp5_plane_state(pstate);
 375
 376                 cnt++;
 377         }
 378
 379         sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
 380
 381         for (i = 0; i < cnt; i++) {
 382                 pstates[i].state->stage = STAGE_BASE + i;
 383                 DBG("%s: assign pipe %s on stage=%d", mdp5_crtc->name,
 384                                 pipe2name(mdp5_plane_pipe(pstates[i].plane)),
 385                                 pstates[i].state->stage);
 386         }
 387
 388         return 0;
 389 }
 390
 391 static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc)
 392 {
 393         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 394         DBG("%s: begin", mdp5_crtc->name);
 395 }
 396
 397 static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc)
 398 {
 399         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 400         struct drm_device *dev = crtc->dev;
 401         unsigned long flags;
 402
 403         DBG("%s: event: %p", mdp5_crtc->name, crtc->state->event);
 404
 405         WARN_ON(mdp5_crtc->event);
 406
 407         spin_lock_irqsave(&dev->event_lock, flags);
 408         mdp5_crtc->event = crtc->state->event;
 409         spin_unlock_irqrestore(&dev->event_lock, flags);
 410
 411         /*
 412          * If no CTL has been allocated in mdp5_crtc_atomic_check(),
 413          * it means we are trying to flush a CRTC whose state is disabled:
 414          * nothing else needs to be done.
 415          */
 416         if (unlikely(!mdp5_crtc->ctl))
 417                 return;
 418
 419         blend_setup(crtc);
 420
 421         /* PP_DONE irq is only used by command mode for now.
 422          * It is better to request pending before FLUSH and START trigger
 423          * to make sure no pp_done irq missed.
 424          * This is safe because no pp_done will happen before SW trigger
 425          * in command mode.
 426          */
 427         if (mdp5_crtc->cmd_mode)
 428                 request_pp_done_pending(crtc);
 429
 430         mdp5_crtc->flushed_mask = crtc_flush_all(crtc);
 431
 432         request_pending(crtc, PENDING_FLIP);
 433 }
 434
 435 static int mdp5_crtc_set_property(struct drm_crtc *crtc,
 436                 struct drm_property *property, uint64_t val)
 437 {
 438         // XXX
 439         return -EINVAL;
 440 }
 441
 442 static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h)
 443 {
 444         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 445         uint32_t xres = crtc->mode.hdisplay;
 446         uint32_t yres = crtc->mode.vdisplay;
 447
 448         /*
 449          * Cursor Region Of Interest (ROI) is a plane read from cursor
 450          * buffer to render. The ROI region is determined by the visibility of
 451          * the cursor point. In the default Cursor image the cursor point will
 452          * be at the top left of the cursor image, unless it is specified
 453          * otherwise using hotspot feature.
 454          *
 455          * If the cursor point reaches the right (xres - x < cursor.width) or
 456          * bottom (yres - y < cursor.height) boundary of the screen, then ROI
 457          * width and ROI height need to be evaluated to crop the cursor image
 458          * accordingly.
 459          * (xres-x) will be new cursor width when x > (xres - cursor.width)
 460          * (yres-y) will be new cursor height when y > (yres - cursor.height)
 461          */
 462         *roi_w = min(mdp5_crtc->cursor.width, xres -
 463                         mdp5_crtc->cursor.x);
 464         *roi_h = min(mdp5_crtc->cursor.height, yres -
 465                         mdp5_crtc->cursor.y);
 466 }
 467
 468 static int mdp5_crtc_cursor_set(struct drm_crtc *crtc,
 469                 struct drm_file *file, uint32_t handle,
 470                 uint32_t width, uint32_t height)
 471 {
 472         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 473         struct drm_device *dev = crtc->dev;
 474         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 475         struct drm_gem_object *cursor_bo, *old_bo = NULL;
 476         uint32_t blendcfg, cursor_addr, stride;
 477         int ret, bpp, lm;
 478         unsigned int depth;
 479         enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;
 480         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 481         uint32_t roi_w, roi_h;
 482         bool cursor_enable = true;
 483         unsigned long flags;
 484
 485         if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {
 486                 dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height);
 487                 return -EINVAL;
 488         }
 489
 490         if (NULL == mdp5_crtc->ctl)
 491                 return -EINVAL;
 492
 493         if (!handle) {
 494                 DBG("Cursor off");
 495                 cursor_enable = false;
 496                 goto set_cursor;
 497         }
 498
 499         cursor_bo = drm_gem_object_lookup(dev, file, handle);
 500         if (!cursor_bo)
 501                 return -ENOENT;
 502
 503         ret = msm_gem_get_iova(cursor_bo, mdp5_kms->id, &cursor_addr);
 504         if (ret)
 505                 return -EINVAL;
 506
 507         lm = mdp5_crtc->lm;
 508         drm_fb_get_bpp_depth(DRM_FORMAT_ARGB8888, &depth, &bpp);
 509         stride = width * (bpp >> 3);
 510
 511         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 512         old_bo = mdp5_crtc->cursor.scanout_bo;
 513
 514         mdp5_crtc->cursor.scanout_bo = cursor_bo;
 515         mdp5_crtc->cursor.width = width;
 516         mdp5_crtc->cursor.height = height;
 517
 518         get_roi(crtc, &roi_w, &roi_h);
 519
 520         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride);
 521         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm),
 522                         MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888));
 523         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm),
 524                         MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) |
 525                         MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width));
 526         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm),
 527                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 528                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 529         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr);
 530
 531         blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN;
 532         blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha);
 533         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg);
 534
 535         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 536
 537 set_cursor:
 538         ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable);
 539         if (ret) {
 540                 dev_err(dev->dev, "failed to %sable cursor: %d\n",
 541                                 cursor_enable ? "en" : "dis", ret);
 542                 goto end;
 543         }
 544
 545         crtc_flush(crtc, flush_mask);
 546
 547 end:
 548         if (old_bo) {
 549                 drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo);
 550                 /* enable vblank to complete cursor work: */
 551                 request_pending(crtc, PENDING_CURSOR);
 552         }
 553         return ret;
 554 }
 555
 556 static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 557 {
 558         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 559         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 560         uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);
 561         uint32_t roi_w;
 562         uint32_t roi_h;
 563         unsigned long flags;
 564
 565         /* In case the CRTC is disabled, just drop the cursor update */
 566         if (unlikely(!crtc->state->enable))
 567                 return 0;
 568
 569         mdp5_crtc->cursor.x = x = max(x, 0);
 570         mdp5_crtc->cursor.y = y = max(y, 0);
 571
 572         get_roi(crtc, &roi_w, &roi_h);
 573
 574         spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags);
 575         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(mdp5_crtc->lm),
 576                         MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) |
 577                         MDP5_LM_CURSOR_SIZE_ROI_W(roi_w));
 578         mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(mdp5_crtc->lm),
 579                         MDP5_LM_CURSOR_START_XY_Y_START(y) |
 580                         MDP5_LM_CURSOR_START_XY_X_START(x));
 581         spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags);
 582
 583         crtc_flush(crtc, flush_mask);
 584
 585         return 0;
 586 }
 587
 588 static const struct drm_crtc_funcs mdp5_crtc_funcs = {
 589         .set_config = drm_atomic_helper_set_config,
 590         .destroy = mdp5_crtc_destroy,
 591         .page_flip = drm_atomic_helper_page_flip,
 592         .set_property = mdp5_crtc_set_property,
 593         .reset = drm_atomic_helper_crtc_reset,
 594         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 595         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 596         .cursor_set = mdp5_crtc_cursor_set,
 597         .cursor_move = mdp5_crtc_cursor_move,
 598 };
 599
 600 static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = {
 601         .mode_fixup = mdp5_crtc_mode_fixup,
 602         .mode_set_nofb = mdp5_crtc_mode_set_nofb,
 603         .disable = mdp5_crtc_disable,
 604         .enable = mdp5_crtc_enable,
 605         .atomic_check = mdp5_crtc_atomic_check,
 606         .atomic_begin = mdp5_crtc_atomic_begin,
 607         .atomic_flush = mdp5_crtc_atomic_flush,
 608 };
 609
 610 static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus)
 611 {
 612         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank);
 613         struct drm_crtc *crtc = &mdp5_crtc->base;
 614         struct msm_drm_private *priv = crtc->dev->dev_private;
 615         unsigned pending;
 616
 617         mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank);
 618
 619         pending = atomic_xchg(&mdp5_crtc->pending, 0);
 620
 621         if (pending & PENDING_FLIP) {
 622                 complete_flip(crtc, NULL);
 623         }
 624
 625         if (pending & PENDING_CURSOR)
 626                 drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq);
 627 }
 628
 629 static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus)
 630 {
 631         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err);
 632
 633         DBG("%s: error: %08x", mdp5_crtc->name, irqstatus);
 634 }
 635
 636 static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus)
 637 {
 638         struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc,
 639                                                                 pp_done);
 640
 641         complete(&mdp5_crtc->pp_completion);
 642 }
 643
 644 static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 648         int ret;
 649
 650         ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion,
 651                                                 msecs_to_jiffies(50));
 652         if (ret == 0)
 653                 dev_warn(dev->dev, "pp done time out, lm=%d\n", mdp5_crtc->lm);
 654 }
 655
 656 static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc)
 657 {
 658         struct drm_device *dev = crtc->dev;
 659         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 660         int ret;
 661
 662         /* Should not call this function if crtc is disabled. */
 663         if (!mdp5_crtc->ctl)
 664                 return;
 665
 666         ret = drm_crtc_vblank_get(crtc);
 667         if (ret)
 668                 return;
 669
 670         ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue,
 671                 ((mdp5_ctl_get_commit_status(mdp5_crtc->ctl) &
 672                 mdp5_crtc->flushed_mask) == 0),
 673                 msecs_to_jiffies(50));
 674         if (ret <= 0)
 675                 dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id);
 676
 677         mdp5_crtc->flushed_mask = 0;
 678
 679         drm_crtc_vblank_put(crtc);
 680 }
 681
 682 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc)
 683 {
 684         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 685         return mdp5_crtc->vblank.irqmask;
 686 }
 687
 688 void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
 689 {
 690         DBG("cancel: %p", file);
 691         complete_flip(crtc, file);
 692 }
 693
 694 /* set interface for routing crtc->encoder: */
 695 void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf)
 696 {
 697         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 698         struct mdp5_kms *mdp5_kms = get_kms(crtc);
 699         int lm = mdp5_crtc_get_lm(crtc);
 700
 701         /* now that we know what irq's we want: */
 702         mdp5_crtc->err.irqmask = intf2err(intf->num);
 703         mdp5_crtc->vblank.irqmask = intf2vblank(lm, intf);
 704
 705         if ((intf->type == INTF_DSI) &&
 706                 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) {
 707                 mdp5_crtc->pp_done.irqmask = lm2ppdone(lm);
 708                 mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq;
 709                 mdp5_crtc->cmd_mode = true;
 710         } else {
 711                 mdp5_crtc->pp_done.irqmask = 0;
 712                 mdp5_crtc->pp_done.irq = NULL;
 713                 mdp5_crtc->cmd_mode = false;
 714         }
 715
 716         mdp_irq_update(&mdp5_kms->base);
 717
 718         mdp5_ctl_set_intf(mdp5_crtc->ctl, intf);
 719 }
 720
 721 int mdp5_crtc_get_lm(struct drm_crtc *crtc)
 722 {
 723         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 724         return WARN_ON(!crtc) ? -EINVAL : mdp5_crtc->lm;
 725 }
 726
 727 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc)
 728 {
 729         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 730         return WARN_ON(!crtc) ? NULL : mdp5_crtc->ctl;
 731 }
 732
 733 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc)
 734 {
 735         struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc);
 736
 737         if (mdp5_crtc->cmd_mode)
 738                 mdp5_crtc_wait_for_pp_done(crtc);
 739         else
 740                 mdp5_crtc_wait_for_flush_done(crtc);
 741 }
 742
 743 /* initialize crtc */
 744 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
 745                 struct drm_plane *plane, int id)
 746 {
 747         struct drm_crtc *crtc = NULL;
 748         struct mdp5_crtc *mdp5_crtc;
 749
 750         mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL);
 751         if (!mdp5_crtc)
 752                 return ERR_PTR(-ENOMEM);
 753
 754         crtc = &mdp5_crtc->base;
 755
 756         mdp5_crtc->id = id;
 757         mdp5_crtc->lm = GET_LM_ID(id);
 758
 759         spin_lock_init(&mdp5_crtc->lm_lock);
 760         spin_lock_init(&mdp5_crtc->cursor.lock);
 761         init_completion(&mdp5_crtc->pp_completion);
 762
 763         mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq;
 764         mdp5_crtc->err.irq = mdp5_crtc_err_irq;
 765
 766         snprintf(mdp5_crtc->name, sizeof(mdp5_crtc->name), "%s:%d",
 767                         pipe2name(mdp5_plane_pipe(plane)), id);
 768
 769         drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp5_crtc_funcs);
 770
 771         drm_flip_work_init(&mdp5_crtc->unref_cursor_work,
 772                         "unref cursor", unref_cursor_worker);
 773
 774         drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs);
 775         plane->crtc = crtc;
 776
 777         mdp5_plane_install_properties(plane, &crtc->base);
 778
 779         return crtc;
 780 }