2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #ifndef __MDP5_KMS_H__
19 #define __MDP5_KMS_H__
23 #include "mdp/mdp_kms.h"
24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
32 struct drm_device *dev;
34 struct mdp5_cfg_handler *cfg;
36 /* mapper-id used to request GEM buffer mapped for scanout: */
41 struct mdp5_ctl_manager *ctlm;
43 /* io/register spaces: */
44 void __iomem *mmio, *vbif;
46 struct regulator *vdd;
53 struct clk *vsync_clk;
56 * lock to protect access to global resources: ie., following register:
57 * - REG_MDP5_MDP_DISP_INTF_SEL
59 spinlock_t resource_lock;
61 struct mdp_irq error_handler;
64 volatile unsigned long enabled_mask;
65 struct irq_domain *domain;
68 #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base)
70 struct mdp5_plane_state {
71 struct drm_plane_state base;
73 /* "virtual" zpos.. we calculate actual mixer-stage at runtime
74 * by sorting the attached planes by zpos and then assigning
75 * mixer stage lowest to highest. Private planes get default
76 * zpos of zero, and public planes a unique value that is
77 * greater than zero. This way, things work out if a naive
78 * userspace assigns planes to a crtc without setting zpos.
82 /* the actual mixer stage, calculated in crtc->atomic_check()
83 * NOTE: this should move to mdp5_crtc_state, when that exists
85 enum mdp_mixer_stage_id stage;
87 /* some additional transactional status to help us know in the
88 * apply path whether we need to update SMP allocation, and
89 * whether current update is still pending:
91 bool mode_changed : 1;
94 #define to_mdp5_plane_state(x) \
95 container_of(x, struct mdp5_plane_state, base)
98 MDP5_INTF_MODE_NONE = 0,
100 /* Modes used for DSI interface (INTF_DSI type): */
101 MDP5_INTF_DSI_MODE_VIDEO,
102 MDP5_INTF_DSI_MODE_COMMAND,
104 /* Modes used for WB interface (INTF_WB type): */
105 MDP5_INTF_WB_MODE_BLOCK,
106 MDP5_INTF_WB_MODE_LINE,
109 struct mdp5_interface {
110 int num; /* display interface number */
111 enum mdp5_intf_type type;
112 enum mdp5_intf_mode mode;
115 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
117 msm_writel(data, mdp5_kms->mmio + reg);
120 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
122 return msm_readl(mdp5_kms->mmio + reg);
125 static inline const char *pipe2name(enum mdp5_pipe pipe)
127 static const char *names[] = {
128 #define NAME(n) [SSPP_ ## n] = #n
129 NAME(VIG0), NAME(VIG1), NAME(VIG2),
130 NAME(RGB0), NAME(RGB1), NAME(RGB2),
131 NAME(DMA0), NAME(DMA1),
132 NAME(VIG3), NAME(RGB3),
138 static inline int pipe2nclients(enum mdp5_pipe pipe)
151 static inline uint32_t intf2err(int intf_num)
154 case 0: return MDP5_IRQ_INTF0_UNDER_RUN;
155 case 1: return MDP5_IRQ_INTF1_UNDER_RUN;
156 case 2: return MDP5_IRQ_INTF2_UNDER_RUN;
157 case 3: return MDP5_IRQ_INTF3_UNDER_RUN;
162 #define GET_PING_PONG_ID(layer_mixer) ((layer_mixer == 5) ? 3 : layer_mixer)
163 static inline uint32_t intf2vblank(int lm, struct mdp5_interface *intf)
166 * In case of DSI Command Mode, the Ping Pong's read pointer IRQ
167 * acts as a Vblank signal. The Ping Pong buffer used is bound to
171 if ((intf->type == INTF_DSI) &&
172 (intf->mode == MDP5_INTF_DSI_MODE_COMMAND))
173 return MDP5_IRQ_PING_PONG_0_RD_PTR << GET_PING_PONG_ID(lm);
175 if (intf->type == INTF_WB)
176 return MDP5_IRQ_WB_2_DONE;
179 case 0: return MDP5_IRQ_INTF0_VSYNC;
180 case 1: return MDP5_IRQ_INTF1_VSYNC;
181 case 2: return MDP5_IRQ_INTF2_VSYNC;
182 case 3: return MDP5_IRQ_INTF3_VSYNC;
187 static inline uint32_t lm2ppdone(int lm)
189 return MDP5_IRQ_PING_PONG_0_DONE << GET_PING_PONG_ID(lm);
192 int mdp5_disable(struct mdp5_kms *mdp5_kms);
193 int mdp5_enable(struct mdp5_kms *mdp5_kms);
195 void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask);
196 void mdp5_irq_preinstall(struct msm_kms *kms);
197 int mdp5_irq_postinstall(struct msm_kms *kms);
198 void mdp5_irq_uninstall(struct msm_kms *kms);
199 irqreturn_t mdp5_irq(struct msm_kms *kms);
200 int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
201 void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
202 int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms);
203 void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms);
205 static inline bool pipe_supports_yuv(enum mdp5_pipe pipe)
219 uint32_t mdp5_get_formats(enum mdp5_pipe pipe, uint32_t *pixel_formats,
220 uint32_t max_formats)
222 return mdp_get_formats(pixel_formats, max_formats,
223 !pipe_supports_yuv(pipe));
226 void mdp5_plane_install_properties(struct drm_plane *plane,
227 struct drm_mode_object *obj);
228 uint32_t mdp5_plane_get_flush(struct drm_plane *plane);
229 void mdp5_plane_complete_flip(struct drm_plane *plane);
230 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane);
231 struct drm_plane *mdp5_plane_init(struct drm_device *dev,
232 enum mdp5_pipe pipe, bool private_plane, uint32_t reg_offset);
234 uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc);
236 int mdp5_crtc_get_lm(struct drm_crtc *crtc);
237 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
238 void mdp5_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
239 void mdp5_crtc_set_intf(struct drm_crtc *crtc, struct mdp5_interface *intf);
240 void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc);
241 struct drm_crtc *mdp5_crtc_init(struct drm_device *dev,
242 struct drm_plane *plane, int id);
244 struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
245 struct mdp5_interface *intf);
246 int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
247 struct drm_encoder *slave_encoder);
249 #ifdef CONFIG_DRM_MSM_DSI
250 struct drm_encoder *mdp5_cmd_encoder_init(struct drm_device *dev,
251 struct mdp5_interface *intf);
252 int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
253 struct drm_encoder *slave_encoder);
255 static inline struct drm_encoder *mdp5_cmd_encoder_init(
256 struct drm_device *dev, struct mdp5_interface *intf)
258 return ERR_PTR(-EINVAL);
260 static inline int mdp5_cmd_encoder_set_split_display(
261 struct drm_encoder *encoder, struct drm_encoder *slave_encoder)
267 #endif /* __MDP5_KMS_H__ */