drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/object.h>
  26 #include <core/parent.h>
  27 #include <core/handle.h>
  28 #include <core/class.h>
  29
  30 #include <engine/disp.h>
  31
  32 #include <subdev/bios.h>
  33 #include <subdev/bios/dcb.h>
  34 #include <subdev/bios/disp.h>
  35 #include <subdev/bios/init.h>
  36 #include <subdev/bios/pll.h>
  37 #include <subdev/devinit.h>
  38 #include <subdev/fb.h>
  39 #include <subdev/timer.h>
  40
  41 #include "nv50.h"
  42
  43 /*******************************************************************************
  44  * EVO DMA channel base class
  45  ******************************************************************************/
  46
  47 static int
  48 nvd0_disp_dmac_object_attach(struct nouveau_object *parent,
  49                              struct nouveau_object *object, u32 name)
  50 {
  51         struct nv50_disp_base *base = (void *)parent->parent;
  52         struct nv50_disp_chan *chan = (void *)parent;
  53         u32 addr = nv_gpuobj(object)->node->offset;
  54         u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
  55         return nouveau_ramht_insert(base->ramht, chan->chid, name, data);
  56 }
  57
  58 static void
  59 nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
  60 {
  61         struct nv50_disp_base *base = (void *)parent->parent;
  62         nouveau_ramht_remove(base->ramht, cookie);
  63 }
  64
  65 static int
  66 nvd0_disp_dmac_init(struct nouveau_object *object)
  67 {
  68         struct nv50_disp_priv *priv = (void *)object->engine;
  69         struct nv50_disp_dmac *dmac = (void *)object;
  70         int chid = dmac->base.chid;
  71         int ret;
  72
  73         ret = nv50_disp_chan_init(&dmac->base);
  74         if (ret)
  75                 return ret;
  76
  77         /* enable error reporting */
  78         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
  79         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
  80
  81         /* initialise channel for dma command submission */
  82         nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push);
  83         nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000);
  84         nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001);
  85         nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010);
  86         nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);
  87         nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013);
  88
  89         /* wait for it to go inactive */
  90         if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) {
  91                 nv_error(dmac, "init: 0x%08x\n",
  92                          nv_rd32(priv, 0x610490 + (chid * 0x10)));
  93                 return -EBUSY;
  94         }
  95
  96         return 0;
  97 }
  98
  99 static int
 100 nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
 101 {
 102         struct nv50_disp_priv *priv = (void *)object->engine;
 103         struct nv50_disp_dmac *dmac = (void *)object;
 104         int chid = dmac->base.chid;
 105
 106         /* deactivate channel */
 107         nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000);
 108         nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000);
 109         if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) {
 110                 nv_error(dmac, "fini: 0x%08x\n",
 111                          nv_rd32(priv, 0x610490 + (chid * 0x10)));
 112                 if (suspend)
 113                         return -EBUSY;
 114         }
 115
 116         /* disable error reporting */
 117         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
 118         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
 119
 120         return nv50_disp_chan_fini(&dmac->base, suspend);
 121 }
 122
 123 /*******************************************************************************
 124  * EVO master channel object
 125  ******************************************************************************/
 126
 127 static int
 128 nvd0_disp_mast_ctor(struct nouveau_object *parent,
 129                     struct nouveau_object *engine,
 130                     struct nouveau_oclass *oclass, void *data, u32 size,
 131                     struct nouveau_object **pobject)
 132 {
 133         struct nv50_display_mast_class *args = data;
 134         struct nv50_disp_dmac *mast;
 135         int ret;
 136
 137         if (size < sizeof(*args))
 138                 return -EINVAL;
 139
 140         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 141                                      0, sizeof(*mast), (void **)&mast);
 142         *pobject = nv_object(mast);
 143         if (ret)
 144                 return ret;
 145
 146         nv_parent(mast)->object_attach = nvd0_disp_dmac_object_attach;
 147         nv_parent(mast)->object_detach = nvd0_disp_dmac_object_detach;
 148         return 0;
 149 }
 150
 151 static int
 152 nvd0_disp_mast_init(struct nouveau_object *object)
 153 {
 154         struct nv50_disp_priv *priv = (void *)object->engine;
 155         struct nv50_disp_dmac *mast = (void *)object;
 156         int ret;
 157
 158         ret = nv50_disp_chan_init(&mast->base);
 159         if (ret)
 160                 return ret;
 161
 162         /* enable error reporting */
 163         nv_mask(priv, 0x610090, 0x00000001, 0x00000001);
 164         nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001);
 165
 166         /* initialise channel for dma command submission */
 167         nv_wr32(priv, 0x610494, mast->push);
 168         nv_wr32(priv, 0x610498, 0x00010000);
 169         nv_wr32(priv, 0x61049c, 0x00000001);
 170         nv_mask(priv, 0x610490, 0x00000010, 0x00000010);
 171         nv_wr32(priv, 0x640000, 0x00000000);
 172         nv_wr32(priv, 0x610490, 0x01000013);
 173
 174         /* wait for it to go inactive */
 175         if (!nv_wait(priv, 0x610490, 0x80000000, 0x00000000)) {
 176                 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490));
 177                 return -EBUSY;
 178         }
 179
 180         return 0;
 181 }
 182
 183 static int
 184 nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
 185 {
 186         struct nv50_disp_priv *priv = (void *)object->engine;
 187         struct nv50_disp_dmac *mast = (void *)object;
 188
 189         /* deactivate channel */
 190         nv_mask(priv, 0x610490, 0x00000010, 0x00000000);
 191         nv_mask(priv, 0x610490, 0x00000003, 0x00000000);
 192         if (!nv_wait(priv, 0x610490, 0x001e0000, 0x00000000)) {
 193                 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490));
 194                 if (suspend)
 195                         return -EBUSY;
 196         }
 197
 198         /* disable error reporting */
 199         nv_mask(priv, 0x610090, 0x00000001, 0x00000000);
 200         nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000);
 201
 202         return nv50_disp_chan_fini(&mast->base, suspend);
 203 }
 204
 205 struct nouveau_ofuncs
 206 nvd0_disp_mast_ofuncs = {
 207         .ctor = nvd0_disp_mast_ctor,
 208         .dtor = nv50_disp_dmac_dtor,
 209         .init = nvd0_disp_mast_init,
 210         .fini = nvd0_disp_mast_fini,
 211         .rd32 = nv50_disp_chan_rd32,
 212         .wr32 = nv50_disp_chan_wr32,
 213 };
 214
 215 /*******************************************************************************
 216  * EVO sync channel objects
 217  ******************************************************************************/
 218
 219 static int
 220 nvd0_disp_sync_ctor(struct nouveau_object *parent,
 221                     struct nouveau_object *engine,
 222                     struct nouveau_oclass *oclass, void *data, u32 size,
 223                     struct nouveau_object **pobject)
 224 {
 225         struct nv50_display_sync_class *args = data;
 226         struct nv50_disp_priv *priv = (void *)engine;
 227         struct nv50_disp_dmac *dmac;
 228         int ret;
 229
 230         if (size < sizeof(*args) || args->head >= priv->head.nr)
 231                 return -EINVAL;
 232
 233         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 234                                      1 + args->head, sizeof(*dmac),
 235                                      (void **)&dmac);
 236         *pobject = nv_object(dmac);
 237         if (ret)
 238                 return ret;
 239
 240         nv_parent(dmac)->object_attach = nvd0_disp_dmac_object_attach;
 241         nv_parent(dmac)->object_detach = nvd0_disp_dmac_object_detach;
 242         return 0;
 243 }
 244
 245 struct nouveau_ofuncs
 246 nvd0_disp_sync_ofuncs = {
 247         .ctor = nvd0_disp_sync_ctor,
 248         .dtor = nv50_disp_dmac_dtor,
 249         .init = nvd0_disp_dmac_init,
 250         .fini = nvd0_disp_dmac_fini,
 251         .rd32 = nv50_disp_chan_rd32,
 252         .wr32 = nv50_disp_chan_wr32,
 253 };
 254
 255 /*******************************************************************************
 256  * EVO overlay channel objects
 257  ******************************************************************************/
 258
 259 static int
 260 nvd0_disp_ovly_ctor(struct nouveau_object *parent,
 261                     struct nouveau_object *engine,
 262                     struct nouveau_oclass *oclass, void *data, u32 size,
 263                     struct nouveau_object **pobject)
 264 {
 265         struct nv50_display_ovly_class *args = data;
 266         struct nv50_disp_priv *priv = (void *)engine;
 267         struct nv50_disp_dmac *dmac;
 268         int ret;
 269
 270         if (size < sizeof(*args) || args->head >= priv->head.nr)
 271                 return -EINVAL;
 272
 273         ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf,
 274                                      5 + args->head, sizeof(*dmac),
 275                                      (void **)&dmac);
 276         *pobject = nv_object(dmac);
 277         if (ret)
 278                 return ret;
 279
 280         nv_parent(dmac)->object_attach = nvd0_disp_dmac_object_attach;
 281         nv_parent(dmac)->object_detach = nvd0_disp_dmac_object_detach;
 282         return 0;
 283 }
 284
 285 struct nouveau_ofuncs
 286 nvd0_disp_ovly_ofuncs = {
 287         .ctor = nvd0_disp_ovly_ctor,
 288         .dtor = nv50_disp_dmac_dtor,
 289         .init = nvd0_disp_dmac_init,
 290         .fini = nvd0_disp_dmac_fini,
 291         .rd32 = nv50_disp_chan_rd32,
 292         .wr32 = nv50_disp_chan_wr32,
 293 };
 294
 295 /*******************************************************************************
 296  * EVO PIO channel base class
 297  ******************************************************************************/
 298
 299 static int
 300 nvd0_disp_pioc_create_(struct nouveau_object *parent,
 301                        struct nouveau_object *engine,
 302                        struct nouveau_oclass *oclass, int chid,
 303                        int length, void **pobject)
 304 {
 305         return nv50_disp_chan_create_(parent, engine, oclass, chid,
 306                                       length, pobject);
 307 }
 308
 309 static void
 310 nvd0_disp_pioc_dtor(struct nouveau_object *object)
 311 {
 312         struct nv50_disp_pioc *pioc = (void *)object;
 313         nv50_disp_chan_destroy(&pioc->base);
 314 }
 315
 316 static int
 317 nvd0_disp_pioc_init(struct nouveau_object *object)
 318 {
 319         struct nv50_disp_priv *priv = (void *)object->engine;
 320         struct nv50_disp_pioc *pioc = (void *)object;
 321         int chid = pioc->base.chid;
 322         int ret;
 323
 324         ret = nv50_disp_chan_init(&pioc->base);
 325         if (ret)
 326                 return ret;
 327
 328         /* enable error reporting */
 329         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000001 << chid);
 330         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid);
 331
 332         /* activate channel */
 333         nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001);
 334         if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) {
 335                 nv_error(pioc, "init: 0x%08x\n",
 336                          nv_rd32(priv, 0x610490 + (chid * 0x10)));
 337                 return -EBUSY;
 338         }
 339
 340         return 0;
 341 }
 342
 343 static int
 344 nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
 345 {
 346         struct nv50_disp_priv *priv = (void *)object->engine;
 347         struct nv50_disp_pioc *pioc = (void *)object;
 348         int chid = pioc->base.chid;
 349
 350         nv_mask(priv, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000);
 351         if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) {
 352                 nv_error(pioc, "timeout: 0x%08x\n",
 353                          nv_rd32(priv, 0x610490 + (chid * 0x10)));
 354                 if (suspend)
 355                         return -EBUSY;
 356         }
 357
 358         /* disable error reporting */
 359         nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000);
 360         nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000);
 361
 362         return nv50_disp_chan_fini(&pioc->base, suspend);
 363 }
 364
 365 /*******************************************************************************
 366  * EVO immediate overlay channel objects
 367  ******************************************************************************/
 368
 369 static int
 370 nvd0_disp_oimm_ctor(struct nouveau_object *parent,
 371                     struct nouveau_object *engine,
 372                     struct nouveau_oclass *oclass, void *data, u32 size,
 373                     struct nouveau_object **pobject)
 374 {
 375         struct nv50_display_oimm_class *args = data;
 376         struct nv50_disp_priv *priv = (void *)engine;
 377         struct nv50_disp_pioc *pioc;
 378         int ret;
 379
 380         if (size < sizeof(*args) || args->head >= priv->head.nr)
 381                 return -EINVAL;
 382
 383         ret = nvd0_disp_pioc_create_(parent, engine, oclass, 9 + args->head,
 384                                      sizeof(*pioc), (void **)&pioc);
 385         *pobject = nv_object(pioc);
 386         if (ret)
 387                 return ret;
 388
 389         return 0;
 390 }
 391
 392 struct nouveau_ofuncs
 393 nvd0_disp_oimm_ofuncs = {
 394         .ctor = nvd0_disp_oimm_ctor,
 395         .dtor = nvd0_disp_pioc_dtor,
 396         .init = nvd0_disp_pioc_init,
 397         .fini = nvd0_disp_pioc_fini,
 398         .rd32 = nv50_disp_chan_rd32,
 399         .wr32 = nv50_disp_chan_wr32,
 400 };
 401
 402 /*******************************************************************************
 403  * EVO cursor channel objects
 404  ******************************************************************************/
 405
 406 static int
 407 nvd0_disp_curs_ctor(struct nouveau_object *parent,
 408                     struct nouveau_object *engine,
 409                     struct nouveau_oclass *oclass, void *data, u32 size,
 410                     struct nouveau_object **pobject)
 411 {
 412         struct nv50_display_curs_class *args = data;
 413         struct nv50_disp_priv *priv = (void *)engine;
 414         struct nv50_disp_pioc *pioc;
 415         int ret;
 416
 417         if (size < sizeof(*args) || args->head >= priv->head.nr)
 418                 return -EINVAL;
 419
 420         ret = nvd0_disp_pioc_create_(parent, engine, oclass, 13 + args->head,
 421                                      sizeof(*pioc), (void **)&pioc);
 422         *pobject = nv_object(pioc);
 423         if (ret)
 424                 return ret;
 425
 426         return 0;
 427 }
 428
 429 struct nouveau_ofuncs
 430 nvd0_disp_curs_ofuncs = {
 431         .ctor = nvd0_disp_curs_ctor,
 432         .dtor = nvd0_disp_pioc_dtor,
 433         .init = nvd0_disp_pioc_init,
 434         .fini = nvd0_disp_pioc_fini,
 435         .rd32 = nv50_disp_chan_rd32,
 436         .wr32 = nv50_disp_chan_wr32,
 437 };
 438
 439 /*******************************************************************************
 440  * Base display object
 441  ******************************************************************************/
 442
 443 static void
 444 nvd0_disp_base_vblank_enable(struct nouveau_event *event, int head)
 445 {
 446         nv_mask(event->priv, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
 447 }
 448
 449 static void
 450 nvd0_disp_base_vblank_disable(struct nouveau_event *event, int head)
 451 {
 452         nv_mask(event->priv, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
 453 }
 454
 455 static int
 456 nvd0_disp_base_ctor(struct nouveau_object *parent,
 457                     struct nouveau_object *engine,
 458                     struct nouveau_oclass *oclass, void *data, u32 size,
 459                     struct nouveau_object **pobject)
 460 {
 461         struct nv50_disp_priv *priv = (void *)engine;
 462         struct nv50_disp_base *base;
 463         int ret;
 464
 465         ret = nouveau_parent_create(parent, engine, oclass, 0,
 466                                     priv->sclass, 0, &base);
 467         *pobject = nv_object(base);
 468         if (ret)
 469                 return ret;
 470
 471         priv->base.vblank->priv = priv;
 472         priv->base.vblank->enable = nvd0_disp_base_vblank_enable;
 473         priv->base.vblank->disable = nvd0_disp_base_vblank_disable;
 474
 475         return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
 476                                 &base->ramht);
 477 }
 478
 479 static void
 480 nvd0_disp_base_dtor(struct nouveau_object *object)
 481 {
 482         struct nv50_disp_base *base = (void *)object;
 483         nouveau_ramht_ref(NULL, &base->ramht);
 484         nouveau_parent_destroy(&base->base);
 485 }
 486
 487 static int
 488 nvd0_disp_base_init(struct nouveau_object *object)
 489 {
 490         struct nv50_disp_priv *priv = (void *)object->engine;
 491         struct nv50_disp_base *base = (void *)object;
 492         int ret, i;
 493         u32 tmp;
 494
 495         ret = nouveau_parent_init(&base->base);
 496         if (ret)
 497                 return ret;
 498
 499         /* The below segments of code copying values from one register to
 500          * another appear to inform EVO of the display capabilities or
 501          * something similar.
 502          */
 503
 504         /* ... CRTC caps */
 505         for (i = 0; i < priv->head.nr; i++) {
 506                 tmp = nv_rd32(priv, 0x616104 + (i * 0x800));
 507                 nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp);
 508                 tmp = nv_rd32(priv, 0x616108 + (i * 0x800));
 509                 nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp);
 510                 tmp = nv_rd32(priv, 0x61610c + (i * 0x800));
 511                 nv_wr32(priv, 0x6101bc + (i * 0x800), tmp);
 512         }
 513
 514         /* ... DAC caps */
 515         for (i = 0; i < priv->dac.nr; i++) {
 516                 tmp = nv_rd32(priv, 0x61a000 + (i * 0x800));
 517                 nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp);
 518         }
 519
 520         /* ... SOR caps */
 521         for (i = 0; i < priv->sor.nr; i++) {
 522                 tmp = nv_rd32(priv, 0x61c000 + (i * 0x800));
 523                 nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp);
 524         }
 525
 526         /* steal display away from vbios, or something like that */
 527         if (nv_rd32(priv, 0x6100ac) & 0x00000100) {
 528                 nv_wr32(priv, 0x6100ac, 0x00000100);
 529                 nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000);
 530                 if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) {
 531                         nv_error(priv, "timeout acquiring display\n");
 532                         return -EBUSY;
 533                 }
 534         }
 535
 536         /* point at display engine memory area (hash table, objects) */
 537         nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9);
 538
 539         /* enable supervisor interrupts, disable everything else */
 540         nv_wr32(priv, 0x610090, 0x00000000);
 541         nv_wr32(priv, 0x6100a0, 0x00000000);
 542         nv_wr32(priv, 0x6100b0, 0x00000307);
 543
 544         /* disable underflow reporting, preventing an intermittent issue
 545          * on some nve4 boards where the production vbios left this
 546          * setting enabled by default.
 547          *
 548          * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
 549          */
 550         for (i = 0; i < priv->head.nr; i++)
 551                 nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
 552
 553         return 0;
 554 }
 555
 556 static int
 557 nvd0_disp_base_fini(struct nouveau_object *object, bool suspend)
 558 {
 559         struct nv50_disp_priv *priv = (void *)object->engine;
 560         struct nv50_disp_base *base = (void *)object;
 561
 562         /* disable all interrupts */
 563         nv_wr32(priv, 0x6100b0, 0x00000000);
 564
 565         return nouveau_parent_fini(&base->base, suspend);
 566 }
 567
 568 struct nouveau_ofuncs
 569 nvd0_disp_base_ofuncs = {
 570         .ctor = nvd0_disp_base_ctor,
 571         .dtor = nvd0_disp_base_dtor,
 572         .init = nvd0_disp_base_init,
 573         .fini = nvd0_disp_base_fini,
 574 };
 575
 576 static struct nouveau_oclass
 577 nvd0_disp_base_oclass[] = {
 578         { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
 579         {}
 580 };
 581
 582 static struct nouveau_oclass
 583 nvd0_disp_sclass[] = {
 584         { NVD0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
 585         { NVD0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
 586         { NVD0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
 587         { NVD0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
 588         { NVD0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
 589         {}
 590 };
 591
 592 /*******************************************************************************
 593  * Display engine implementation
 594  ******************************************************************************/
 595
 596 static u16
 597 exec_lookup(struct nv50_disp_priv *priv, int head, int outp, u32 ctrl,
 598             struct dcb_output *dcb, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 599             struct nvbios_outp *info)
 600 {
 601         struct nouveau_bios *bios = nouveau_bios(priv);
 602         u16 mask, type, data;
 603
 604         if (outp < 4) {
 605                 type = DCB_OUTPUT_ANALOG;
 606                 mask = 0;
 607         } else {
 608                 outp -= 4;
 609                 switch (ctrl & 0x00000f00) {
 610                 case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break;
 611                 case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break;
 612                 case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break;
 613                 case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break;
 614                 case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break;
 615                 case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break;
 616                 default:
 617                         nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl);
 618                         return 0x0000;
 619                 }
 620                 dcb->sorconf.link = mask;
 621         }
 622
 623         mask  = 0x00c0 & (mask << 6);
 624         mask |= 0x0001 << outp;
 625         mask |= 0x0100 << head;
 626
 627         data = dcb_outp_match(bios, type, mask, ver, hdr, dcb);
 628         if (!data)
 629                 return 0x0000;
 630
 631         return nvbios_outp_match(bios, type, mask, ver, hdr, cnt, len, info);
 632 }
 633
 634 static bool
 635 exec_script(struct nv50_disp_priv *priv, int head, int id)
 636 {
 637         struct nouveau_bios *bios = nouveau_bios(priv);
 638         struct nvbios_outp info;
 639         struct dcb_output dcb;
 640         u8  ver, hdr, cnt, len;
 641         u32 ctrl = 0x00000000;
 642         u16 data;
 643         int outp;
 644
 645         for (outp = 0; !(ctrl & (1 << head)) && outp < 8; outp++) {
 646                 ctrl = nv_rd32(priv, 0x640180 + (outp * 0x20));
 647                 if (ctrl & (1 << head))
 648                         break;
 649         }
 650
 651         if (outp == 8)
 652                 return false;
 653
 654         data = exec_lookup(priv, head, outp, ctrl, &dcb, &ver, &hdr, &cnt, &len, &info);
 655         if (data) {
 656                 struct nvbios_init init = {
 657                         .subdev = nv_subdev(priv),
 658                         .bios = bios,
 659                         .offset = info.script[id],
 660                         .outp = &dcb,
 661                         .crtc = head,
 662                         .execute = 1,
 663                 };
 664
 665                 return nvbios_exec(&init) == 0;
 666         }
 667
 668         return false;
 669 }
 670
 671 static u32
 672 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id,
 673             u32 pclk, struct dcb_output *dcb)
 674 {
 675         struct nouveau_bios *bios = nouveau_bios(priv);
 676         struct nvbios_outp info1;
 677         struct nvbios_ocfg info2;
 678         u8  ver, hdr, cnt, len;
 679         u32 ctrl = 0x00000000;
 680         u32 data, conf = ~0;
 681         int outp;
 682
 683         for (outp = 0; !(ctrl & (1 << head)) && outp < 8; outp++) {
 684                 ctrl = nv_rd32(priv, 0x660180 + (outp * 0x20));
 685                 if (ctrl & (1 << head))
 686                         break;
 687         }
 688
 689         if (outp == 8)
 690                 return false;
 691
 692         data = exec_lookup(priv, head, outp, ctrl, dcb, &ver, &hdr, &cnt, &len, &info1);
 693         if (data == 0x0000)
 694                 return conf;
 695
 696         switch (dcb->type) {
 697         case DCB_OUTPUT_TMDS:
 698                 conf = (ctrl & 0x00000f00) >> 8;
 699                 if (pclk >= 165000)
 700                         conf |= 0x0100;
 701                 break;
 702         case DCB_OUTPUT_LVDS:
 703                 conf = priv->sor.lvdsconf;
 704                 break;
 705         case DCB_OUTPUT_DP:
 706                 conf = (ctrl & 0x00000f00) >> 8;
 707                 break;
 708         case DCB_OUTPUT_ANALOG:
 709         default:
 710                 conf = 0x00ff;
 711                 break;
 712         }
 713
 714         data = nvbios_ocfg_match(bios, data, conf, &ver, &hdr, &cnt, &len, &info2);
 715         if (data && id < 0xff) {
 716                 data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk);
 717                 if (data) {
 718                         struct nvbios_init init = {
 719                                 .subdev = nv_subdev(priv),
 720                                 .bios = bios,
 721                                 .offset = data,
 722                                 .outp = dcb,
 723                                 .crtc = head,
 724                                 .execute = 1,
 725                         };
 726
 727                         nvbios_exec(&init);
 728                 }
 729         }
 730
 731         return conf;
 732 }
 733
 734 static void
 735 nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
 736 {
 737         exec_script(priv, head, 1);
 738 }
 739
 740 static void
 741 nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
 742 {
 743         exec_script(priv, head, 2);
 744 }
 745
 746 static void
 747 nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
 748 {
 749         struct nouveau_devinit *devinit = nouveau_devinit(priv);
 750         u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
 751         if (pclk)
 752                 devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
 753         nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000);
 754 }
 755
 756 static void
 757 nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
 758                          struct dcb_output *outp)
 759 {
 760         const int or = ffs(outp->or) - 1;
 761         const u32 ctrl = nv_rd32(priv, 0x660200 + (or   * 0x020));
 762         const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300));
 763         const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
 764         const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1;
 765         const u32 hoff = (head * 0x800);
 766         const u32 soff = (  or * 0x800);
 767         const u32 loff = (link * 0x080) + soff;
 768         const u32 symbol = 100000;
 769         const u32 TU = 64;
 770         u32 dpctrl = nv_rd32(priv, 0x61c10c + loff) & 0x000f0000;
 771         u32 clksor = nv_rd32(priv, 0x612300 + soff);
 772         u32 datarate, link_nr, link_bw, bits;
 773         u64 ratio, value;
 774
 775         if      ((conf & 0x3c0) == 0x180) bits = 30;
 776         else if ((conf & 0x3c0) == 0x140) bits = 24;
 777         else                              bits = 18;
 778         datarate = (pclk * bits) / 8;
 779
 780         if      (dpctrl > 0x00030000) link_nr = 4;
 781         else if (dpctrl > 0x00010000) link_nr = 2;
 782         else                          link_nr = 1;
 783
 784         link_bw  = (clksor & 0x007c0000) >> 18;
 785         link_bw *= 27000;
 786
 787         ratio  = datarate;
 788         ratio *= symbol;
 789         do_div(ratio, link_nr * link_bw);
 790
 791         value  = (symbol - ratio) * TU;
 792         value *= ratio;
 793         do_div(value, symbol);
 794         do_div(value, symbol);
 795
 796         value += 5;
 797         value |= 0x08000000;
 798
 799         nv_wr32(priv, 0x616610 + hoff, value);
 800 }
 801
 802 static void
 803 nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
 804 {
 805         struct dcb_output outp;
 806         u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
 807         u32 conf = exec_clkcmp(priv, head, 0xff, pclk, &outp);
 808         if (conf != ~0) {
 809                 u32 addr, data;
 810
 811                 if (outp.type == DCB_OUTPUT_DP) {
 812                         u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
 813                         switch ((sync & 0x000003c0) >> 6) {
 814                         case 6: pclk = pclk * 30 / 8; break;
 815                         case 5: pclk = pclk * 24 / 8; break;
 816                         case 2:
 817                         default:
 818                                 pclk = pclk * 18 / 8;
 819                                 break;
 820                         }
 821
 822                         nouveau_dp_train(&priv->base, priv->sor.dp,
 823                                          &outp, head, pclk);
 824                 }
 825
 826                 exec_clkcmp(priv, head, 0, pclk, &outp);
 827
 828                 if (outp.type == DCB_OUTPUT_ANALOG) {
 829                         addr = 0x612280 + (ffs(outp.or) - 1) * 0x800;
 830                         data = 0x00000000;
 831                 } else {
 832                         if (outp.type == DCB_OUTPUT_DP)
 833                                 nvd0_disp_intr_unk2_2_tu(priv, head, &outp);
 834                         addr = 0x612300 + (ffs(outp.or) - 1) * 0x800;
 835                         data = (conf & 0x0100) ? 0x00000101 : 0x00000000;
 836                 }
 837
 838                 nv_mask(priv, addr, 0x00000707, data);
 839         }
 840 }
 841
 842 static void
 843 nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
 844 {
 845         struct dcb_output outp;
 846         u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
 847         exec_clkcmp(priv, head, 1, pclk, &outp);
 848 }
 849
 850 void
 851 nvd0_disp_intr_supervisor(struct work_struct *work)
 852 {
 853         struct nv50_disp_priv *priv =
 854                 container_of(work, struct nv50_disp_priv, supervisor);
 855         u32 mask[4];
 856         int head;
 857
 858         nv_debug(priv, "supervisor %08x\n", priv->super);
 859         for (head = 0; head < priv->head.nr; head++) {
 860                 mask[head] = nv_rd32(priv, 0x6101d4 + (head * 0x800));
 861                 nv_debug(priv, "head %d: 0x%08x\n", head, mask[head]);
 862         }
 863
 864         if (priv->super & 0x00000001) {
 865                 for (head = 0; head < priv->head.nr; head++) {
 866                         if (!(mask[head] & 0x00001000))
 867                                 continue;
 868                         nvd0_disp_intr_unk1_0(priv, head);
 869                 }
 870         } else
 871         if (priv->super & 0x00000002) {
 872                 for (head = 0; head < priv->head.nr; head++) {
 873                         if (!(mask[head] & 0x00001000))
 874                                 continue;
 875                         nvd0_disp_intr_unk2_0(priv, head);
 876                 }
 877                 for (head = 0; head < priv->head.nr; head++) {
 878                         if (!(mask[head] & 0x00010000))
 879                                 continue;
 880                         nvd0_disp_intr_unk2_1(priv, head);
 881                 }
 882                 for (head = 0; head < priv->head.nr; head++) {
 883                         if (!(mask[head] & 0x00001000))
 884                                 continue;
 885                         nvd0_disp_intr_unk2_2(priv, head);
 886                 }
 887         } else
 888         if (priv->super & 0x00000004) {
 889                 for (head = 0; head < priv->head.nr; head++) {
 890                         if (!(mask[head] & 0x00001000))
 891                                 continue;
 892                         nvd0_disp_intr_unk4_0(priv, head);
 893                 }
 894         }
 895
 896         for (head = 0; head < priv->head.nr; head++)
 897                 nv_wr32(priv, 0x6101d4 + (head * 0x800), 0x00000000);
 898         nv_wr32(priv, 0x6101d0, 0x80000000);
 899 }
 900
 901 void
 902 nvd0_disp_intr(struct nouveau_subdev *subdev)
 903 {
 904         struct nv50_disp_priv *priv = (void *)subdev;
 905         u32 intr = nv_rd32(priv, 0x610088);
 906         int i;
 907
 908         if (intr & 0x00000001) {
 909                 u32 stat = nv_rd32(priv, 0x61008c);
 910                 nv_wr32(priv, 0x61008c, stat);
 911                 intr &= ~0x00000001;
 912         }
 913
 914         if (intr & 0x00000002) {
 915                 u32 stat = nv_rd32(priv, 0x61009c);
 916                 int chid = ffs(stat) - 1;
 917                 if (chid >= 0) {
 918                         u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12));
 919                         u32 data = nv_rd32(priv, 0x6101f4 + (chid * 12));
 920                         u32 unkn = nv_rd32(priv, 0x6101f8 + (chid * 12));
 921
 922                         nv_error(priv, "chid %d mthd 0x%04x data 0x%08x "
 923                                        "0x%08x 0x%08x\n",
 924                                  chid, (mthd & 0x0000ffc), data, mthd, unkn);
 925                         nv_wr32(priv, 0x61009c, (1 << chid));
 926                         nv_wr32(priv, 0x6101f0 + (chid * 12), 0x90000000);
 927                 }
 928
 929                 intr &= ~0x00000002;
 930         }
 931
 932         if (intr & 0x00100000) {
 933                 u32 stat = nv_rd32(priv, 0x6100ac);
 934                 if (stat & 0x00000007) {
 935                         priv->super = (stat & 0x00000007);
 936                         schedule_work(&priv->supervisor);
 937                         nv_wr32(priv, 0x6100ac, priv->super);
 938                         stat &= ~0x00000007;
 939                 }
 940
 941                 if (stat) {
 942                         nv_info(priv, "unknown intr24 0x%08x\n", stat);
 943                         nv_wr32(priv, 0x6100ac, stat);
 944                 }
 945
 946                 intr &= ~0x00100000;
 947         }
 948
 949         for (i = 0; i < priv->head.nr; i++) {
 950                 u32 mask = 0x01000000 << i;
 951                 if (mask & intr) {
 952                         u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800));
 953                         if (stat & 0x00000001)
 954                                 nouveau_event_trigger(priv->base.vblank, i);
 955                         nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0);
 956                         nv_rd32(priv, 0x6100c0 + (i * 0x800));
 957                 }
 958         }
 959 }
 960
 961 static int
 962 nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 963                struct nouveau_oclass *oclass, void *data, u32 size,
 964                struct nouveau_object **pobject)
 965 {
 966         struct nv50_disp_priv *priv;
 967         int heads = nv_rd32(parent, 0x022448);
 968         int ret;
 969
 970         if (nv_rd32(parent, 0x022500) & 0x00000001)
 971                 return -ENODEV;
 972
 973         ret = nouveau_disp_create(parent, engine, oclass, heads,
 974                                   "PDISP", "display", &priv);
 975         *pobject = nv_object(priv);
 976         if (ret)
 977                 return ret;
 978
 979         nv_engine(priv)->sclass = nvd0_disp_base_oclass;
 980         nv_engine(priv)->cclass = &nv50_disp_cclass;
 981         nv_subdev(priv)->intr = nvd0_disp_intr;
 982         INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
 983         priv->sclass = nvd0_disp_sclass;
 984         priv->head.nr = heads;
 985         priv->dac.nr = 3;
 986         priv->sor.nr = 4;
 987         priv->dac.power = nv50_dac_power;
 988         priv->dac.sense = nv50_dac_sense;
 989         priv->sor.power = nv50_sor_power;
 990         priv->sor.hda_eld = nvd0_hda_eld;
 991         priv->sor.hdmi = nvd0_hdmi_ctrl;
 992         priv->sor.dp = &nvd0_sor_dp_func;
 993         return 0;
 994 }
 995
 996 struct nouveau_oclass
 997 nvd0_disp_oclass = {
 998         .handle = NV_ENGINE(DISP, 0x90),
 999         .ofuncs = &(struct nouveau_ofuncs) {
1000                 .ctor = nvd0_disp_ctor,
1001                 .dtor = _nouveau_disp_dtor,
1002                 .init = _nouveau_disp_init,
1003                 .fini = _nouveau_disp_fini,
1004         },
1005 };