2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/gpuobj.h>
26 #include <core/class.h>
28 #include <subdev/fb.h>
29 #include <subdev/vm/nv04.h>
31 #include <engine/dmaobj.h>
33 struct nv04_dmaeng_priv {
34 struct nouveau_dmaeng base;
38 nv04_dmaobj_bind(struct nouveau_dmaeng *dmaeng,
39 struct nouveau_object *parent,
40 struct nouveau_dmaobj *dmaobj,
41 struct nouveau_gpuobj **pgpuobj)
43 struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaeng);
44 struct nouveau_gpuobj *gpuobj;
45 u32 flags0 = nv_mclass(dmaobj);
46 u32 flags2 = 0x00000000;
47 u64 offset = dmaobj->start & 0xfffff000;
48 u64 adjust = dmaobj->start & 0x00000fff;
49 u32 length = dmaobj->limit - dmaobj->start;
52 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
53 switch (nv_mclass(parent->parent)) {
54 case NV03_CHANNEL_DMA_CLASS:
55 case NV10_CHANNEL_DMA_CLASS:
56 case NV17_CHANNEL_DMA_CLASS:
57 case NV40_CHANNEL_DMA_CLASS:
64 if (dmaobj->target == NV_MEM_TARGET_VM) {
65 if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) {
66 struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0];
68 return nouveau_gpuobj_dup(parent, pgt, pgpuobj);
69 offset = nv_ro32(pgt, 8 + (offset >> 10));
73 dmaobj->target = NV_MEM_TARGET_PCI;
74 dmaobj->access = NV_MEM_ACCESS_RW;
77 switch (dmaobj->target) {
78 case NV_MEM_TARGET_VRAM:
81 case NV_MEM_TARGET_PCI:
84 case NV_MEM_TARGET_PCI_NOSNOOP:
91 switch (dmaobj->access) {
92 case NV_MEM_ACCESS_RO:
95 case NV_MEM_ACCESS_WO:
97 case NV_MEM_ACCESS_RW:
104 ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj);
107 nv_wo32(*pgpuobj, 0x00, flags0 | (adjust << 20));
108 nv_wo32(*pgpuobj, 0x04, length);
109 nv_wo32(*pgpuobj, 0x08, flags2 | offset);
110 nv_wo32(*pgpuobj, 0x0c, flags2 | offset);
117 nv04_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
118 struct nouveau_oclass *oclass, void *data, u32 size,
119 struct nouveau_object **pobject)
121 struct nv04_dmaeng_priv *priv;
124 ret = nouveau_dmaeng_create(parent, engine, oclass, &priv);
125 *pobject = nv_object(priv);
129 nv_engine(priv)->sclass = nouveau_dmaobj_sclass;
130 priv->base.bind = nv04_dmaobj_bind;
134 struct nouveau_oclass
135 nv04_dmaeng_oclass = {
136 .handle = NV_ENGINE(DMAOBJ, 0x04),
137 .ofuncs = &(struct nouveau_ofuncs) {
138 .ctor = nv04_dmaeng_ctor,
139 .dtor = _nouveau_dmaeng_dtor,
140 .init = _nouveau_dmaeng_init,
141 .fini = _nouveau_dmaeng_fini,