drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <nvif/unpack.h>
  27 #include <nvif/class.h>
  28 #include <core/engctx.h>
  29 #include <core/ramht.h>
  30
  31 #include <subdev/instmem.h>
  32 #include <subdev/instmem/nv04.h>
  33 #include <subdev/fb.h>
  34
  35 #include <engine/fifo.h>
  36
  37 #include "nv04.h"
  38
  39 static struct ramfc_desc
  40 nv40_ramfc[] = {
  41         { 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
  42         { 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
  43         { 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
  44         { 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
  45         { 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
  46         { 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
  47         { 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
  48         {  2, 28, 0x18, 28, 0x002058 },
  49         { 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
  50         { 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
  51         { 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
  52         { 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
  53         { 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
  54         { 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
  55         { 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
  56         { 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
  57         { 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
  58         { 32,  0, 0x40,  0, 0x0032e4 },
  59         { 32,  0, 0x44,  0, 0x0032e8 },
  60         { 32,  0, 0x4c,  0, 0x002088 },
  61         { 32,  0, 0x50,  0, 0x003300 },
  62         { 32,  0, 0x54,  0, 0x00330c },
  63         {}
  64 };
  65
  66 /*******************************************************************************
  67  * FIFO channel objects
  68  ******************************************************************************/
  69
  70 static int
  71 nv40_fifo_object_attach(struct nouveau_object *parent,
  72                         struct nouveau_object *object, u32 handle)
  73 {
  74         struct nv04_fifo_priv *priv = (void *)parent->engine;
  75         struct nv04_fifo_chan *chan = (void *)parent;
  76         u32 context, chid = chan->base.chid;
  77         int ret;
  78
  79         if (nv_iclass(object, NV_GPUOBJ_CLASS))
  80                 context = nv_gpuobj(object)->addr >> 4;
  81         else
  82                 context = 0x00000004; /* just non-zero */
  83
  84         switch (nv_engidx(object->engine)) {
  85         case NVDEV_ENGINE_DMAOBJ:
  86         case NVDEV_ENGINE_SW:
  87                 context |= 0x00000000;
  88                 break;
  89         case NVDEV_ENGINE_GR:
  90                 context |= 0x00100000;
  91                 break;
  92         case NVDEV_ENGINE_MPEG:
  93                 context |= 0x00200000;
  94                 break;
  95         default:
  96                 return -EINVAL;
  97         }
  98
  99         context |= chid << 23;
 100
 101         mutex_lock(&nv_subdev(priv)->mutex);
 102         ret = nouveau_ramht_insert(priv->ramht, chid, handle, context);
 103         mutex_unlock(&nv_subdev(priv)->mutex);
 104         return ret;
 105 }
 106
 107 static int
 108 nv40_fifo_context_attach(struct nouveau_object *parent,
 109                          struct nouveau_object *engctx)
 110 {
 111         struct nv04_fifo_priv *priv = (void *)parent->engine;
 112         struct nv04_fifo_chan *chan = (void *)parent;
 113         unsigned long flags;
 114         u32 reg, ctx;
 115
 116         switch (nv_engidx(engctx->engine)) {
 117         case NVDEV_ENGINE_SW:
 118                 return 0;
 119         case NVDEV_ENGINE_GR:
 120                 reg = 0x32e0;
 121                 ctx = 0x38;
 122                 break;
 123         case NVDEV_ENGINE_MPEG:
 124                 reg = 0x330c;
 125                 ctx = 0x54;
 126                 break;
 127         default:
 128                 return -EINVAL;
 129         }
 130
 131         spin_lock_irqsave(&priv->base.lock, flags);
 132         nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4;
 133         nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
 134
 135         if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
 136                 nv_wr32(priv, reg, nv_engctx(engctx)->addr);
 137         nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr);
 138
 139         nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
 140         spin_unlock_irqrestore(&priv->base.lock, flags);
 141         return 0;
 142 }
 143
 144 static int
 145 nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 146                          struct nouveau_object *engctx)
 147 {
 148         struct nv04_fifo_priv *priv = (void *)parent->engine;
 149         struct nv04_fifo_chan *chan = (void *)parent;
 150         unsigned long flags;
 151         u32 reg, ctx;
 152
 153         switch (nv_engidx(engctx->engine)) {
 154         case NVDEV_ENGINE_SW:
 155                 return 0;
 156         case NVDEV_ENGINE_GR:
 157                 reg = 0x32e0;
 158                 ctx = 0x38;
 159                 break;
 160         case NVDEV_ENGINE_MPEG:
 161                 reg = 0x330c;
 162                 ctx = 0x54;
 163                 break;
 164         default:
 165                 return -EINVAL;
 166         }
 167
 168         spin_lock_irqsave(&priv->base.lock, flags);
 169         nv_mask(priv, 0x002500, 0x00000001, 0x00000000);
 170
 171         if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid)
 172                 nv_wr32(priv, reg, 0x00000000);
 173         nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000);
 174
 175         nv_mask(priv, 0x002500, 0x00000001, 0x00000001);
 176         spin_unlock_irqrestore(&priv->base.lock, flags);
 177         return 0;
 178 }
 179
 180 static int
 181 nv40_fifo_chan_ctor(struct nouveau_object *parent,
 182                     struct nouveau_object *engine,
 183                     struct nouveau_oclass *oclass, void *data, u32 size,
 184                     struct nouveau_object **pobject)
 185 {
 186         union {
 187                 struct nv03_channel_dma_v0 v0;
 188         } *args = data;
 189         struct nv04_fifo_priv *priv = (void *)engine;
 190         struct nv04_fifo_chan *chan;
 191         int ret;
 192
 193         nv_ioctl(parent, "create channel dma size %d\n", size);
 194         if (nvif_unpack(args->v0, 0, 0, false)) {
 195                 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
 196                                  "offset %016llx\n", args->v0.version,
 197                          args->v0.pushbuf, args->v0.offset);
 198         } else
 199                 return ret;
 200
 201         ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 202                                           0x1000, args->v0.pushbuf,
 203                                           (1ULL << NVDEV_ENGINE_DMAOBJ) |
 204                                           (1ULL << NVDEV_ENGINE_SW) |
 205                                           (1ULL << NVDEV_ENGINE_GR) |
 206                                           (1ULL << NVDEV_ENGINE_MPEG), &chan);
 207         *pobject = nv_object(chan);
 208         if (ret)
 209                 return ret;
 210
 211         args->v0.chid = chan->base.chid;
 212
 213         nv_parent(chan)->context_attach = nv40_fifo_context_attach;
 214         nv_parent(chan)->context_detach = nv40_fifo_context_detach;
 215         nv_parent(chan)->object_attach = nv40_fifo_object_attach;
 216         nv_parent(chan)->object_detach = nv04_fifo_object_detach;
 217         chan->ramfc = chan->base.chid * 128;
 218
 219         nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset);
 220         nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset);
 221         nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4);
 222         nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 |
 223                              NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 224                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 225 #ifdef __BIG_ENDIAN
 226                              NV_PFIFO_CACHE1_BIG_ENDIAN |
 227 #endif
 228                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
 229         nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff);
 230         return 0;
 231 }
 232
 233 static struct nouveau_ofuncs
 234 nv40_fifo_ofuncs = {
 235         .ctor = nv40_fifo_chan_ctor,
 236         .dtor = nv04_fifo_chan_dtor,
 237         .init = nv04_fifo_chan_init,
 238         .fini = nv04_fifo_chan_fini,
 239         .map  = _nouveau_fifo_channel_map,
 240         .rd32 = _nouveau_fifo_channel_rd32,
 241         .wr32 = _nouveau_fifo_channel_wr32,
 242         .ntfy = _nouveau_fifo_channel_ntfy
 243 };
 244
 245 static struct nouveau_oclass
 246 nv40_fifo_sclass[] = {
 247         { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs },
 248         {}
 249 };
 250
 251 /*******************************************************************************
 252  * FIFO context - basically just the instmem reserved for the channel
 253  ******************************************************************************/
 254
 255 static struct nouveau_oclass
 256 nv40_fifo_cclass = {
 257         .handle = NV_ENGCTX(FIFO, 0x40),
 258         .ofuncs = &(struct nouveau_ofuncs) {
 259                 .ctor = nv04_fifo_context_ctor,
 260                 .dtor = _nouveau_fifo_context_dtor,
 261                 .init = _nouveau_fifo_context_init,
 262                 .fini = _nouveau_fifo_context_fini,
 263                 .rd32 = _nouveau_fifo_context_rd32,
 264                 .wr32 = _nouveau_fifo_context_wr32,
 265         },
 266 };
 267
 268 /*******************************************************************************
 269  * PFIFO engine
 270  ******************************************************************************/
 271
 272 static int
 273 nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 274                struct nouveau_oclass *oclass, void *data, u32 size,
 275                struct nouveau_object **pobject)
 276 {
 277         struct nv04_instmem_priv *imem = nv04_instmem(parent);
 278         struct nv04_fifo_priv *priv;
 279         int ret;
 280
 281         ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv);
 282         *pobject = nv_object(priv);
 283         if (ret)
 284                 return ret;
 285
 286         nouveau_ramht_ref(imem->ramht, &priv->ramht);
 287         nouveau_gpuobj_ref(imem->ramro, &priv->ramro);
 288         nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc);
 289
 290         nv_subdev(priv)->unit = 0x00000100;
 291         nv_subdev(priv)->intr = nv04_fifo_intr;
 292         nv_engine(priv)->cclass = &nv40_fifo_cclass;
 293         nv_engine(priv)->sclass = nv40_fifo_sclass;
 294         priv->base.pause = nv04_fifo_pause;
 295         priv->base.start = nv04_fifo_start;
 296         priv->ramfc_desc = nv40_ramfc;
 297         return 0;
 298 }
 299
 300 static int
 301 nv40_fifo_init(struct nouveau_object *object)
 302 {
 303         struct nv04_fifo_priv *priv = (void *)object;
 304         struct nouveau_fb *pfb = nouveau_fb(object);
 305         int ret;
 306
 307         ret = nouveau_fifo_init(&priv->base);
 308         if (ret)
 309                 return ret;
 310
 311         nv_wr32(priv, 0x002040, 0x000000ff);
 312         nv_wr32(priv, 0x002044, 0x2101ffff);
 313         nv_wr32(priv, 0x002058, 0x00000001);
 314
 315         nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
 316                                        ((priv->ramht->bits - 9) << 16) |
 317                                         (priv->ramht->base.addr >> 8));
 318         nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8);
 319
 320         switch (nv_device(priv)->chipset) {
 321         case 0x47:
 322         case 0x49:
 323         case 0x4b:
 324                 nv_wr32(priv, 0x002230, 0x00000001);
 325         case 0x40:
 326         case 0x41:
 327         case 0x42:
 328         case 0x43:
 329         case 0x45:
 330         case 0x48:
 331                 nv_wr32(priv, 0x002220, 0x00030002);
 332                 break;
 333         default:
 334                 nv_wr32(priv, 0x002230, 0x00000000);
 335                 nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 +
 336                                          priv->ramfc->addr) >> 16) |
 337                                         0x00030000);
 338                 break;
 339         }
 340
 341         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max);
 342
 343         nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff);
 344         nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff);
 345
 346         nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1);
 347         nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1);
 348         nv_wr32(priv, NV03_PFIFO_CACHES, 1);
 349         return 0;
 350 }
 351
 352 struct nouveau_oclass *
 353 nv40_fifo_oclass = &(struct nouveau_oclass) {
 354         .handle = NV_ENGINE(FIFO, 0x40),
 355         .ofuncs = &(struct nouveau_ofuncs) {
 356                 .ctor = nv40_fifo_ctor,
 357                 .dtor = nv04_fifo_dtor,
 358                 .init = nv40_fifo_init,
 359                 .fini = _nouveau_fifo_fini,
 360         },
 361 };