drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/event.h>
  31 #include <core/class.h>
  32 #include <core/enum.h>
  33
  34 #include <subdev/timer.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/vm.h>
  37
  38 #include <engine/dmaobj.h>
  39 #include <engine/fifo.h>
  40
  41 struct nvc0_fifo_priv {
  42         struct nouveau_fifo base;
  43         struct nouveau_gpuobj *playlist[2];
  44         int cur_playlist;
  45         struct {
  46                 struct nouveau_gpuobj *mem;
  47                 struct nouveau_vma bar;
  48         } user;
  49         int spoon_nr;
  50 };
  51
  52 struct nvc0_fifo_base {
  53         struct nouveau_fifo_base base;
  54         struct nouveau_gpuobj *pgd;
  55         struct nouveau_vm *vm;
  56 };
  57
  58 struct nvc0_fifo_chan {
  59         struct nouveau_fifo_chan base;
  60 };
  61
  62 /*******************************************************************************
  63  * FIFO channel objects
  64  ******************************************************************************/
  65
  66 static void
  67 nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv)
  68 {
  69         struct nouveau_bar *bar = nouveau_bar(priv);
  70         struct nouveau_gpuobj *cur;
  71         int i, p;
  72
  73         mutex_lock(&nv_subdev(priv)->mutex);
  74         cur = priv->playlist[priv->cur_playlist];
  75         priv->cur_playlist = !priv->cur_playlist;
  76
  77         for (i = 0, p = 0; i < 128; i++) {
  78                 if (!(nv_rd32(priv, 0x003004 + (i * 8)) & 1))
  79                         continue;
  80                 nv_wo32(cur, p + 0, i);
  81                 nv_wo32(cur, p + 4, 0x00000004);
  82                 p += 8;
  83         }
  84         bar->flush(bar);
  85
  86         nv_wr32(priv, 0x002270, cur->addr >> 12);
  87         nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
  88         if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000))
  89                 nv_error(priv, "playlist update failed\n");
  90         mutex_unlock(&nv_subdev(priv)->mutex);
  91 }
  92
  93 static int
  94 nvc0_fifo_context_attach(struct nouveau_object *parent,
  95                          struct nouveau_object *object)
  96 {
  97         struct nouveau_bar *bar = nouveau_bar(parent);
  98         struct nvc0_fifo_base *base = (void *)parent->parent;
  99         struct nouveau_engctx *ectx = (void *)object;
 100         u32 addr;
 101         int ret;
 102
 103         switch (nv_engidx(object->engine)) {
 104         case NVDEV_ENGINE_SW   : return 0;
 105         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 106         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 107         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 108         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 109         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 110         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 111         default:
 112                 return -EINVAL;
 113         }
 114
 115         if (!ectx->vma.node) {
 116                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 117                                             NV_MEM_ACCESS_RW, &ectx->vma);
 118                 if (ret)
 119                         return ret;
 120
 121                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 122         }
 123
 124         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 125         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 126         bar->flush(bar);
 127         return 0;
 128 }
 129
 130 static int
 131 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 132                          struct nouveau_object *object)
 133 {
 134         struct nouveau_bar *bar = nouveau_bar(parent);
 135         struct nvc0_fifo_priv *priv = (void *)parent->engine;
 136         struct nvc0_fifo_base *base = (void *)parent->parent;
 137         struct nvc0_fifo_chan *chan = (void *)parent;
 138         u32 addr;
 139
 140         switch (nv_engidx(object->engine)) {
 141         case NVDEV_ENGINE_SW   : return 0;
 142         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 143         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 144         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 145         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 146         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 147         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 148         default:
 149                 return -EINVAL;
 150         }
 151
 152         nv_wr32(priv, 0x002634, chan->base.chid);
 153         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 154                 nv_error(priv, "channel %d [%s] kick timeout\n",
 155                          chan->base.chid, nouveau_client_name(chan));
 156                 if (suspend)
 157                         return -EBUSY;
 158         }
 159
 160         nv_wo32(base, addr + 0x00, 0x00000000);
 161         nv_wo32(base, addr + 0x04, 0x00000000);
 162         bar->flush(bar);
 163         return 0;
 164 }
 165
 166 static int
 167 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
 168                     struct nouveau_object *engine,
 169                     struct nouveau_oclass *oclass, void *data, u32 size,
 170                     struct nouveau_object **pobject)
 171 {
 172         struct nouveau_bar *bar = nouveau_bar(parent);
 173         struct nvc0_fifo_priv *priv = (void *)engine;
 174         struct nvc0_fifo_base *base = (void *)parent;
 175         struct nvc0_fifo_chan *chan;
 176         struct nv50_channel_ind_class *args = data;
 177         u64 usermem, ioffset, ilength;
 178         int ret, i;
 179
 180         if (size < sizeof(*args))
 181                 return -EINVAL;
 182
 183         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 184                                           priv->user.bar.offset, 0x1000,
 185                                           args->pushbuf,
 186                                           (1ULL << NVDEV_ENGINE_SW) |
 187                                           (1ULL << NVDEV_ENGINE_GR) |
 188                                           (1ULL << NVDEV_ENGINE_COPY0) |
 189                                           (1ULL << NVDEV_ENGINE_COPY1) |
 190                                           (1ULL << NVDEV_ENGINE_BSP) |
 191                                           (1ULL << NVDEV_ENGINE_VP) |
 192                                           (1ULL << NVDEV_ENGINE_PPP), &chan);
 193         *pobject = nv_object(chan);
 194         if (ret)
 195                 return ret;
 196
 197         nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
 198         nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
 199
 200         usermem = chan->base.chid * 0x1000;
 201         ioffset = args->ioffset;
 202         ilength = order_base_2(args->ilength / 8);
 203
 204         for (i = 0; i < 0x1000; i += 4)
 205                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 206
 207         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 208         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 209         nv_wo32(base, 0x10, 0x0000face);
 210         nv_wo32(base, 0x30, 0xfffff902);
 211         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 212         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 213         nv_wo32(base, 0x54, 0x00000002);
 214         nv_wo32(base, 0x84, 0x20400000);
 215         nv_wo32(base, 0x94, 0x30000001);
 216         nv_wo32(base, 0x9c, 0x00000100);
 217         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 218         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 219         nv_wo32(base, 0xac, 0x0000001f);
 220         nv_wo32(base, 0xb8, 0xf8000000);
 221         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 222         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 223         bar->flush(bar);
 224         return 0;
 225 }
 226
 227 static int
 228 nvc0_fifo_chan_init(struct nouveau_object *object)
 229 {
 230         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 231         struct nvc0_fifo_priv *priv = (void *)object->engine;
 232         struct nvc0_fifo_chan *chan = (void *)object;
 233         u32 chid = chan->base.chid;
 234         int ret;
 235
 236         ret = nouveau_fifo_channel_init(&chan->base);
 237         if (ret)
 238                 return ret;
 239
 240         nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 241         nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
 242         nvc0_fifo_playlist_update(priv);
 243         return 0;
 244 }
 245
 246 static int
 247 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 248 {
 249         struct nvc0_fifo_priv *priv = (void *)object->engine;
 250         struct nvc0_fifo_chan *chan = (void *)object;
 251         u32 chid = chan->base.chid;
 252         u32 mask, engine;
 253
 254         nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 255         nvc0_fifo_playlist_update(priv);
 256         mask = nv_rd32(priv, 0x0025a4);
 257         for (engine = 0; mask && engine < 16; engine++) {
 258                 if (!(mask & (1 << engine)))
 259                         continue;
 260                 nv_mask(priv, 0x0025a8 + (engine * 4), 0x00000000, 0x00000000);
 261                 mask &= ~(1 << engine);
 262         }
 263         nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
 264
 265         return nouveau_fifo_channel_fini(&chan->base, suspend);
 266 }
 267
 268 static struct nouveau_ofuncs
 269 nvc0_fifo_ofuncs = {
 270         .ctor = nvc0_fifo_chan_ctor,
 271         .dtor = _nouveau_fifo_channel_dtor,
 272         .init = nvc0_fifo_chan_init,
 273         .fini = nvc0_fifo_chan_fini,
 274         .rd32 = _nouveau_fifo_channel_rd32,
 275         .wr32 = _nouveau_fifo_channel_wr32,
 276 };
 277
 278 static struct nouveau_oclass
 279 nvc0_fifo_sclass[] = {
 280         { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs },
 281         {}
 282 };
 283
 284 /*******************************************************************************
 285  * FIFO context - instmem heap and vm setup
 286  ******************************************************************************/
 287
 288 static int
 289 nvc0_fifo_context_ctor(struct nouveau_object *parent,
 290                        struct nouveau_object *engine,
 291                        struct nouveau_oclass *oclass, void *data, u32 size,
 292                        struct nouveau_object **pobject)
 293 {
 294         struct nvc0_fifo_base *base;
 295         int ret;
 296
 297         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 298                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 299                                           NVOBJ_FLAG_HEAP, &base);
 300         *pobject = nv_object(base);
 301         if (ret)
 302                 return ret;
 303
 304         ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
 305                                 &base->pgd);
 306         if (ret)
 307                 return ret;
 308
 309         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 310         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 311         nv_wo32(base, 0x0208, 0xffffffff);
 312         nv_wo32(base, 0x020c, 0x000000ff);
 313
 314         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 315         if (ret)
 316                 return ret;
 317
 318         return 0;
 319 }
 320
 321 static void
 322 nvc0_fifo_context_dtor(struct nouveau_object *object)
 323 {
 324         struct nvc0_fifo_base *base = (void *)object;
 325         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 326         nouveau_gpuobj_ref(NULL, &base->pgd);
 327         nouveau_fifo_context_destroy(&base->base);
 328 }
 329
 330 static struct nouveau_oclass
 331 nvc0_fifo_cclass = {
 332         .handle = NV_ENGCTX(FIFO, 0xc0),
 333         .ofuncs = &(struct nouveau_ofuncs) {
 334                 .ctor = nvc0_fifo_context_ctor,
 335                 .dtor = nvc0_fifo_context_dtor,
 336                 .init = _nouveau_fifo_context_init,
 337                 .fini = _nouveau_fifo_context_fini,
 338                 .rd32 = _nouveau_fifo_context_rd32,
 339                 .wr32 = _nouveau_fifo_context_wr32,
 340         },
 341 };
 342
 343 /*******************************************************************************
 344  * PFIFO engine
 345  ******************************************************************************/
 346
 347 static const struct nouveau_enum nvc0_fifo_fault_unit[] = {
 348         { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
 349         { 0x03, "PEEPHOLE" },
 350         { 0x04, "BAR1" },
 351         { 0x05, "BAR3" },
 352         { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 353         { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
 354         { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
 355         { 0x13, "PCOUNTER" },
 356         { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
 357         { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
 358         { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
 359         { 0x17, "PDAEMON" },
 360         {}
 361 };
 362
 363 static const struct nouveau_enum nvc0_fifo_fault_reason[] = {
 364         { 0x00, "PT_NOT_PRESENT" },
 365         { 0x01, "PT_TOO_SHORT" },
 366         { 0x02, "PAGE_NOT_PRESENT" },
 367         { 0x03, "VM_LIMIT_EXCEEDED" },
 368         { 0x04, "NO_CHANNEL" },
 369         { 0x05, "PAGE_SYSTEM_ONLY" },
 370         { 0x06, "PAGE_READ_ONLY" },
 371         { 0x0a, "COMPRESSED_SYSRAM" },
 372         { 0x0c, "INVALID_STORAGE_TYPE" },
 373         {}
 374 };
 375
 376 static const struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
 377         { 0x01, "PCOPY0" },
 378         { 0x02, "PCOPY1" },
 379         { 0x04, "DISPATCH" },
 380         { 0x05, "CTXCTL" },
 381         { 0x06, "PFIFO" },
 382         { 0x07, "BAR_READ" },
 383         { 0x08, "BAR_WRITE" },
 384         { 0x0b, "PVP" },
 385         { 0x0c, "PPPP" },
 386         { 0x0d, "PBSP" },
 387         { 0x11, "PCOUNTER" },
 388         { 0x12, "PDAEMON" },
 389         { 0x14, "CCACHE" },
 390         { 0x15, "CCACHE_POST" },
 391         {}
 392 };
 393
 394 static const struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
 395         { 0x01, "TEX" },
 396         { 0x0c, "ESETUP" },
 397         { 0x0e, "CTXCTL" },
 398         { 0x0f, "PROP" },
 399         {}
 400 };
 401
 402 static const struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
 403 /*      { 0x00008000, "" }      seen with null ib push */
 404         { 0x00200000, "ILLEGAL_MTHD" },
 405         { 0x00800000, "EMPTY_SUBC" },
 406         {}
 407 };
 408
 409 static void
 410 nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
 411 {
 412         u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
 413         u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
 414         u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
 415         u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
 416         u32 client = (stat & 0x00001f00) >> 8;
 417         const struct nouveau_enum *en;
 418         struct nouveau_engine *engine;
 419         struct nouveau_object *engctx = NULL;
 420
 421         switch (unit) {
 422         case 3: /* PEEPHOLE */
 423                 nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
 424                 break;
 425         case 4: /* BAR1 */
 426                 nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
 427                 break;
 428         case 5: /* BAR3 */
 429                 nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
 430                 break;
 431         default:
 432                 break;
 433         }
 434
 435         nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ?
 436                  "write" : "read", (u64)vahi << 32 | valo);
 437         nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
 438         pr_cont("] from ");
 439         en = nouveau_enum_print(nvc0_fifo_fault_unit, unit);
 440         if (stat & 0x00000040) {
 441                 pr_cont("/");
 442                 nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
 443         } else {
 444                 pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
 445                 nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
 446         }
 447
 448         if (en && en->data2) {
 449                 engine = nouveau_engine(priv, en->data2);
 450                 if (engine)
 451                         engctx = nouveau_engctx_get(engine, inst);
 452
 453         }
 454         pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
 455                         nouveau_client_name(engctx));
 456
 457         nouveau_engctx_put(engctx);
 458 }
 459
 460 static int
 461 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 462 {
 463         struct nvc0_fifo_chan *chan = NULL;
 464         struct nouveau_handle *bind;
 465         unsigned long flags;
 466         int ret = -EINVAL;
 467
 468         spin_lock_irqsave(&priv->base.lock, flags);
 469         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 470                 chan = (void *)priv->base.channel[chid];
 471         if (unlikely(!chan))
 472                 goto out;
 473
 474         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 475         if (likely(bind)) {
 476                 if (!mthd || !nv_call(bind->object, mthd, data))
 477                         ret = 0;
 478                 nouveau_namedb_put(bind);
 479         }
 480
 481 out:
 482         spin_unlock_irqrestore(&priv->base.lock, flags);
 483         return ret;
 484 }
 485
 486 static void
 487 nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
 488 {
 489         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 490         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 491         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 492         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
 493         u32 subc = (addr & 0x00070000) >> 16;
 494         u32 mthd = (addr & 0x00003ffc);
 495         u32 show = stat;
 496
 497         if (stat & 0x00200000) {
 498                 if (mthd == 0x0054) {
 499                         if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
 500                                 show &= ~0x00200000;
 501                 }
 502         }
 503
 504         if (stat & 0x00800000) {
 505                 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
 506                         show &= ~0x00800000;
 507         }
 508
 509         if (show) {
 510                 nv_error(priv, "SUBFIFO%d:", unit);
 511                 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
 512                 pr_cont("\n");
 513                 nv_error(priv,
 514                          "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
 515                          unit, chid,
 516                          nouveau_client_name_for_fifo_chid(&priv->base, chid),
 517                          subc, mthd, data);
 518         }
 519
 520         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 521         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 522 }
 523
 524 static void
 525 nvc0_fifo_intr(struct nouveau_subdev *subdev)
 526 {
 527         struct nvc0_fifo_priv *priv = (void *)subdev;
 528         u32 mask = nv_rd32(priv, 0x002140);
 529         u32 stat = nv_rd32(priv, 0x002100) & mask;
 530
 531         if (stat & 0x00000001) {
 532                 u32 intr = nv_rd32(priv, 0x00252c);
 533                 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
 534                 nv_wr32(priv, 0x002100, 0x00000001);
 535                 stat &= ~0x00000001;
 536         }
 537
 538         if (stat & 0x00000100) {
 539                 u32 intr = nv_rd32(priv, 0x00254c);
 540                 nv_warn(priv, "INTR 0x00000100: 0x%08x\n", intr);
 541                 nv_wr32(priv, 0x002100, 0x00000100);
 542                 stat &= ~0x00000100;
 543         }
 544
 545         if (stat & 0x00010000) {
 546                 u32 intr = nv_rd32(priv, 0x00256c);
 547                 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
 548                 nv_wr32(priv, 0x002100, 0x00010000);
 549                 stat &= ~0x00010000;
 550         }
 551
 552         if (stat & 0x01000000) {
 553                 u32 intr = nv_rd32(priv, 0x00258c);
 554                 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
 555                 nv_wr32(priv, 0x002100, 0x01000000);
 556                 stat &= ~0x01000000;
 557         }
 558
 559         if (stat & 0x10000000) {
 560                 u32 units = nv_rd32(priv, 0x00259c);
 561                 u32 u = units;
 562
 563                 while (u) {
 564                         int i = ffs(u) - 1;
 565                         nvc0_fifo_isr_vm_fault(priv, i);
 566                         u &= ~(1 << i);
 567                 }
 568
 569                 nv_wr32(priv, 0x00259c, units);
 570                 stat &= ~0x10000000;
 571         }
 572
 573         if (stat & 0x20000000) {
 574                 u32 units = nv_rd32(priv, 0x0025a0);
 575                 u32 u = units;
 576
 577                 while (u) {
 578                         int i = ffs(u) - 1;
 579                         nvc0_fifo_isr_subfifo_intr(priv, i);
 580                         u &= ~(1 << i);
 581                 }
 582
 583                 nv_wr32(priv, 0x0025a0, units);
 584                 stat &= ~0x20000000;
 585         }
 586
 587         if (stat & 0x40000000) {
 588                 u32 intr0 = nv_rd32(priv, 0x0025a4);
 589                 u32 intr1 = nv_mask(priv, 0x002a00, 0x00000000, 0x00000);
 590                 nv_debug(priv, "INTR 0x40000000: 0x%08x 0x%08x\n",
 591                                intr0, intr1);
 592                 stat &= ~0x40000000;
 593         }
 594
 595         if (stat & 0x80000000) {
 596                 u32 intr = nv_mask(priv, 0x0025a8, 0x00000000, 0x00000000);
 597                 nouveau_event_trigger(priv->base.uevent, 0);
 598                 nv_debug(priv, "INTR 0x80000000: 0x%08x\n", intr);
 599                 stat &= ~0x80000000;
 600         }
 601
 602         if (stat) {
 603                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 604                 nv_wr32(priv, 0x002100, stat);
 605                 nv_wr32(priv, 0x002140, 0);
 606         }
 607 }
 608
 609 static void
 610 nvc0_fifo_uevent_enable(struct nouveau_event *event, int index)
 611 {
 612         struct nvc0_fifo_priv *priv = event->priv;
 613         nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
 614 }
 615
 616 static void
 617 nvc0_fifo_uevent_disable(struct nouveau_event *event, int index)
 618 {
 619         struct nvc0_fifo_priv *priv = event->priv;
 620         nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 621 }
 622
 623 static int
 624 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 625                struct nouveau_oclass *oclass, void *data, u32 size,
 626                struct nouveau_object **pobject)
 627 {
 628         struct nvc0_fifo_priv *priv;
 629         int ret;
 630
 631         ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
 632         *pobject = nv_object(priv);
 633         if (ret)
 634                 return ret;
 635
 636         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
 637                                 &priv->playlist[0]);
 638         if (ret)
 639                 return ret;
 640
 641         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
 642                                 &priv->playlist[1]);
 643         if (ret)
 644                 return ret;
 645
 646         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
 647                                 &priv->user.mem);
 648         if (ret)
 649                 return ret;
 650
 651         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 652                                 &priv->user.bar);
 653         if (ret)
 654                 return ret;
 655
 656         priv->base.uevent->enable = nvc0_fifo_uevent_enable;
 657         priv->base.uevent->disable = nvc0_fifo_uevent_disable;
 658         priv->base.uevent->priv = priv;
 659
 660         nv_subdev(priv)->unit = 0x00000100;
 661         nv_subdev(priv)->intr = nvc0_fifo_intr;
 662         nv_engine(priv)->cclass = &nvc0_fifo_cclass;
 663         nv_engine(priv)->sclass = nvc0_fifo_sclass;
 664         return 0;
 665 }
 666
 667 static void
 668 nvc0_fifo_dtor(struct nouveau_object *object)
 669 {
 670         struct nvc0_fifo_priv *priv = (void *)object;
 671
 672         nouveau_gpuobj_unmap(&priv->user.bar);
 673         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 674         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 675         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 676
 677         nouveau_fifo_destroy(&priv->base);
 678 }
 679
 680 static int
 681 nvc0_fifo_init(struct nouveau_object *object)
 682 {
 683         struct nvc0_fifo_priv *priv = (void *)object;
 684         int ret, i;
 685
 686         ret = nouveau_fifo_init(&priv->base);
 687         if (ret)
 688                 return ret;
 689
 690         nv_wr32(priv, 0x000204, 0xffffffff);
 691         nv_wr32(priv, 0x002204, 0xffffffff);
 692
 693         priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
 694         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 695
 696         /* assign engines to subfifos */
 697         if (priv->spoon_nr >= 3) {
 698                 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
 699                 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
 700                 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
 701                 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
 702                 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
 703                 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
 704         }
 705
 706         /* PSUBFIFO[n] */
 707         for (i = 0; i < priv->spoon_nr; i++) {
 708                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 709                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 710                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 711         }
 712
 713         nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
 714         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 715
 716         nv_wr32(priv, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
 717         nv_wr32(priv, 0x002100, 0xffffffff);
 718         nv_wr32(priv, 0x002140, 0x3fffffff);
 719         nv_wr32(priv, 0x002628, 0x00000001); /* makes mthd 0x20 work */
 720         return 0;
 721 }
 722
 723 struct nouveau_oclass
 724 nvc0_fifo_oclass = {
 725         .handle = NV_ENGINE(FIFO, 0xc0),
 726         .ofuncs = &(struct nouveau_ofuncs) {
 727                 .ctor = nvc0_fifo_ctor,
 728                 .dtor = nvc0_fifo_dtor,
 729                 .init = nvc0_fifo_init,
 730                 .fini = _nouveau_fifo_fini,
 731         },
 732 };