drivers/gpu/drm/nouveau/core/include/core/device.h

   1 #ifndef __NOUVEAU_DEVICE_H__
   2 #define __NOUVEAU_DEVICE_H__
   3
   4 #include <core/object.h>
   5 #include <core/subdev.h>
   6 #include <core/engine.h>
   7
   8 enum nv_subdev_type {
   9         NVDEV_ENGINE_DEVICE,
  10         NVDEV_SUBDEV_VBIOS,
  11
  12         /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
  13          * *any* of them are initialised.  This subdev category is used
  14          * for any subdevs that the VBIOS init table parsing may call out
  15          * to during POST.
  16          */
  17         NVDEV_SUBDEV_DEVINIT,
  18         NVDEV_SUBDEV_GPIO,
  19         NVDEV_SUBDEV_I2C,
  20         NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
  21
  22         /* This grouping of subdevs are initialised right after they've
  23          * been created, and are allowed to assume any subdevs in the
  24          * list above them exist and have been initialised.
  25          */
  26         NVDEV_SUBDEV_MXM,
  27         NVDEV_SUBDEV_MC,
  28         NVDEV_SUBDEV_BUS,
  29         NVDEV_SUBDEV_TIMER,
  30         NVDEV_SUBDEV_FB,
  31         NVDEV_SUBDEV_LTCG,
  32         NVDEV_SUBDEV_IBUS,
  33         NVDEV_SUBDEV_INSTMEM,
  34         NVDEV_SUBDEV_VM,
  35         NVDEV_SUBDEV_BAR,
  36         NVDEV_SUBDEV_PWR,
  37         NVDEV_SUBDEV_VOLT,
  38         NVDEV_SUBDEV_THERM,
  39         NVDEV_SUBDEV_CLOCK,
  40
  41         NVDEV_ENGINE_FIRST,
  42         NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
  43         NVDEV_ENGINE_IFB,
  44         NVDEV_ENGINE_FIFO,
  45         NVDEV_ENGINE_SW,
  46         NVDEV_ENGINE_GR,
  47         NVDEV_ENGINE_MPEG,
  48         NVDEV_ENGINE_ME,
  49         NVDEV_ENGINE_VP,
  50         NVDEV_ENGINE_CRYPT,
  51         NVDEV_ENGINE_BSP,
  52         NVDEV_ENGINE_PPP,
  53         NVDEV_ENGINE_COPY0,
  54         NVDEV_ENGINE_COPY1,
  55         NVDEV_ENGINE_COPY2,
  56         NVDEV_ENGINE_VIC,
  57         NVDEV_ENGINE_VENC,
  58         NVDEV_ENGINE_DISP,
  59         NVDEV_ENGINE_PERFMON,
  60
  61         NVDEV_SUBDEV_NR,
  62 };
  63
  64 struct nouveau_device {
  65         struct nouveau_engine base;
  66         struct list_head head;
  67
  68         struct pci_dev *pdev;
  69         struct platform_device *platformdev;
  70         u64 handle;
  71
  72         const char *cfgopt;
  73         const char *dbgopt;
  74         const char *name;
  75         const char *cname;
  76         u64 disable_mask;
  77
  78         enum {
  79                 NV_04    = 0x04,
  80                 NV_10    = 0x10,
  81                 NV_11    = 0x11,
  82                 NV_20    = 0x20,
  83                 NV_30    = 0x30,
  84                 NV_40    = 0x40,
  85                 NV_50    = 0x50,
  86                 NV_C0    = 0xc0,
  87                 NV_D0    = 0xd0,
  88                 NV_E0    = 0xe0,
  89                 GM100    = 0x110,
  90         } card_type;
  91         u32 chipset;
  92         u32 crystal;
  93
  94         struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR];
  95         struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
  96 };
  97
  98 static inline struct nouveau_device *
  99 nv_device(void *obj)
 100 {
 101         struct nouveau_object *object = nv_object(obj);
 102         struct nouveau_object *device = object;
 103
 104         if (device->engine)
 105                 device = device->engine;
 106         if (device->parent)
 107                 device = device->parent;
 108
 109 #if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
 110         if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) ||
 111                      (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) {
 112                 nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x",
 113                           nv_hclass(object), nv_hclass(device));
 114         }
 115 #endif
 116
 117         return (void *)device;
 118 }
 119
 120 static inline struct nouveau_subdev *
 121 nouveau_subdev(void *obj, int sub)
 122 {
 123         if (nv_device(obj)->subdev[sub])
 124                 return nv_subdev(nv_device(obj)->subdev[sub]);
 125         return NULL;
 126 }
 127
 128 static inline struct nouveau_engine *
 129 nouveau_engine(void *obj, int sub)
 130 {
 131         struct nouveau_subdev *subdev = nouveau_subdev(obj, sub);
 132         if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS))
 133                 return nv_engine(subdev);
 134         return NULL;
 135 }
 136
 137 static inline bool
 138 nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub)
 139 {
 140         struct nouveau_device *device = nv_device(object);
 141         return device->pdev->device == dev &&
 142                device->pdev->subsystem_vendor == ven &&
 143                device->pdev->subsystem_device == sub;
 144 }
 145
 146 static inline bool
 147 nv_device_is_pci(struct nouveau_device *device)
 148 {
 149         return device->pdev != NULL;
 150 }
 151
 152 static inline struct device *
 153 nv_device_base(struct nouveau_device *device)
 154 {
 155         return nv_device_is_pci(device) ? &device->pdev->dev :
 156                                           &device->platformdev->dev;
 157 }
 158
 159 resource_size_t
 160 nv_device_resource_start(struct nouveau_device *device, unsigned int bar);
 161
 162 resource_size_t
 163 nv_device_resource_len(struct nouveau_device *device, unsigned int bar);
 164
 165 dma_addr_t
 166 nv_device_map_page(struct nouveau_device *device, struct page *page);
 167
 168 void
 169 nv_device_unmap_page(struct nouveau_device *device, dma_addr_t addr);
 170
 171 int
 172 nv_device_get_irq(struct nouveau_device *device, bool stall);
 173
 174 #endif