2 * Copyright 2012 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/fb.h>
26 #include <subdev/timer.h>
31 gf100_ltcg_lts_isr(struct gf100_ltcg_priv *priv, int ltc, int lts)
33 u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400);
34 u32 stat = nv_rd32(priv, base + 0x020);
37 nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat);
38 nv_wr32(priv, base + 0x020, stat);
43 gf100_ltcg_intr(struct nouveau_subdev *subdev)
45 struct gf100_ltcg_priv *priv = (void *)subdev;
48 mask = nv_rd32(priv, 0x00017c);
50 u32 lts, ltc = __ffs(mask);
51 for (lts = 0; lts < priv->lts_nr; lts++)
52 gf100_ltcg_lts_isr(priv, ltc, lts);
56 /* we do something horribly wrong and upset PMFB a lot, so mask off
57 * interrupts from it after the first one until it's fixed
59 nv_mask(priv, 0x000640, 0x02000000, 0x00000000);
63 gf100_ltcg_tags_alloc(struct nouveau_ltcg *ltcg, u32 n,
64 struct nouveau_mm_node **pnode)
66 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
69 ret = nouveau_mm_head(&priv->tags, 1, n, n, 1, pnode);
77 gf100_ltcg_tags_free(struct nouveau_ltcg *ltcg, struct nouveau_mm_node **pnode)
79 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
81 nouveau_mm_free(&priv->tags, pnode);
85 gf100_ltcg_tags_clear(struct nouveau_ltcg *ltcg, u32 first, u32 count)
87 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
88 u32 last = first + count - 1;
91 BUG_ON((first > last) || (last >= priv->num_tags));
93 nv_wr32(priv, 0x17e8cc, first);
94 nv_wr32(priv, 0x17e8d0, last);
95 nv_wr32(priv, 0x17e8c8, 0x4); /* trigger clear */
97 /* wait until it's finished with clearing */
98 for (p = 0; p < priv->ltc_nr; ++p) {
99 for (i = 0; i < priv->lts_nr; ++i)
100 nv_wait(priv, 0x1410c8 + p * 0x2000 + i * 0x400, ~0, 0);
104 /* TODO: Figure out tag memory details and drop the over-cautious allocation.
107 gf100_ltcg_init_tag_ram(struct nouveau_fb *pfb, struct gf100_ltcg_priv *priv)
109 u32 tag_size, tag_margin, tag_align;
112 /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
113 priv->num_tags = (pfb->ram->size >> 17) / 4;
114 if (priv->num_tags > (1 << 17))
115 priv->num_tags = 1 << 17; /* we have 17 bits in PTE */
116 priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */
118 tag_align = priv->ltc_nr * 0x800;
119 tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align;
121 /* 4 part 4 sub: 0x2000 bytes for 56 tags */
122 /* 3 part 4 sub: 0x6000 bytes for 168 tags */
124 * About 147 bytes per tag. Let's be safe and allocate x2, which makes
125 * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags.
127 * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %.
129 tag_size = (priv->num_tags / 64) * 0x6000 + tag_margin;
130 tag_size += tag_align;
131 tag_size = (tag_size + 0xfff) >> 12; /* round up */
133 ret = nouveau_mm_tail(&pfb->vram, 1, tag_size, tag_size, 1,
138 u64 tag_base = (priv->tag_ram->offset << 12) + tag_margin;
140 tag_base += tag_align - 1;
141 ret = do_div(tag_base, tag_align);
143 priv->tag_base = tag_base;
145 ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1);
151 gf100_ltcg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
152 struct nouveau_oclass *oclass, void *data, u32 size,
153 struct nouveau_object **pobject)
155 struct gf100_ltcg_priv *priv;
156 struct nouveau_fb *pfb = nouveau_fb(parent);
160 ret = nouveau_ltcg_create(parent, engine, oclass, &priv);
161 *pobject = nv_object(priv);
165 parts = nv_rd32(priv, 0x022438);
166 mask = nv_rd32(priv, 0x022554);
167 for (i = 0; i < parts; i++) {
168 if (!(mask & (1 << i)))
171 priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28;
173 ret = gf100_ltcg_init_tag_ram(pfb, priv);
177 priv->base.tags_alloc = gf100_ltcg_tags_alloc;
178 priv->base.tags_free = gf100_ltcg_tags_free;
179 priv->base.tags_clear = gf100_ltcg_tags_clear;
181 nv_subdev(priv)->intr = gf100_ltcg_intr;
186 gf100_ltcg_dtor(struct nouveau_object *object)
188 struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
189 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
190 struct nouveau_fb *pfb = nouveau_fb(ltcg->base.base.parent);
192 nouveau_mm_fini(&priv->tags);
193 nouveau_mm_free(&pfb->vram, &priv->tag_ram);
195 nouveau_ltcg_destroy(ltcg);
199 gf100_ltcg_init(struct nouveau_object *object)
201 struct nouveau_ltcg *ltcg = (struct nouveau_ltcg *)object;
202 struct gf100_ltcg_priv *priv = (struct gf100_ltcg_priv *)ltcg;
205 ret = nouveau_ltcg_init(ltcg);
209 nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */
210 nv_wr32(priv, 0x17e8d8, priv->ltc_nr);
211 if (nv_device(ltcg)->card_type >= NV_E0)
212 nv_wr32(priv, 0x17e000, priv->ltc_nr);
213 nv_wr32(priv, 0x17e8d4, priv->tag_base);
217 struct nouveau_oclass *
218 gf100_ltcg_oclass = &(struct nouveau_oclass) {
219 .handle = NV_SUBDEV(LTCG, 0xc0),
220 .ofuncs = &(struct nouveau_ofuncs) {
221 .ctor = gf100_ltcg_ctor,
222 .dtor = gf100_ltcg_dtor,
223 .init = gf100_ltcg_init,
224 .fini = _nouveau_ltcg_fini,