drivers/gpu/drm/nouveau/core/subdev/pwr/base.c

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <subdev/timer.h>
  26
  27 #include "priv.h"
  28
  29 static void
  30 nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable)
  31 {
  32         const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr);
  33         if (impl->pgob)
  34                 impl->pgob(ppwr, enable);
  35 }
  36
  37 static int
  38 nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2],
  39                  u32 process, u32 message, u32 data0, u32 data1)
  40 {
  41         struct nouveau_subdev *subdev = nv_subdev(ppwr);
  42         u32 addr;
  43
  44         /* wait for a free slot in the fifo */
  45         addr  = nv_rd32(ppwr, 0x10a4a0);
  46         if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8))
  47                 return -EBUSY;
  48
  49         /* we currently only support a single process at a time waiting
  50          * on a synchronous reply, take the PPWR mutex and tell the
  51          * receive handler what we're waiting for
  52          */
  53         if (reply) {
  54                 mutex_lock(&subdev->mutex);
  55                 ppwr->recv.message = message;
  56                 ppwr->recv.process = process;
  57         }
  58
  59         /* acquire data segment access */
  60         do {
  61                 nv_wr32(ppwr, 0x10a580, 0x00000001);
  62         } while (nv_rd32(ppwr, 0x10a580) != 0x00000001);
  63
  64         /* write the packet */
  65         nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) +
  66                                 ppwr->send.base));
  67         nv_wr32(ppwr, 0x10a1c4, process);
  68         nv_wr32(ppwr, 0x10a1c4, message);
  69         nv_wr32(ppwr, 0x10a1c4, data0);
  70         nv_wr32(ppwr, 0x10a1c4, data1);
  71         nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f);
  72
  73         /* release data segment access */
  74         nv_wr32(ppwr, 0x10a580, 0x00000000);
  75
  76         /* wait for reply, if requested */
  77         if (reply) {
  78                 wait_event(ppwr->recv.wait, (ppwr->recv.process == 0));
  79                 reply[0] = ppwr->recv.data[0];
  80                 reply[1] = ppwr->recv.data[1];
  81                 mutex_unlock(&subdev->mutex);
  82         }
  83
  84         return 0;
  85 }
  86
  87 static void
  88 nouveau_pwr_recv(struct work_struct *work)
  89 {
  90         struct nouveau_pwr *ppwr =
  91                 container_of(work, struct nouveau_pwr, recv.work);
  92         u32 process, message, data0, data1;
  93
  94         /* nothing to do if GET == PUT */
  95         u32 addr =  nv_rd32(ppwr, 0x10a4cc);
  96         if (addr == nv_rd32(ppwr, 0x10a4c8))
  97                 return;
  98
  99         /* acquire data segment access */
 100         do {
 101                 nv_wr32(ppwr, 0x10a580, 0x00000002);
 102         } while (nv_rd32(ppwr, 0x10a580) != 0x00000002);
 103
 104         /* read the packet */
 105         nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) +
 106                                 ppwr->recv.base));
 107         process = nv_rd32(ppwr, 0x10a1c4);
 108         message = nv_rd32(ppwr, 0x10a1c4);
 109         data0   = nv_rd32(ppwr, 0x10a1c4);
 110         data1   = nv_rd32(ppwr, 0x10a1c4);
 111         nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f);
 112
 113         /* release data segment access */
 114         nv_wr32(ppwr, 0x10a580, 0x00000000);
 115
 116         /* wake process if it's waiting on a synchronous reply */
 117         if (ppwr->recv.process) {
 118                 if (process == ppwr->recv.process &&
 119                     message == ppwr->recv.message) {
 120                         ppwr->recv.data[0] = data0;
 121                         ppwr->recv.data[1] = data1;
 122                         ppwr->recv.process = 0;
 123                         wake_up(&ppwr->recv.wait);
 124                         return;
 125                 }
 126         }
 127
 128         /* right now there's no other expected responses from the engine,
 129          * so assume that any unexpected message is an error.
 130          */
 131         nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n",
 132                 (char)((process & 0x000000ff) >>  0),
 133                 (char)((process & 0x0000ff00) >>  8),
 134                 (char)((process & 0x00ff0000) >> 16),
 135                 (char)((process & 0xff000000) >> 24),
 136                 process, message, data0, data1);
 137 }
 138
 139 static void
 140 nouveau_pwr_intr(struct nouveau_subdev *subdev)
 141 {
 142         struct nouveau_pwr *ppwr = (void *)subdev;
 143         u32 disp = nv_rd32(ppwr, 0x10a01c);
 144         u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16);
 145
 146         if (intr & 0x00000020) {
 147                 u32 stat = nv_rd32(ppwr, 0x10a16c);
 148                 if (stat & 0x80000000) {
 149                         nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n",
 150                                  stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168));
 151                         nv_wr32(ppwr, 0x10a16c, 0x00000000);
 152                         intr &= ~0x00000020;
 153                 }
 154         }
 155
 156         if (intr & 0x00000040) {
 157                 schedule_work(&ppwr->recv.work);
 158                 nv_wr32(ppwr, 0x10a004, 0x00000040);
 159                 intr &= ~0x00000040;
 160         }
 161
 162         if (intr & 0x00000080) {
 163                 nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0),
 164                                                       nv_rd32(ppwr, 0x10a7a4));
 165                 nv_wr32(ppwr, 0x10a004, 0x00000080);
 166                 intr &= ~0x00000080;
 167         }
 168
 169         if (intr) {
 170                 nv_error(ppwr, "intr 0x%08x\n", intr);
 171                 nv_wr32(ppwr, 0x10a004, intr);
 172         }
 173 }
 174
 175 int
 176 _nouveau_pwr_fini(struct nouveau_object *object, bool suspend)
 177 {
 178         struct nouveau_pwr *ppwr = (void *)object;
 179
 180         nv_wr32(ppwr, 0x10a014, 0x00000060);
 181         flush_work(&ppwr->recv.work);
 182
 183         return nouveau_subdev_fini(&ppwr->base, suspend);
 184 }
 185
 186 int
 187 _nouveau_pwr_init(struct nouveau_object *object)
 188 {
 189         const struct nvkm_pwr_impl *impl = (void *)object->oclass;
 190         struct nouveau_pwr *ppwr = (void *)object;
 191         int ret, i;
 192
 193         ret = nouveau_subdev_init(&ppwr->base);
 194         if (ret)
 195                 return ret;
 196
 197         nv_subdev(ppwr)->intr = nouveau_pwr_intr;
 198         ppwr->message = nouveau_pwr_send;
 199         ppwr->pgob = nouveau_pwr_pgob;
 200
 201         /* prevent previous ucode from running, wait for idle, reset */
 202         nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */
 203         nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000);
 204         nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000);
 205         nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000);
 206
 207         /* upload data segment */
 208         nv_wr32(ppwr, 0x10a1c0, 0x01000000);
 209         for (i = 0; i < impl->data.size / 4; i++)
 210                 nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]);
 211
 212         /* upload code segment */
 213         nv_wr32(ppwr, 0x10a180, 0x01000000);
 214         for (i = 0; i < impl->code.size / 4; i++) {
 215                 if ((i & 0x3f) == 0)
 216                         nv_wr32(ppwr, 0x10a188, i >> 6);
 217                 nv_wr32(ppwr, 0x10a184, impl->code.data[i]);
 218         }
 219
 220         /* start it running */
 221         nv_wr32(ppwr, 0x10a10c, 0x00000000);
 222         nv_wr32(ppwr, 0x10a104, 0x00000000);
 223         nv_wr32(ppwr, 0x10a100, 0x00000002);
 224
 225         /* wait for valid host->pwr ring configuration */
 226         if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000))
 227                 return -EBUSY;
 228         ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff;
 229         ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16;
 230
 231         /* wait for valid pwr->host ring configuration */
 232         if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000))
 233                 return -EBUSY;
 234         ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff;
 235         ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16;
 236
 237         nv_wr32(ppwr, 0x10a010, 0x000000e0);
 238         return 0;
 239 }
 240
 241 int
 242 nouveau_pwr_create_(struct nouveau_object *parent,
 243                     struct nouveau_object *engine,
 244                     struct nouveau_oclass *oclass, int length, void **pobject)
 245 {
 246         struct nouveau_pwr *ppwr;
 247         int ret;
 248
 249         ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR",
 250                                      "pwr", length, pobject);
 251         ppwr = *pobject;
 252         if (ret)
 253                 return ret;
 254
 255         INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv);
 256         init_waitqueue_head(&ppwr->recv.wait);
 257         return 0;
 258 }
 259
 260 int
 261 _nouveau_pwr_ctor(struct nouveau_object *parent,
 262                   struct nouveau_object *engine,
 263                   struct nouveau_oclass *oclass, void *data, u32 size,
 264                   struct nouveau_object **pobject)
 265 {
 266         struct nouveau_pwr *ppwr;
 267         int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr);
 268         *pobject = nv_object(ppwr);
 269         return ret;
 270 }