drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  *          Martin Peres
  24  */
  25
  26 #include "priv.h"
  27
  28 struct nv84_therm_priv {
  29         struct nouveau_therm_priv base;
  30 };
  31
  32 int
  33 nv84_temp_get(struct nouveau_therm *therm)
  34 {
  35         return nv_rd32(therm, 0x20400);
  36 }
  37
  38 static void
  39 nv84_therm_program_alarms(struct nouveau_therm *therm)
  40 {
  41         struct nouveau_therm_priv *priv = (void *)therm;
  42         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
  43         unsigned long flags;
  44
  45         spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
  46
  47         /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */
  48         nv_wr32(therm, 0x20000, 0x000003ff);
  49
  50         /* shutdown: The computer should be shutdown when reached */
  51         nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis);
  52         nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp);
  53
  54         /* THRS_1 : fan boost*/
  55         nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp);
  56
  57         /* THRS_2 : critical */
  58         nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp);
  59
  60         /* THRS_4 : down clock */
  61         nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp);
  62         spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
  63
  64         nv_debug(therm,
  65                  "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n",
  66                  sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis,
  67                  sensor->thrs_down_clock.temp,
  68                  sensor->thrs_down_clock.hysteresis,
  69                  sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis,
  70                  sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis);
  71
  72 }
  73
  74 /* must be called with alarm_program_lock taken ! */
  75 static void
  76 nv84_therm_threshold_hyst_emulation(struct nouveau_therm *therm,
  77                                    uint32_t thrs_reg, u8 status_bit,
  78                                    const struct nvbios_therm_threshold *thrs,
  79                                    enum nouveau_therm_thrs thrs_name)
  80 {
  81         enum nouveau_therm_thrs_direction direction;
  82         enum nouveau_therm_thrs_state prev_state, new_state;
  83         int temp, cur;
  84
  85         prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name);
  86         temp = nv_rd32(therm, thrs_reg);
  87
  88         /* program the next threshold */
  89         if (temp == thrs->temp) {
  90                 nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis);
  91                 new_state = NOUVEAU_THERM_THRS_HIGHER;
  92         } else {
  93                 nv_wr32(therm, thrs_reg, thrs->temp);
  94                 new_state = NOUVEAU_THERM_THRS_LOWER;
  95         }
  96
  97         /* fix the state (in case someone reprogrammed the alarms) */
  98         cur = therm->temp_get(therm);
  99         if (new_state == NOUVEAU_THERM_THRS_LOWER && cur > thrs->temp)
 100                 new_state = NOUVEAU_THERM_THRS_HIGHER;
 101         else if (new_state == NOUVEAU_THERM_THRS_HIGHER &&
 102                 cur < thrs->temp - thrs->hysteresis)
 103                 new_state = NOUVEAU_THERM_THRS_LOWER;
 104         nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state);
 105
 106         /* find the direction */
 107         if (prev_state < new_state)
 108                 direction = NOUVEAU_THERM_THRS_RISING;
 109         else if (prev_state > new_state)
 110                 direction = NOUVEAU_THERM_THRS_FALLING;
 111         else
 112                 return;
 113
 114         /* advertise a change in direction */
 115         nouveau_therm_sensor_event(therm, thrs_name, direction);
 116 }
 117
 118 static void
 119 nv84_therm_intr(struct nouveau_subdev *subdev)
 120 {
 121         struct nouveau_therm *therm = nouveau_therm(subdev);
 122         struct nouveau_therm_priv *priv = (void *)therm;
 123         struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
 124         unsigned long flags;
 125         uint32_t intr;
 126
 127         spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags);
 128
 129         intr = nv_rd32(therm, 0x20100) & 0x3ff;
 130
 131         /* THRS_4: downclock */
 132         if (intr & 0x002) {
 133                 nv84_therm_threshold_hyst_emulation(therm, 0x20414, 24,
 134                                                   &sensor->thrs_down_clock,
 135                                                   NOUVEAU_THERM_THRS_DOWNCLOCK);
 136                 intr &= ~0x002;
 137         }
 138
 139         /* shutdown */
 140         if (intr & 0x004) {
 141                 nv84_therm_threshold_hyst_emulation(therm, 0x20480, 20,
 142                                                    &sensor->thrs_shutdown,
 143                                                    NOUVEAU_THERM_THRS_SHUTDOWN);
 144                 intr &= ~0x004;
 145         }
 146
 147         /* THRS_1 : fan boost */
 148         if (intr & 0x008) {
 149                 nv84_therm_threshold_hyst_emulation(therm, 0x204c4, 21,
 150                                                    &sensor->thrs_fan_boost,
 151                                                    NOUVEAU_THERM_THRS_FANBOOST);
 152                 intr &= ~0x008;
 153         }
 154
 155         /* THRS_2 : critical */
 156         if (intr & 0x010) {
 157                 nv84_therm_threshold_hyst_emulation(therm, 0x204c0, 22,
 158                                                    &sensor->thrs_critical,
 159                                                    NOUVEAU_THERM_THRS_CRITICAL);
 160                 intr &= ~0x010;
 161         }
 162
 163         if (intr)
 164                 nv_error(therm, "unhandled intr 0x%08x\n", intr);
 165
 166         /* ACK everything */
 167         nv_wr32(therm, 0x20100, 0xffffffff);
 168         nv_wr32(therm, 0x1100, 0x10000); /* PBUS */
 169
 170         spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags);
 171 }
 172
 173 static int
 174 nv84_therm_ctor(struct nouveau_object *parent,
 175                 struct nouveau_object *engine,
 176                 struct nouveau_oclass *oclass, void *data, u32 size,
 177                 struct nouveau_object **pobject)
 178 {
 179         struct nv84_therm_priv *priv;
 180         int ret;
 181
 182         ret = nouveau_therm_create(parent, engine, oclass, &priv);
 183         *pobject = nv_object(priv);
 184         if (ret)
 185                 return ret;
 186
 187         priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl;
 188         priv->base.base.pwm_get = nv50_fan_pwm_get;
 189         priv->base.base.pwm_set = nv50_fan_pwm_set;
 190         priv->base.base.pwm_clock = nv50_fan_pwm_clock;
 191         priv->base.base.temp_get = nv84_temp_get;
 192         priv->base.sensor.program_alarms = nv84_therm_program_alarms;
 193         nv_subdev(priv)->intr = nv84_therm_intr;
 194
 195         /* init the thresholds */
 196         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 197                                                  NOUVEAU_THERM_THRS_SHUTDOWN,
 198                                                  NOUVEAU_THERM_THRS_LOWER);
 199         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 200                                                  NOUVEAU_THERM_THRS_FANBOOST,
 201                                                  NOUVEAU_THERM_THRS_LOWER);
 202         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 203                                                  NOUVEAU_THERM_THRS_CRITICAL,
 204                                                  NOUVEAU_THERM_THRS_LOWER);
 205         nouveau_therm_sensor_set_threshold_state(&priv->base.base,
 206                                                  NOUVEAU_THERM_THRS_DOWNCLOCK,
 207                                                  NOUVEAU_THERM_THRS_LOWER);
 208
 209         return nouveau_therm_preinit(&priv->base.base);
 210 }
 211
 212 int
 213 nv84_therm_fini(struct nouveau_object *object, bool suspend)
 214 {
 215         /* Disable PTherm IRQs */
 216         nv_wr32(object, 0x20000, 0x00000000);
 217
 218         /* ACK all PTherm IRQs */
 219         nv_wr32(object, 0x20100, 0xffffffff);
 220         nv_wr32(object, 0x1100, 0x10000); /* PBUS */
 221
 222         return _nouveau_therm_fini(object, suspend);
 223 }
 224
 225 struct nouveau_oclass
 226 nv84_therm_oclass = {
 227         .handle = NV_SUBDEV(THERM, 0x84),
 228         .ofuncs = &(struct nouveau_ofuncs) {
 229                 .ctor = nv84_therm_ctor,
 230                 .dtor = _nouveau_therm_dtor,
 231                 .init = _nouveau_therm_init,
 232                 .fini = nv84_therm_fini,
 233         },
 234 };