2 * Copyright 2005-2006 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_drm.h"
29 #include "nouveau_dma.h"
32 nouveau_channel_pushbuf_ctxdma_init(struct nouveau_channel *chan)
34 struct drm_device *dev = chan->dev;
35 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 struct nouveau_bo *pb = chan->pushbuf_bo;
37 struct nouveau_gpuobj *pushbuf = NULL;
40 if (dev_priv->card_type >= NV_50) {
41 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
42 dev_priv->vm_end, NV_DMA_ACCESS_RO,
43 NV_DMA_TARGET_AGP, &pushbuf);
44 chan->pushbuf_base = pb->bo.offset;
46 if (pb->bo.mem.mem_type == TTM_PL_TT) {
47 ret = nouveau_gpuobj_gart_dma_new(chan, 0,
48 dev_priv->gart_info.aper_size,
49 NV_DMA_ACCESS_RO, &pushbuf,
51 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
53 if (dev_priv->card_type != NV_04) {
54 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, 0,
55 dev_priv->fb_available_size,
57 NV_DMA_TARGET_VIDMEM, &pushbuf);
58 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
60 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
61 * exact reason for existing :) PCI access to cmdbuf in
64 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
65 pci_resource_start(dev->pdev,
67 dev_priv->fb_available_size,
69 NV_DMA_TARGET_PCI, &pushbuf);
70 chan->pushbuf_base = pb->bo.mem.start << PAGE_SHIFT;
73 nouveau_gpuobj_ref(pushbuf, &chan->pushbuf);
74 nouveau_gpuobj_ref(NULL, &pushbuf);
78 static struct nouveau_bo *
79 nouveau_channel_user_pushbuf_alloc(struct drm_device *dev)
81 struct nouveau_bo *pushbuf = NULL;
84 if (nouveau_vram_pushbuf)
85 location = TTM_PL_FLAG_VRAM;
87 location = TTM_PL_FLAG_TT;
89 ret = nouveau_bo_new(dev, NULL, 65536, 0, location, 0, 0x0000, false,
92 NV_ERROR(dev, "error allocating DMA push buffer: %d\n", ret);
96 ret = nouveau_bo_pin(pushbuf, location);
98 NV_ERROR(dev, "error pinning DMA push buffer: %d\n", ret);
99 nouveau_bo_ref(NULL, &pushbuf);
106 /* allocates and initializes a fifo for user space consumption */
108 nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret,
109 struct drm_file *file_priv,
110 uint32_t vram_handle, uint32_t gart_handle)
112 struct drm_nouveau_private *dev_priv = dev->dev_private;
113 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
114 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
115 struct nouveau_channel *chan;
119 /* allocate and lock channel structure */
120 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
124 chan->file_priv = file_priv;
125 chan->vram_handle = vram_handle;
126 chan->gart_handle = gart_handle;
128 atomic_set(&chan->refcount, 1);
129 mutex_init(&chan->mutex);
130 mutex_lock(&chan->mutex);
132 /* allocate hw channel id */
133 spin_lock_irqsave(&dev_priv->channels.lock, flags);
134 for (chan->id = 0; chan->id < pfifo->channels; chan->id++) {
135 if (!dev_priv->channels.ptr[chan->id]) {
136 dev_priv->channels.ptr[chan->id] = chan;
140 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
142 if (chan->id == pfifo->channels) {
143 mutex_unlock(&chan->mutex);
148 NV_DEBUG(dev, "initialising channel %d\n", chan->id);
149 INIT_LIST_HEAD(&chan->nvsw.vbl_wait);
150 INIT_LIST_HEAD(&chan->fence.pending);
152 /* Allocate DMA push buffer */
153 chan->pushbuf_bo = nouveau_channel_user_pushbuf_alloc(dev);
154 if (!chan->pushbuf_bo) {
156 NV_ERROR(dev, "pushbuf %d\n", ret);
157 nouveau_channel_put(&chan);
161 nouveau_dma_pre_init(chan);
163 /* Locate channel's user control regs */
164 if (dev_priv->card_type < NV_40)
165 user = NV03_USER(chan->id);
167 if (dev_priv->card_type < NV_50)
168 user = NV40_USER(chan->id);
170 user = NV50_USER(chan->id);
172 chan->user = ioremap(pci_resource_start(dev->pdev, 0) + user,
175 NV_ERROR(dev, "ioremap of regs failed.\n");
176 nouveau_channel_put(&chan);
179 chan->user_put = 0x40;
180 chan->user_get = 0x44;
182 /* Allocate space for per-channel fixed notifier memory */
183 ret = nouveau_notifier_init_channel(chan);
185 NV_ERROR(dev, "ntfy %d\n", ret);
186 nouveau_channel_put(&chan);
190 /* Setup channel's default objects */
191 ret = nouveau_gpuobj_channel_init(chan, vram_handle, gart_handle);
193 NV_ERROR(dev, "gpuobj %d\n", ret);
194 nouveau_channel_put(&chan);
198 /* Create a dma object for the push buffer */
199 ret = nouveau_channel_pushbuf_ctxdma_init(chan);
201 NV_ERROR(dev, "pbctxdma %d\n", ret);
202 nouveau_channel_put(&chan);
206 /* disable the fifo caches */
207 pfifo->reassign(dev, false);
209 /* Create a graphics context for new channel */
210 ret = pgraph->create_context(chan);
212 nouveau_channel_put(&chan);
216 /* Construct inital RAMFC for new channel */
217 ret = pfifo->create_context(chan);
219 nouveau_channel_put(&chan);
223 pfifo->reassign(dev, true);
225 ret = nouveau_dma_init(chan);
227 ret = nouveau_fence_channel_init(chan);
229 nouveau_channel_put(&chan);
233 nouveau_debugfs_channel_init(chan);
235 NV_DEBUG(dev, "channel %d initialised\n", chan->id);
240 struct nouveau_channel *
241 nouveau_channel_get(struct drm_device *dev, struct drm_file *file_priv, int id)
243 struct drm_nouveau_private *dev_priv = dev->dev_private;
244 struct nouveau_channel *chan = ERR_PTR(-ENODEV);
247 spin_lock_irqsave(&dev_priv->channels.lock, flags);
248 chan = dev_priv->channels.ptr[id];
250 if (unlikely(!chan || atomic_read(&chan->refcount) == 0)) {
251 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
252 return ERR_PTR(-EINVAL);
255 if (unlikely(file_priv && chan->file_priv != file_priv)) {
256 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
257 return ERR_PTR(-EINVAL);
260 atomic_inc(&chan->refcount);
261 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
263 mutex_lock(&chan->mutex);
268 nouveau_channel_put(struct nouveau_channel **pchan)
270 struct nouveau_channel *chan = *pchan;
271 struct drm_device *dev = chan->dev;
272 struct drm_nouveau_private *dev_priv = dev->dev_private;
273 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
274 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
278 /* unlock the channel */
279 mutex_unlock(&chan->mutex);
281 /* decrement the refcount, and we're done if there's still refs */
282 if (likely(!atomic_dec_and_test(&chan->refcount))) {
287 /* noone wants the channel anymore */
288 NV_DEBUG(dev, "freeing channel %d\n", chan->id);
289 nouveau_debugfs_channel_fini(chan);
292 /* give it chance to idle */
293 nouveau_fence_update(chan);
294 if (chan->fence.sequence != chan->fence.sequence_ack) {
295 struct nouveau_fence *fence = NULL;
297 ret = nouveau_fence_new(chan, &fence, true);
299 ret = nouveau_fence_wait(fence, NULL, false, false);
300 nouveau_fence_unref((void *)&fence);
304 NV_ERROR(dev, "Failed to idle channel %d.\n", chan->id);
307 /* ensure all outstanding fences are signaled. they should be if the
308 * above attempts at idling were OK, but if we failed this'll tell TTM
309 * we're done with the buffers.
311 nouveau_fence_channel_fini(chan);
313 /* boot it off the hardware */
314 pfifo->reassign(dev, false);
316 /* We want to give pgraph a chance to idle and get rid of all
317 * potential errors. We need to do this without the context
318 * switch lock held, otherwise the irq handler is unable to
321 if (pgraph->channel(dev) == chan)
322 nouveau_wait_for_idle(dev);
324 /* destroy the engine specific contexts */
325 pfifo->destroy_context(chan);
326 pgraph->destroy_context(chan);
328 pfifo->reassign(dev, true);
330 /* aside from its resources, the channel should now be dead,
331 * remove it from the channel list
333 spin_lock_irqsave(&dev_priv->channels.lock, flags);
334 dev_priv->channels.ptr[chan->id] = NULL;
335 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
337 /* destroy any resources the channel owned */
338 nouveau_gpuobj_ref(NULL, &chan->pushbuf);
339 if (chan->pushbuf_bo) {
340 nouveau_bo_unmap(chan->pushbuf_bo);
341 nouveau_bo_unpin(chan->pushbuf_bo);
342 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
344 nouveau_gpuobj_channel_takedown(chan);
345 nouveau_notifier_takedown_channel(chan);
352 /* cleans up all the fifos from file_priv */
354 nouveau_channel_cleanup(struct drm_device *dev, struct drm_file *file_priv)
356 struct drm_nouveau_private *dev_priv = dev->dev_private;
357 struct nouveau_engine *engine = &dev_priv->engine;
358 struct nouveau_channel *chan;
361 NV_DEBUG(dev, "clearing FIFO enables from file_priv\n");
362 for (i = 0; i < engine->fifo.channels; i++) {
363 chan = nouveau_channel_get(dev, file_priv, i);
367 atomic_dec(&chan->refcount);
368 nouveau_channel_put(&chan);
373 /***********************************
374 * ioctls wrapping the functions
375 ***********************************/
378 nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data,
379 struct drm_file *file_priv)
381 struct drm_nouveau_private *dev_priv = dev->dev_private;
382 struct drm_nouveau_channel_alloc *init = data;
383 struct nouveau_channel *chan;
386 if (dev_priv->engine.graph.accel_blocked)
389 if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
392 ret = nouveau_channel_alloc(dev, &chan, file_priv,
393 init->fb_ctxdma_handle,
394 init->tt_ctxdma_handle);
397 init->channel = chan->id;
399 if (chan->dma.ib_max)
400 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM |
401 NOUVEAU_GEM_DOMAIN_GART;
402 else if (chan->pushbuf_bo->bo.mem.mem_type == TTM_PL_VRAM)
403 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM;
405 init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART;
407 init->subchan[0].handle = NvM2MF;
408 if (dev_priv->card_type < NV_50)
409 init->subchan[0].grclass = 0x0039;
411 init->subchan[0].grclass = 0x5039;
412 init->subchan[1].handle = NvSw;
413 init->subchan[1].grclass = NV_SW;
414 init->nr_subchan = 2;
416 /* Named memory object area */
417 ret = drm_gem_handle_create(file_priv, chan->notifier_bo->gem,
418 &init->notifier_handle);
421 atomic_inc(&chan->refcount); /* userspace reference */
422 nouveau_channel_put(&chan);
427 nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
428 struct drm_file *file_priv)
430 struct drm_nouveau_channel_free *req = data;
431 struct nouveau_channel *chan;
433 chan = nouveau_channel_get(dev, file_priv, req->channel);
435 return PTR_ERR(chan);
437 atomic_dec(&chan->refcount);
438 nouveau_channel_put(&chan);
442 /***********************************
443 * finally, the ioctl table
444 ***********************************/
446 struct drm_ioctl_desc nouveau_ioctls[] = {
447 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH),
448 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
449 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_UNLOCKED|DRM_AUTH),
450 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_UNLOCKED|DRM_AUTH),
451 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH),
452 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_UNLOCKED|DRM_AUTH),
453 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH),
454 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH),
455 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH),
456 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH),
457 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH),
458 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH),
461 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);