2 * Copyright 2009 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drv.h"
28 #include "nouveau_i2c.h"
29 #include "nouveau_connector.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_crtc.h"
33 /******************************************************************************
34 * aux channel util functions
35 *****************************************************************************/
36 #define AUX_DBG(fmt, args...) do { \
37 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \
38 NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \
41 #define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
44 auxch_fini(struct drm_device *dev, int ch)
46 nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
50 auxch_init(struct drm_device *dev, int ch)
52 const u32 unksel = 1; /* nfi which to use, or if it matters.. */
53 const u32 ureq = unksel ? 0x00100000 : 0x00200000;
54 const u32 urep = unksel ? 0x01000000 : 0x02000000;
57 /* wait up to 1ms for any previous transaction to be done... */
60 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
63 AUX_ERR("begin idle timeout 0x%08x", ctrl);
66 } while (ctrl & 0x03010000);
68 /* set some magic, and wait up to 1ms for it to appear */
69 nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
72 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
75 AUX_ERR("magic wait 0x%08x\n", ctrl);
79 } while ((ctrl & 0x03000000) != urep);
85 auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
87 u32 ctrl, stat, timeout, retries;
91 AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
93 ret = auxch_init(dev, ch);
97 stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
98 if (!(stat & 0x10000000)) {
99 AUX_DBG("sink not detected\n");
105 memcpy(xbuf, data, size);
106 for (i = 0; i < 16; i += 4) {
107 AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
108 nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
112 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
116 nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
118 /* retry transaction a number of times on failure... */
120 for (retries = 0; retries < 32; retries++) {
121 /* reset, and delay a while if this is a retry */
122 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
123 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
127 /* transaction request, wait up to 1ms for it to complete */
128 nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);
132 ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
135 AUX_ERR("tx req timeout 0x%08x\n", ctrl);
138 } while (ctrl & 0x00010000);
140 /* read status, and check if transaction completed ok */
141 stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
142 if (!(stat & 0x000f0f00)) {
147 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
151 for (i = 0; i < 16; i += 4) {
152 xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
153 AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
155 memcpy(data, xbuf, size);
164 dp_link_bw_get(struct drm_device *dev, int or, int link)
166 u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
167 if (!(ctrl & 0x000c0000))
173 dp_lane_count_get(struct drm_device *dev, int or, int link)
175 u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
176 switch (ctrl & 0x000f0000) {
177 case 0x00010000: return 1;
178 case 0x00030000: return 2;
185 nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
187 const u32 symbol = 100000;
188 int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
189 int TU, VTUi, VTUf, VTUa;
190 u64 link_data_rate, link_ratio, unk;
191 u32 best_diff = 64 * symbol;
192 u32 link_nr, link_bw, r;
194 /* calculate packed data rate for each lane */
195 link_nr = dp_lane_count_get(dev, or, link);
196 link_data_rate = (clk * bpp / 8) / link_nr;
198 /* calculate ratio of packed data rate to link symbol rate */
199 link_bw = dp_link_bw_get(dev, or, link);
200 link_ratio = link_data_rate * symbol;
201 r = do_div(link_ratio, link_bw);
203 for (TU = 64; TU >= 32; TU--) {
204 /* calculate average number of valid symbols in each TU */
205 u32 tu_valid = link_ratio * TU;
208 /* find a hw representation for the fraction.. */
209 VTUi = tu_valid / symbol;
210 calc = VTUi * symbol;
211 diff = tu_valid - calc;
213 if (diff >= (symbol / 2)) {
214 VTUf = symbol / (symbol - diff);
215 if (symbol - (VTUf * diff))
220 calc += symbol - (symbol / VTUf);
228 VTUf = min((int)(symbol / diff), 15);
229 calc += symbol / VTUf;
232 diff = calc - tu_valid;
234 /* no remainder, but the hw doesn't like the fractional
235 * part to be zero. decrement the integer part and
236 * have the fraction add a whole symbol back
243 if (diff < best_diff) {
255 NV_ERROR(dev, "DP: unable to find suitable config\n");
259 /* XXX close to vbios numbers, but not right */
260 unk = (symbol - link_ratio) * bestTU;
262 r = do_div(unk, symbol);
263 r = do_div(unk, symbol);
266 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
267 nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
273 /******************************************************************************
275 *****************************************************************************/
277 struct dcb_entry *dcb;
290 dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
292 struct drm_nouveau_private *dev_priv = dev->dev_private;
293 int or = dp->or, link = dp->link;
294 u8 *bios, headerlen, sink[2];
297 NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
299 /* set selected link rate on source */
300 switch (dp->link_bw) {
302 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
303 sink[0] = DP_LINK_BW_2_7;
306 nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
307 sink[0] = DP_LINK_BW_1_62;
311 /* offset +0x0a of each dp encoder table entry is a pointer to another
312 * table, that has (among other things) pointers to more scripts that
313 * need to be executed, this time depending on link speed.
315 bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
316 if (bios && (bios = ROMPTR(&dev_priv->vbios, bios[10]))) {
317 while (dp->link_bw < (ROM16(bios[0]) * 10))
320 nouveau_bios_run_init_table(dev, ROM16(bios[2]), dp->dcb, dp->crtc);
323 /* configure lane count on the source */
324 dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
325 sink[1] = dp->link_nr;
326 if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) {
327 dp_ctrl |= 0x00004000;
328 sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
331 nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
333 /* inform the sink of the new configuration */
334 auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
338 dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
340 NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
341 nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
342 auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &tp, 1);
346 dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
348 u32 mask = 0, drv = 0, pre = 0, unk = 0;
349 u8 shifts[4] = { 16, 8, 0, 24 };
350 u8 *bios, *last, headerlen;
355 bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
356 last = bios + headerlen + (bios[4] * 5);
357 for (i = 0; i < dp->link_nr; i++) {
358 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
359 u8 *conf = bios + headerlen;
361 while (conf < last) {
362 if ((lane & 3) == conf[0] &&
363 (lane >> 2) == conf[1])
371 dp->conf[i] = (conf[1] << 3) | conf[0];
372 if (conf[0] == DP_TRAIN_VOLTAGE_SWING_1200)
373 dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
374 if (conf[1] == DP_TRAIN_PRE_EMPHASIS_9_5)
375 dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
377 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
379 mask |= 0xff << shifts[i];
380 drv |= conf[2] << shifts[i];
381 pre |= conf[3] << shifts[i];
382 unk = (unk & ~0x0000ff00) | (conf[4] << 8);
383 unk |= 1 << (shifts[i] >> 3);
386 nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
387 nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
388 nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
390 return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
394 dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
400 ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
404 NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
405 dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
406 dp->stat[4], dp->stat[5]);
411 dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
413 bool cr_done = false, abort = false;
414 int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
417 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
420 if (dp_link_train_commit(dev, dp) ||
421 dp_link_train_update(dev, dp, 100))
425 for (i = 0; i < dp->link_nr; i++) {
426 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
427 if (!(lane & DP_LANE_CR_DONE)) {
429 if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
435 if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
436 voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
439 } while (!cr_done && !abort && ++tries < 5);
441 return cr_done ? 0 : -1;
445 dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
447 bool eq_done, cr_done = true;
450 dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
453 if (dp_link_train_update(dev, dp, 400))
456 eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
457 for (i = 0; i < dp->link_nr && eq_done; i++) {
458 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
459 if (!(lane & DP_LANE_CR_DONE))
461 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
462 !(lane & DP_LANE_SYMBOL_LOCKED))
466 if (dp_link_train_commit(dev, dp))
468 } while (!eq_done && cr_done && ++tries <= 5);
470 return eq_done ? 0 : -1;
474 nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
476 struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
477 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
478 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
479 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
480 struct nouveau_connector *nv_connector =
481 nouveau_encoder_connector_get(nv_encoder);
482 struct drm_device *dev = encoder->dev;
483 struct nouveau_i2c_chan *auxch;
484 const u32 bw_list[] = { 270000, 162000, 0 };
485 const u32 *link_bw = bw_list;
489 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
493 bios = nouveau_bios_dp_table(dev, nv_encoder->dcb, &headerlen);
497 dp.dcb = nv_encoder->dcb;
498 dp.crtc = nv_crtc->index;
499 dp.auxch = auxch->rd;
500 dp.or = nv_encoder->or;
501 dp.link = !(nv_encoder->dcb->sorconf.link & 1);
502 dp.dpcd = nv_encoder->dp.dpcd;
504 /* some sinks toggle hotplug in response to some of the actions
505 * we take during link training (DP_SET_POWER is one), we need
506 * to ignore them for the moment to avoid races.
508 pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
510 /* enable down-spreading, if possible */
511 if (headerlen >= 16) {
512 u16 script = ROM16(bios[14]);
513 if (nv_encoder->dp.dpcd[3] & 1)
514 script = ROM16(bios[12]);
516 nouveau_bios_run_init_table(dev, script, dp.dcb, dp.crtc);
519 /* execute pre-train script from vbios */
520 nouveau_bios_run_init_table(dev, ROM16(bios[6]), dp.dcb, dp.crtc);
522 /* start off at highest link rate supported by encoder and display */
523 while (*link_bw > nv_encoder->dp.link_bw)
527 /* find minimum required lane count at this link rate */
528 dp.link_nr = nv_encoder->dp.link_nr;
529 while ((dp.link_nr >> 1) * link_bw[0] > datarate)
532 /* drop link rate to minimum with this lane count */
533 while ((link_bw[1] * dp.link_nr) > datarate)
535 dp.link_bw = link_bw[0];
537 /* program selected link configuration */
538 dp_set_link_config(dev, &dp);
540 /* attempt to train the link at this configuration */
541 memset(dp.stat, 0x00, sizeof(dp.stat));
542 if (!dp_link_train_cr(dev, &dp) &&
543 !dp_link_train_eq(dev, &dp))
546 /* retry at lower rate */
550 /* finish link training */
551 dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
553 /* execute post-train script from vbios */
554 nouveau_bios_run_init_table(dev, ROM16(bios[8]), dp.dcb, dp.crtc);
556 /* re-enable hotplug detect */
557 pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
562 nouveau_dp_detect(struct drm_encoder *encoder)
564 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
565 struct drm_device *dev = encoder->dev;
566 struct nouveau_i2c_chan *auxch;
567 u8 *dpcd = nv_encoder->dp.dpcd;
570 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
574 ret = auxch_tx(dev, auxch->rd, 9, DP_DPCD_REV, dpcd, 8);
578 nv_encoder->dp.link_bw = 27000 * dpcd[1];
579 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
581 NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
582 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
583 NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
584 nv_encoder->dcb->dpconf.link_nr,
585 nv_encoder->dcb->dpconf.link_bw);
587 if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
588 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
589 if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
590 nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
592 NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
593 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
599 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
600 uint8_t *data, int data_nr)
602 return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
606 nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
608 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
609 struct i2c_msg *msg = msgs;
613 u8 remaining = msg->len;
617 u8 cnt = (remaining > 16) ? 16 : remaining;
620 if (msg->flags & I2C_M_RD)
625 if (mcnt || remaining > 16)
628 ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
643 nouveau_dp_i2c_func(struct i2c_adapter *adap)
645 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
648 const struct i2c_algorithm nouveau_dp_i2c_algo = {
649 .master_xfer = nouveau_dp_i2c_xfer,
650 .functionality = nouveau_dp_i2c_func