2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 #include <linux/swab.h>
27 #include <linux/slab.h>
30 #include "drm_sarea.h"
31 #include "drm_crtc_helper.h"
32 #include <linux/vgaarb.h>
33 #include <linux/vga_switcheroo.h>
35 #include "nouveau_drv.h"
36 #include "nouveau_drm.h"
37 #include "nouveau_fbcon.h"
38 #include "nouveau_ramht.h"
39 #include "nouveau_pm.h"
40 #include "nv50_display.h"
42 static void nouveau_stub_takedown(struct drm_device *dev) {}
43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
50 switch (dev_priv->chipset & 0xf0) {
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
56 engine->instmem.get = nv04_instmem_get;
57 engine->instmem.put = nv04_instmem_put;
58 engine->instmem.map = nv04_instmem_map;
59 engine->instmem.unmap = nv04_instmem_unmap;
60 engine->instmem.flush = nv04_instmem_flush;
61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
68 engine->fifo.channels = 16;
69 engine->fifo.init = nv04_fifo_init;
70 engine->fifo.takedown = nv04_fifo_fini;
71 engine->fifo.disable = nv04_fifo_disable;
72 engine->fifo.enable = nv04_fifo_enable;
73 engine->fifo.reassign = nv04_fifo_reassign;
74 engine->fifo.cache_pull = nv04_fifo_cache_pull;
75 engine->fifo.channel_id = nv04_fifo_channel_id;
76 engine->fifo.create_context = nv04_fifo_create_context;
77 engine->fifo.destroy_context = nv04_fifo_destroy_context;
78 engine->fifo.load_context = nv04_fifo_load_context;
79 engine->fifo.unload_context = nv04_fifo_unload_context;
80 engine->display.early_init = nv04_display_early_init;
81 engine->display.late_takedown = nv04_display_late_takedown;
82 engine->display.create = nv04_display_create;
83 engine->display.init = nv04_display_init;
84 engine->display.destroy = nv04_display_destroy;
85 engine->gpio.init = nouveau_stub_init;
86 engine->gpio.takedown = nouveau_stub_takedown;
87 engine->gpio.get = NULL;
88 engine->gpio.set = NULL;
89 engine->gpio.irq_enable = NULL;
90 engine->pm.clock_get = nv04_pm_clock_get;
91 engine->pm.clock_pre = nv04_pm_clock_pre;
92 engine->pm.clock_set = nv04_pm_clock_set;
93 engine->vram.init = nouveau_mem_detect;
94 engine->vram.takedown = nouveau_stub_takedown;
95 engine->vram.flags_valid = nouveau_mem_flags_valid;
98 engine->instmem.init = nv04_instmem_init;
99 engine->instmem.takedown = nv04_instmem_takedown;
100 engine->instmem.suspend = nv04_instmem_suspend;
101 engine->instmem.resume = nv04_instmem_resume;
102 engine->instmem.get = nv04_instmem_get;
103 engine->instmem.put = nv04_instmem_put;
104 engine->instmem.map = nv04_instmem_map;
105 engine->instmem.unmap = nv04_instmem_unmap;
106 engine->instmem.flush = nv04_instmem_flush;
107 engine->mc.init = nv04_mc_init;
108 engine->mc.takedown = nv04_mc_takedown;
109 engine->timer.init = nv04_timer_init;
110 engine->timer.read = nv04_timer_read;
111 engine->timer.takedown = nv04_timer_takedown;
112 engine->fb.init = nv10_fb_init;
113 engine->fb.takedown = nv10_fb_takedown;
114 engine->fb.init_tile_region = nv10_fb_init_tile_region;
115 engine->fb.set_tile_region = nv10_fb_set_tile_region;
116 engine->fb.free_tile_region = nv10_fb_free_tile_region;
117 engine->fifo.channels = 32;
118 engine->fifo.init = nv10_fifo_init;
119 engine->fifo.takedown = nv04_fifo_fini;
120 engine->fifo.disable = nv04_fifo_disable;
121 engine->fifo.enable = nv04_fifo_enable;
122 engine->fifo.reassign = nv04_fifo_reassign;
123 engine->fifo.cache_pull = nv04_fifo_cache_pull;
124 engine->fifo.channel_id = nv10_fifo_channel_id;
125 engine->fifo.create_context = nv10_fifo_create_context;
126 engine->fifo.destroy_context = nv04_fifo_destroy_context;
127 engine->fifo.load_context = nv10_fifo_load_context;
128 engine->fifo.unload_context = nv10_fifo_unload_context;
129 engine->display.early_init = nv04_display_early_init;
130 engine->display.late_takedown = nv04_display_late_takedown;
131 engine->display.create = nv04_display_create;
132 engine->display.init = nv04_display_init;
133 engine->display.destroy = nv04_display_destroy;
134 engine->gpio.init = nouveau_stub_init;
135 engine->gpio.takedown = nouveau_stub_takedown;
136 engine->gpio.get = nv10_gpio_get;
137 engine->gpio.set = nv10_gpio_set;
138 engine->gpio.irq_enable = NULL;
139 engine->pm.clock_get = nv04_pm_clock_get;
140 engine->pm.clock_pre = nv04_pm_clock_pre;
141 engine->pm.clock_set = nv04_pm_clock_set;
142 engine->vram.init = nouveau_mem_detect;
143 engine->vram.takedown = nouveau_stub_takedown;
144 engine->vram.flags_valid = nouveau_mem_flags_valid;
147 engine->instmem.init = nv04_instmem_init;
148 engine->instmem.takedown = nv04_instmem_takedown;
149 engine->instmem.suspend = nv04_instmem_suspend;
150 engine->instmem.resume = nv04_instmem_resume;
151 engine->instmem.get = nv04_instmem_get;
152 engine->instmem.put = nv04_instmem_put;
153 engine->instmem.map = nv04_instmem_map;
154 engine->instmem.unmap = nv04_instmem_unmap;
155 engine->instmem.flush = nv04_instmem_flush;
156 engine->mc.init = nv04_mc_init;
157 engine->mc.takedown = nv04_mc_takedown;
158 engine->timer.init = nv04_timer_init;
159 engine->timer.read = nv04_timer_read;
160 engine->timer.takedown = nv04_timer_takedown;
161 engine->fb.init = nv10_fb_init;
162 engine->fb.takedown = nv10_fb_takedown;
163 engine->fb.init_tile_region = nv10_fb_init_tile_region;
164 engine->fb.set_tile_region = nv10_fb_set_tile_region;
165 engine->fb.free_tile_region = nv10_fb_free_tile_region;
166 engine->fifo.channels = 32;
167 engine->fifo.init = nv10_fifo_init;
168 engine->fifo.takedown = nv04_fifo_fini;
169 engine->fifo.disable = nv04_fifo_disable;
170 engine->fifo.enable = nv04_fifo_enable;
171 engine->fifo.reassign = nv04_fifo_reassign;
172 engine->fifo.cache_pull = nv04_fifo_cache_pull;
173 engine->fifo.channel_id = nv10_fifo_channel_id;
174 engine->fifo.create_context = nv10_fifo_create_context;
175 engine->fifo.destroy_context = nv04_fifo_destroy_context;
176 engine->fifo.load_context = nv10_fifo_load_context;
177 engine->fifo.unload_context = nv10_fifo_unload_context;
178 engine->display.early_init = nv04_display_early_init;
179 engine->display.late_takedown = nv04_display_late_takedown;
180 engine->display.create = nv04_display_create;
181 engine->display.init = nv04_display_init;
182 engine->display.destroy = nv04_display_destroy;
183 engine->gpio.init = nouveau_stub_init;
184 engine->gpio.takedown = nouveau_stub_takedown;
185 engine->gpio.get = nv10_gpio_get;
186 engine->gpio.set = nv10_gpio_set;
187 engine->gpio.irq_enable = NULL;
188 engine->pm.clock_get = nv04_pm_clock_get;
189 engine->pm.clock_pre = nv04_pm_clock_pre;
190 engine->pm.clock_set = nv04_pm_clock_set;
191 engine->vram.init = nouveau_mem_detect;
192 engine->vram.takedown = nouveau_stub_takedown;
193 engine->vram.flags_valid = nouveau_mem_flags_valid;
196 engine->instmem.init = nv04_instmem_init;
197 engine->instmem.takedown = nv04_instmem_takedown;
198 engine->instmem.suspend = nv04_instmem_suspend;
199 engine->instmem.resume = nv04_instmem_resume;
200 engine->instmem.get = nv04_instmem_get;
201 engine->instmem.put = nv04_instmem_put;
202 engine->instmem.map = nv04_instmem_map;
203 engine->instmem.unmap = nv04_instmem_unmap;
204 engine->instmem.flush = nv04_instmem_flush;
205 engine->mc.init = nv04_mc_init;
206 engine->mc.takedown = nv04_mc_takedown;
207 engine->timer.init = nv04_timer_init;
208 engine->timer.read = nv04_timer_read;
209 engine->timer.takedown = nv04_timer_takedown;
210 engine->fb.init = nv30_fb_init;
211 engine->fb.takedown = nv30_fb_takedown;
212 engine->fb.init_tile_region = nv30_fb_init_tile_region;
213 engine->fb.set_tile_region = nv10_fb_set_tile_region;
214 engine->fb.free_tile_region = nv30_fb_free_tile_region;
215 engine->fifo.channels = 32;
216 engine->fifo.init = nv10_fifo_init;
217 engine->fifo.takedown = nv04_fifo_fini;
218 engine->fifo.disable = nv04_fifo_disable;
219 engine->fifo.enable = nv04_fifo_enable;
220 engine->fifo.reassign = nv04_fifo_reassign;
221 engine->fifo.cache_pull = nv04_fifo_cache_pull;
222 engine->fifo.channel_id = nv10_fifo_channel_id;
223 engine->fifo.create_context = nv10_fifo_create_context;
224 engine->fifo.destroy_context = nv04_fifo_destroy_context;
225 engine->fifo.load_context = nv10_fifo_load_context;
226 engine->fifo.unload_context = nv10_fifo_unload_context;
227 engine->display.early_init = nv04_display_early_init;
228 engine->display.late_takedown = nv04_display_late_takedown;
229 engine->display.create = nv04_display_create;
230 engine->display.init = nv04_display_init;
231 engine->display.destroy = nv04_display_destroy;
232 engine->gpio.init = nouveau_stub_init;
233 engine->gpio.takedown = nouveau_stub_takedown;
234 engine->gpio.get = nv10_gpio_get;
235 engine->gpio.set = nv10_gpio_set;
236 engine->gpio.irq_enable = NULL;
237 engine->pm.clock_get = nv04_pm_clock_get;
238 engine->pm.clock_pre = nv04_pm_clock_pre;
239 engine->pm.clock_set = nv04_pm_clock_set;
240 engine->pm.voltage_get = nouveau_voltage_gpio_get;
241 engine->pm.voltage_set = nouveau_voltage_gpio_set;
242 engine->vram.init = nouveau_mem_detect;
243 engine->vram.takedown = nouveau_stub_takedown;
244 engine->vram.flags_valid = nouveau_mem_flags_valid;
248 engine->instmem.init = nv04_instmem_init;
249 engine->instmem.takedown = nv04_instmem_takedown;
250 engine->instmem.suspend = nv04_instmem_suspend;
251 engine->instmem.resume = nv04_instmem_resume;
252 engine->instmem.get = nv04_instmem_get;
253 engine->instmem.put = nv04_instmem_put;
254 engine->instmem.map = nv04_instmem_map;
255 engine->instmem.unmap = nv04_instmem_unmap;
256 engine->instmem.flush = nv04_instmem_flush;
257 engine->mc.init = nv40_mc_init;
258 engine->mc.takedown = nv40_mc_takedown;
259 engine->timer.init = nv04_timer_init;
260 engine->timer.read = nv04_timer_read;
261 engine->timer.takedown = nv04_timer_takedown;
262 engine->fb.init = nv40_fb_init;
263 engine->fb.takedown = nv40_fb_takedown;
264 engine->fb.init_tile_region = nv30_fb_init_tile_region;
265 engine->fb.set_tile_region = nv40_fb_set_tile_region;
266 engine->fb.free_tile_region = nv30_fb_free_tile_region;
267 engine->fifo.channels = 32;
268 engine->fifo.init = nv40_fifo_init;
269 engine->fifo.takedown = nv04_fifo_fini;
270 engine->fifo.disable = nv04_fifo_disable;
271 engine->fifo.enable = nv04_fifo_enable;
272 engine->fifo.reassign = nv04_fifo_reassign;
273 engine->fifo.cache_pull = nv04_fifo_cache_pull;
274 engine->fifo.channel_id = nv10_fifo_channel_id;
275 engine->fifo.create_context = nv40_fifo_create_context;
276 engine->fifo.destroy_context = nv04_fifo_destroy_context;
277 engine->fifo.load_context = nv40_fifo_load_context;
278 engine->fifo.unload_context = nv40_fifo_unload_context;
279 engine->display.early_init = nv04_display_early_init;
280 engine->display.late_takedown = nv04_display_late_takedown;
281 engine->display.create = nv04_display_create;
282 engine->display.init = nv04_display_init;
283 engine->display.destroy = nv04_display_destroy;
284 engine->gpio.init = nouveau_stub_init;
285 engine->gpio.takedown = nouveau_stub_takedown;
286 engine->gpio.get = nv10_gpio_get;
287 engine->gpio.set = nv10_gpio_set;
288 engine->gpio.irq_enable = NULL;
289 engine->pm.clock_get = nv04_pm_clock_get;
290 engine->pm.clock_pre = nv04_pm_clock_pre;
291 engine->pm.clock_set = nv04_pm_clock_set;
292 engine->pm.voltage_get = nouveau_voltage_gpio_get;
293 engine->pm.voltage_set = nouveau_voltage_gpio_set;
294 engine->pm.temp_get = nv40_temp_get;
295 engine->vram.init = nouveau_mem_detect;
296 engine->vram.takedown = nouveau_stub_takedown;
297 engine->vram.flags_valid = nouveau_mem_flags_valid;
300 case 0x80: /* gotta love NVIDIA's consistency.. */
303 engine->instmem.init = nv50_instmem_init;
304 engine->instmem.takedown = nv50_instmem_takedown;
305 engine->instmem.suspend = nv50_instmem_suspend;
306 engine->instmem.resume = nv50_instmem_resume;
307 engine->instmem.get = nv50_instmem_get;
308 engine->instmem.put = nv50_instmem_put;
309 engine->instmem.map = nv50_instmem_map;
310 engine->instmem.unmap = nv50_instmem_unmap;
311 if (dev_priv->chipset == 0x50)
312 engine->instmem.flush = nv50_instmem_flush;
314 engine->instmem.flush = nv84_instmem_flush;
315 engine->mc.init = nv50_mc_init;
316 engine->mc.takedown = nv50_mc_takedown;
317 engine->timer.init = nv04_timer_init;
318 engine->timer.read = nv04_timer_read;
319 engine->timer.takedown = nv04_timer_takedown;
320 engine->fb.init = nv50_fb_init;
321 engine->fb.takedown = nv50_fb_takedown;
322 engine->fifo.channels = 128;
323 engine->fifo.init = nv50_fifo_init;
324 engine->fifo.takedown = nv50_fifo_takedown;
325 engine->fifo.disable = nv04_fifo_disable;
326 engine->fifo.enable = nv04_fifo_enable;
327 engine->fifo.reassign = nv04_fifo_reassign;
328 engine->fifo.channel_id = nv50_fifo_channel_id;
329 engine->fifo.create_context = nv50_fifo_create_context;
330 engine->fifo.destroy_context = nv50_fifo_destroy_context;
331 engine->fifo.load_context = nv50_fifo_load_context;
332 engine->fifo.unload_context = nv50_fifo_unload_context;
333 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
334 engine->display.early_init = nv50_display_early_init;
335 engine->display.late_takedown = nv50_display_late_takedown;
336 engine->display.create = nv50_display_create;
337 engine->display.init = nv50_display_init;
338 engine->display.destroy = nv50_display_destroy;
339 engine->gpio.init = nv50_gpio_init;
340 engine->gpio.takedown = nv50_gpio_fini;
341 engine->gpio.get = nv50_gpio_get;
342 engine->gpio.set = nv50_gpio_set;
343 engine->gpio.irq_register = nv50_gpio_irq_register;
344 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
345 engine->gpio.irq_enable = nv50_gpio_irq_enable;
346 switch (dev_priv->chipset) {
357 engine->pm.clock_get = nv50_pm_clock_get;
358 engine->pm.clock_pre = nv50_pm_clock_pre;
359 engine->pm.clock_set = nv50_pm_clock_set;
362 engine->pm.clocks_get = nva3_pm_clocks_get;
363 engine->pm.clocks_pre = nva3_pm_clocks_pre;
364 engine->pm.clocks_set = nva3_pm_clocks_set;
367 engine->pm.voltage_get = nouveau_voltage_gpio_get;
368 engine->pm.voltage_set = nouveau_voltage_gpio_set;
369 if (dev_priv->chipset >= 0x84)
370 engine->pm.temp_get = nv84_temp_get;
372 engine->pm.temp_get = nv40_temp_get;
373 engine->vram.init = nv50_vram_init;
374 engine->vram.takedown = nv50_vram_fini;
375 engine->vram.get = nv50_vram_new;
376 engine->vram.put = nv50_vram_del;
377 engine->vram.flags_valid = nv50_vram_flags_valid;
380 engine->instmem.init = nvc0_instmem_init;
381 engine->instmem.takedown = nvc0_instmem_takedown;
382 engine->instmem.suspend = nvc0_instmem_suspend;
383 engine->instmem.resume = nvc0_instmem_resume;
384 engine->instmem.get = nv50_instmem_get;
385 engine->instmem.put = nv50_instmem_put;
386 engine->instmem.map = nv50_instmem_map;
387 engine->instmem.unmap = nv50_instmem_unmap;
388 engine->instmem.flush = nv84_instmem_flush;
389 engine->mc.init = nv50_mc_init;
390 engine->mc.takedown = nv50_mc_takedown;
391 engine->timer.init = nv04_timer_init;
392 engine->timer.read = nv04_timer_read;
393 engine->timer.takedown = nv04_timer_takedown;
394 engine->fb.init = nvc0_fb_init;
395 engine->fb.takedown = nvc0_fb_takedown;
396 engine->fifo.channels = 128;
397 engine->fifo.init = nvc0_fifo_init;
398 engine->fifo.takedown = nvc0_fifo_takedown;
399 engine->fifo.disable = nvc0_fifo_disable;
400 engine->fifo.enable = nvc0_fifo_enable;
401 engine->fifo.reassign = nvc0_fifo_reassign;
402 engine->fifo.channel_id = nvc0_fifo_channel_id;
403 engine->fifo.create_context = nvc0_fifo_create_context;
404 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
405 engine->fifo.load_context = nvc0_fifo_load_context;
406 engine->fifo.unload_context = nvc0_fifo_unload_context;
407 engine->display.early_init = nv50_display_early_init;
408 engine->display.late_takedown = nv50_display_late_takedown;
409 engine->display.create = nv50_display_create;
410 engine->display.init = nv50_display_init;
411 engine->display.destroy = nv50_display_destroy;
412 engine->gpio.init = nv50_gpio_init;
413 engine->gpio.takedown = nouveau_stub_takedown;
414 engine->gpio.get = nv50_gpio_get;
415 engine->gpio.set = nv50_gpio_set;
416 engine->gpio.irq_register = nv50_gpio_irq_register;
417 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
418 engine->gpio.irq_enable = nv50_gpio_irq_enable;
419 engine->vram.init = nvc0_vram_init;
420 engine->vram.takedown = nv50_vram_fini;
421 engine->vram.get = nvc0_vram_new;
422 engine->vram.put = nv50_vram_del;
423 engine->vram.flags_valid = nvc0_vram_flags_valid;
424 engine->pm.temp_get = nv84_temp_get;
425 engine->pm.clocks_get = nvc0_pm_clocks_get;
426 engine->pm.voltage_get = nouveau_voltage_gpio_get;
427 engine->pm.voltage_set = nouveau_voltage_gpio_set;
430 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
435 if (nouveau_modeset == 2) {
436 engine->display.early_init = nouveau_stub_init;
437 engine->display.late_takedown = nouveau_stub_takedown;
438 engine->display.create = nouveau_stub_init;
439 engine->display.init = nouveau_stub_init;
440 engine->display.destroy = nouveau_stub_takedown;
447 nouveau_vga_set_decode(void *priv, bool state)
449 struct drm_device *dev = priv;
450 struct drm_nouveau_private *dev_priv = dev->dev_private;
452 if (dev_priv->chipset >= 0x40)
453 nv_wr32(dev, 0x88054, state);
455 nv_wr32(dev, 0x1854, state);
458 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
459 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
461 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
464 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
465 enum vga_switcheroo_state state)
467 struct drm_device *dev = pci_get_drvdata(pdev);
468 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
469 if (state == VGA_SWITCHEROO_ON) {
470 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
471 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
472 nouveau_pci_resume(pdev);
473 drm_kms_helper_poll_enable(dev);
474 dev->switch_power_state = DRM_SWITCH_POWER_ON;
476 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
477 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
478 drm_kms_helper_poll_disable(dev);
479 nouveau_pci_suspend(pdev, pmm);
480 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
484 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
486 struct drm_device *dev = pci_get_drvdata(pdev);
487 nouveau_fbcon_output_poll_changed(dev);
490 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
492 struct drm_device *dev = pci_get_drvdata(pdev);
495 spin_lock(&dev->count_lock);
496 can_switch = (dev->open_count == 0);
497 spin_unlock(&dev->count_lock);
502 nouveau_card_init(struct drm_device *dev)
504 struct drm_nouveau_private *dev_priv = dev->dev_private;
505 struct nouveau_engine *engine;
508 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
509 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
510 nouveau_switcheroo_reprobe,
511 nouveau_switcheroo_can_switch);
513 /* Initialise internal driver API hooks */
514 ret = nouveau_init_engine_ptrs(dev);
517 engine = &dev_priv->engine;
518 spin_lock_init(&dev_priv->channels.lock);
519 spin_lock_init(&dev_priv->tile.lock);
520 spin_lock_init(&dev_priv->context_switch_lock);
521 spin_lock_init(&dev_priv->vm_lock);
523 /* Make the CRTCs and I2C buses accessible */
524 ret = engine->display.early_init(dev);
528 /* Parse BIOS tables / Run init tables if card not POSTed */
529 ret = nouveau_bios_init(dev);
531 goto out_display_early;
533 nouveau_pm_init(dev);
535 ret = engine->vram.init(dev);
539 ret = nouveau_gpuobj_init(dev);
543 ret = engine->instmem.init(dev);
547 ret = nouveau_mem_vram_init(dev);
551 ret = nouveau_mem_gart_init(dev);
556 ret = engine->mc.init(dev);
561 ret = engine->gpio.init(dev);
566 ret = engine->timer.init(dev);
571 ret = engine->fb.init(dev);
575 if (!dev_priv->noaccel) {
576 switch (dev_priv->card_type) {
578 nv04_graph_create(dev);
581 nv10_graph_create(dev);
585 nv20_graph_create(dev);
588 nv40_graph_create(dev);
591 nv50_graph_create(dev);
594 nvc0_graph_create(dev);
600 switch (dev_priv->chipset) {
607 nv84_crypt_create(dev);
611 switch (dev_priv->card_type) {
613 switch (dev_priv->chipset) {
618 nva3_copy_create(dev);
623 nvc0_copy_create(dev, 0);
624 nvc0_copy_create(dev, 1);
630 if (dev_priv->card_type == NV_40 ||
631 dev_priv->chipset == 0x31 ||
632 dev_priv->chipset == 0x34 ||
633 dev_priv->chipset == 0x36)
634 nv31_mpeg_create(dev);
636 if (dev_priv->card_type == NV_50 &&
637 (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
638 nv50_mpeg_create(dev);
640 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
641 if (dev_priv->eng[e]) {
642 ret = dev_priv->eng[e]->init(dev, e);
649 ret = engine->fifo.init(dev);
654 ret = nouveau_irq_init(dev);
658 /* initialise general modesetting */
659 drm_mode_config_init(dev);
660 drm_mode_create_scaling_mode_property(dev);
661 drm_mode_create_dithering_property(dev);
662 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
663 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 1);
664 dev->mode_config.min_width = 0;
665 dev->mode_config.min_height = 0;
666 if (dev_priv->card_type < NV_10) {
667 dev->mode_config.max_width = 2048;
668 dev->mode_config.max_height = 2048;
670 if (dev_priv->card_type < NV_50) {
671 dev->mode_config.max_width = 4096;
672 dev->mode_config.max_height = 4096;
674 dev->mode_config.max_width = 8192;
675 dev->mode_config.max_height = 8192;
678 ret = engine->display.create(dev);
682 if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
683 ret = nouveau_fence_init(dev);
687 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
692 mutex_unlock(&dev_priv->channel->mutex);
695 if (dev->mode_config.num_crtc) {
696 ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
700 nouveau_fbcon_init(dev);
701 drm_kms_helper_poll_init(dev);
707 nouveau_channel_put_unlocked(&dev_priv->channel);
709 nouveau_fence_fini(dev);
711 engine->display.destroy(dev);
713 nouveau_irq_fini(dev);
715 if (!dev_priv->noaccel)
716 engine->fifo.takedown(dev);
718 if (!dev_priv->noaccel) {
719 for (e = e - 1; e >= 0; e--) {
720 if (!dev_priv->eng[e])
722 dev_priv->eng[e]->fini(dev, e, false);
723 dev_priv->eng[e]->destroy(dev,e );
727 engine->fb.takedown(dev);
729 engine->timer.takedown(dev);
731 engine->gpio.takedown(dev);
733 engine->mc.takedown(dev);
735 nouveau_mem_gart_fini(dev);
737 nouveau_mem_vram_fini(dev);
739 engine->instmem.takedown(dev);
741 nouveau_gpuobj_takedown(dev);
743 engine->vram.takedown(dev);
745 nouveau_pm_fini(dev);
746 nouveau_bios_takedown(dev);
748 engine->display.late_takedown(dev);
750 vga_client_register(dev->pdev, NULL, NULL, NULL);
754 static void nouveau_card_takedown(struct drm_device *dev)
756 struct drm_nouveau_private *dev_priv = dev->dev_private;
757 struct nouveau_engine *engine = &dev_priv->engine;
760 if (dev->mode_config.num_crtc) {
761 drm_kms_helper_poll_fini(dev);
762 nouveau_fbcon_fini(dev);
763 drm_vblank_cleanup(dev);
766 if (dev_priv->channel) {
767 nouveau_channel_put_unlocked(&dev_priv->channel);
768 nouveau_fence_fini(dev);
771 engine->display.destroy(dev);
772 drm_mode_config_cleanup(dev);
774 if (!dev_priv->noaccel) {
775 engine->fifo.takedown(dev);
776 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
777 if (dev_priv->eng[e]) {
778 dev_priv->eng[e]->fini(dev, e, false);
779 dev_priv->eng[e]->destroy(dev,e );
783 engine->fb.takedown(dev);
784 engine->timer.takedown(dev);
785 engine->gpio.takedown(dev);
786 engine->mc.takedown(dev);
787 engine->display.late_takedown(dev);
789 if (dev_priv->vga_ram) {
790 nouveau_bo_unpin(dev_priv->vga_ram);
791 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
794 mutex_lock(&dev->struct_mutex);
795 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
796 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
797 mutex_unlock(&dev->struct_mutex);
798 nouveau_mem_gart_fini(dev);
799 nouveau_mem_vram_fini(dev);
801 engine->instmem.takedown(dev);
802 nouveau_gpuobj_takedown(dev);
803 engine->vram.takedown(dev);
805 nouveau_irq_fini(dev);
807 nouveau_pm_fini(dev);
808 nouveau_bios_takedown(dev);
810 vga_client_register(dev->pdev, NULL, NULL, NULL);
814 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
816 struct drm_nouveau_private *dev_priv = dev->dev_private;
817 struct nouveau_fpriv *fpriv;
820 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
821 if (unlikely(!fpriv))
824 spin_lock_init(&fpriv->lock);
825 INIT_LIST_HEAD(&fpriv->channels);
827 if (dev_priv->card_type == NV_50) {
828 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
835 if (dev_priv->card_type >= NV_C0) {
836 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
844 file_priv->driver_priv = fpriv;
848 /* here a client dies, release the stuff that was allocated for its
850 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
852 nouveau_channel_cleanup(dev, file_priv);
856 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
858 struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
859 nouveau_vm_ref(NULL, &fpriv->vm, NULL);
863 /* first module load, setup the mmio/fb mapping */
864 /* KMS: we need mmio at load time, not when the first drm client opens. */
865 int nouveau_firstopen(struct drm_device *dev)
870 /* if we have an OF card, copy vbios to RAMIN */
871 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
873 #if defined(__powerpc__)
875 const uint32_t *bios;
876 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
878 NV_INFO(dev, "Unable to get the OF node\n");
882 bios = of_get_property(dn, "NVDA,BMP", &size);
884 for (i = 0; i < size; i += 4)
885 nv_wi32(dev, i, bios[i/4]);
886 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
888 NV_INFO(dev, "Unable to get the OF bios\n");
893 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
895 struct pci_dev *pdev = dev->pdev;
896 struct apertures_struct *aper = alloc_apertures(3);
900 aper->ranges[0].base = pci_resource_start(pdev, 1);
901 aper->ranges[0].size = pci_resource_len(pdev, 1);
904 if (pci_resource_len(pdev, 2)) {
905 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
906 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
910 if (pci_resource_len(pdev, 3)) {
911 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
912 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
919 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
921 struct drm_nouveau_private *dev_priv = dev->dev_private;
922 bool primary = false;
923 dev_priv->apertures = nouveau_get_apertures(dev);
924 if (!dev_priv->apertures)
928 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
931 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
935 int nouveau_load(struct drm_device *dev, unsigned long flags)
937 struct drm_nouveau_private *dev_priv;
939 resource_size_t mmio_start_offs;
942 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
947 dev->dev_private = dev_priv;
950 dev_priv->flags = flags & NOUVEAU_FLAGS;
952 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
953 dev->pci_vendor, dev->pci_device, dev->pdev->class);
955 /* resource 0 is mmio regs */
956 /* resource 1 is linear FB */
957 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
958 /* resource 6 is bios */
960 /* map the mmio regs */
961 mmio_start_offs = pci_resource_start(dev->pdev, 0);
962 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
963 if (!dev_priv->mmio) {
964 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
965 "Please report your setup to " DRIVER_EMAIL "\n");
969 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
970 (unsigned long long)mmio_start_offs);
973 /* Put the card in BE mode if it's not */
974 if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
975 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
980 /* Time to determine the card architecture */
981 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
982 dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
984 /* We're dealing with >=NV10 */
985 if ((reg0 & 0x0f000000) > 0) {
986 /* Bit 27-20 contain the architecture in hex */
987 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
988 dev_priv->stepping = (reg0 & 0xff);
990 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
991 if (reg0 & 0x00f00000)
992 dev_priv->chipset = 0x05;
994 dev_priv->chipset = 0x04;
996 dev_priv->chipset = 0xff;
998 switch (dev_priv->chipset & 0xf0) {
1003 dev_priv->card_type = dev_priv->chipset & 0xf0;
1007 dev_priv->card_type = NV_40;
1013 dev_priv->card_type = NV_50;
1016 dev_priv->card_type = NV_C0;
1019 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1024 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1025 dev_priv->card_type, reg0);
1027 /* Determine whether we'll attempt acceleration or not, some
1028 * cards are disabled by default here due to them being known
1029 * non-functional, or never been tested due to lack of hw.
1031 dev_priv->noaccel = !!nouveau_noaccel;
1032 if (nouveau_noaccel == -1) {
1033 switch (dev_priv->chipset) {
1034 case 0xc1: /* known broken */
1035 case 0xc8: /* never tested */
1036 NV_INFO(dev, "acceleration disabled by default, pass "
1037 "noaccel=0 to force enable\n");
1038 dev_priv->noaccel = true;
1041 dev_priv->noaccel = false;
1046 ret = nouveau_remove_conflicting_drivers(dev);
1050 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1051 if (dev_priv->card_type >= NV_40) {
1053 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1056 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1058 ioremap(pci_resource_start(dev->pdev, ramin_bar),
1059 dev_priv->ramin_size);
1060 if (!dev_priv->ramin) {
1061 NV_ERROR(dev, "Failed to PRAMIN BAR");
1066 dev_priv->ramin_size = 1 * 1024 * 1024;
1067 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1068 dev_priv->ramin_size);
1069 if (!dev_priv->ramin) {
1070 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1076 nouveau_OF_copy_vbios_to_ramin(dev);
1079 if (dev->pci_device == 0x01a0)
1080 dev_priv->flags |= NV_NFORCE;
1081 else if (dev->pci_device == 0x01f0)
1082 dev_priv->flags |= NV_NFORCE2;
1084 /* For kernel modesetting, init card now and bring up fbcon */
1085 ret = nouveau_card_init(dev);
1092 iounmap(dev_priv->ramin);
1094 iounmap(dev_priv->mmio);
1097 dev->dev_private = NULL;
1102 void nouveau_lastclose(struct drm_device *dev)
1104 vga_switcheroo_process_delayed_switch();
1107 int nouveau_unload(struct drm_device *dev)
1109 struct drm_nouveau_private *dev_priv = dev->dev_private;
1111 nouveau_card_takedown(dev);
1113 iounmap(dev_priv->mmio);
1114 iounmap(dev_priv->ramin);
1117 dev->dev_private = NULL;
1121 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1122 struct drm_file *file_priv)
1124 struct drm_nouveau_private *dev_priv = dev->dev_private;
1125 struct drm_nouveau_getparam *getparam = data;
1127 switch (getparam->param) {
1128 case NOUVEAU_GETPARAM_CHIPSET_ID:
1129 getparam->value = dev_priv->chipset;
1131 case NOUVEAU_GETPARAM_PCI_VENDOR:
1132 getparam->value = dev->pci_vendor;
1134 case NOUVEAU_GETPARAM_PCI_DEVICE:
1135 getparam->value = dev->pci_device;
1137 case NOUVEAU_GETPARAM_BUS_TYPE:
1138 if (drm_pci_device_is_agp(dev))
1139 getparam->value = NV_AGP;
1140 else if (pci_is_pcie(dev->pdev))
1141 getparam->value = NV_PCIE;
1143 getparam->value = NV_PCI;
1145 case NOUVEAU_GETPARAM_FB_SIZE:
1146 getparam->value = dev_priv->fb_available_size;
1148 case NOUVEAU_GETPARAM_AGP_SIZE:
1149 getparam->value = dev_priv->gart_info.aper_size;
1151 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1152 getparam->value = 0; /* deprecated */
1154 case NOUVEAU_GETPARAM_PTIMER_TIME:
1155 getparam->value = dev_priv->engine.timer.read(dev);
1157 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1158 getparam->value = 1;
1160 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1161 getparam->value = 1;
1163 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1164 /* NV40 and NV50 versions are quite different, but register
1165 * address is the same. User is supposed to know the card
1166 * family anyway... */
1167 if (dev_priv->chipset >= 0x40) {
1168 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1173 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1181 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1182 struct drm_file *file_priv)
1184 struct drm_nouveau_setparam *setparam = data;
1186 switch (setparam->param) {
1188 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1195 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1197 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1198 uint32_t reg, uint32_t mask, uint32_t val)
1200 struct drm_nouveau_private *dev_priv = dev->dev_private;
1201 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1202 uint64_t start = ptimer->read(dev);
1205 if ((nv_rd32(dev, reg) & mask) == val)
1207 } while (ptimer->read(dev) - start < timeout);
1212 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1214 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1215 uint32_t reg, uint32_t mask, uint32_t val)
1217 struct drm_nouveau_private *dev_priv = dev->dev_private;
1218 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1219 uint64_t start = ptimer->read(dev);
1222 if ((nv_rd32(dev, reg) & mask) != val)
1224 } while (ptimer->read(dev) - start < timeout);
1229 /* Wait until cond(data) == true, up until timeout has hit */
1231 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1232 bool (*cond)(void *), void *data)
1234 struct drm_nouveau_private *dev_priv = dev->dev_private;
1235 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1236 u64 start = ptimer->read(dev);
1239 if (cond(data) == true)
1241 } while (ptimer->read(dev) - start < timeout);
1246 /* Waits for PGRAPH to go completely idle */
1247 bool nouveau_wait_for_idle(struct drm_device *dev)
1249 struct drm_nouveau_private *dev_priv = dev->dev_private;
1252 if (dev_priv->card_type == NV_40)
1253 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1255 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1256 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1257 nv_rd32(dev, NV04_PGRAPH_STATUS));