drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_pm.h"
  40 #include "nv50_display.h"
  41
  42 static void nouveau_stub_takedown(struct drm_device *dev) {}
  43 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  44
  45 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48         struct nouveau_engine *engine = &dev_priv->engine;
  49
  50         switch (dev_priv->chipset & 0xf0) {
  51         case 0x00:
  52                 engine->instmem.init            = nv04_instmem_init;
  53                 engine->instmem.takedown        = nv04_instmem_takedown;
  54                 engine->instmem.suspend         = nv04_instmem_suspend;
  55                 engine->instmem.resume          = nv04_instmem_resume;
  56                 engine->instmem.populate        = nv04_instmem_populate;
  57                 engine->instmem.clear           = nv04_instmem_clear;
  58                 engine->instmem.bind            = nv04_instmem_bind;
  59                 engine->instmem.unbind          = nv04_instmem_unbind;
  60                 engine->instmem.flush           = nv04_instmem_flush;
  61                 engine->mc.init                 = nv04_mc_init;
  62                 engine->mc.takedown             = nv04_mc_takedown;
  63                 engine->timer.init              = nv04_timer_init;
  64                 engine->timer.read              = nv04_timer_read;
  65                 engine->timer.takedown          = nv04_timer_takedown;
  66                 engine->fb.init                 = nv04_fb_init;
  67                 engine->fb.takedown             = nv04_fb_takedown;
  68                 engine->graph.init              = nv04_graph_init;
  69                 engine->graph.takedown          = nv04_graph_takedown;
  70                 engine->graph.fifo_access       = nv04_graph_fifo_access;
  71                 engine->graph.channel           = nv04_graph_channel;
  72                 engine->graph.create_context    = nv04_graph_create_context;
  73                 engine->graph.destroy_context   = nv04_graph_destroy_context;
  74                 engine->graph.load_context      = nv04_graph_load_context;
  75                 engine->graph.unload_context    = nv04_graph_unload_context;
  76                 engine->fifo.channels           = 16;
  77                 engine->fifo.init               = nv04_fifo_init;
  78                 engine->fifo.takedown           = nouveau_stub_takedown;
  79                 engine->fifo.disable            = nv04_fifo_disable;
  80                 engine->fifo.enable             = nv04_fifo_enable;
  81                 engine->fifo.reassign           = nv04_fifo_reassign;
  82                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  83                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  84                 engine->fifo.create_context     = nv04_fifo_create_context;
  85                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  86                 engine->fifo.load_context       = nv04_fifo_load_context;
  87                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  88                 engine->display.early_init      = nv04_display_early_init;
  89                 engine->display.late_takedown   = nv04_display_late_takedown;
  90                 engine->display.create          = nv04_display_create;
  91                 engine->display.init            = nv04_display_init;
  92                 engine->display.destroy         = nv04_display_destroy;
  93                 engine->gpio.init               = nouveau_stub_init;
  94                 engine->gpio.takedown           = nouveau_stub_takedown;
  95                 engine->gpio.get                = NULL;
  96                 engine->gpio.set                = NULL;
  97                 engine->gpio.irq_enable         = NULL;
  98                 engine->pm.clock_get            = nv04_pm_clock_get;
  99                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 100                 engine->pm.clock_set            = nv04_pm_clock_set;
 101                 engine->crypt.init              = nouveau_stub_init;
 102                 engine->crypt.takedown          = nouveau_stub_takedown;
 103                 break;
 104         case 0x10:
 105                 engine->instmem.init            = nv04_instmem_init;
 106                 engine->instmem.takedown        = nv04_instmem_takedown;
 107                 engine->instmem.suspend         = nv04_instmem_suspend;
 108                 engine->instmem.resume          = nv04_instmem_resume;
 109                 engine->instmem.populate        = nv04_instmem_populate;
 110                 engine->instmem.clear           = nv04_instmem_clear;
 111                 engine->instmem.bind            = nv04_instmem_bind;
 112                 engine->instmem.unbind          = nv04_instmem_unbind;
 113                 engine->instmem.flush           = nv04_instmem_flush;
 114                 engine->mc.init                 = nv04_mc_init;
 115                 engine->mc.takedown             = nv04_mc_takedown;
 116                 engine->timer.init              = nv04_timer_init;
 117                 engine->timer.read              = nv04_timer_read;
 118                 engine->timer.takedown          = nv04_timer_takedown;
 119                 engine->fb.init                 = nv10_fb_init;
 120                 engine->fb.takedown             = nv10_fb_takedown;
 121                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 122                 engine->graph.init              = nv10_graph_init;
 123                 engine->graph.takedown          = nv10_graph_takedown;
 124                 engine->graph.channel           = nv10_graph_channel;
 125                 engine->graph.create_context    = nv10_graph_create_context;
 126                 engine->graph.destroy_context   = nv10_graph_destroy_context;
 127                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 128                 engine->graph.load_context      = nv10_graph_load_context;
 129                 engine->graph.unload_context    = nv10_graph_unload_context;
 130                 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
 131                 engine->fifo.channels           = 32;
 132                 engine->fifo.init               = nv10_fifo_init;
 133                 engine->fifo.takedown           = nouveau_stub_takedown;
 134                 engine->fifo.disable            = nv04_fifo_disable;
 135                 engine->fifo.enable             = nv04_fifo_enable;
 136                 engine->fifo.reassign           = nv04_fifo_reassign;
 137                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 138                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 139                 engine->fifo.create_context     = nv10_fifo_create_context;
 140                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 141                 engine->fifo.load_context       = nv10_fifo_load_context;
 142                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 143                 engine->display.early_init      = nv04_display_early_init;
 144                 engine->display.late_takedown   = nv04_display_late_takedown;
 145                 engine->display.create          = nv04_display_create;
 146                 engine->display.init            = nv04_display_init;
 147                 engine->display.destroy         = nv04_display_destroy;
 148                 engine->gpio.init               = nouveau_stub_init;
 149                 engine->gpio.takedown           = nouveau_stub_takedown;
 150                 engine->gpio.get                = nv10_gpio_get;
 151                 engine->gpio.set                = nv10_gpio_set;
 152                 engine->gpio.irq_enable         = NULL;
 153                 engine->pm.clock_get            = nv04_pm_clock_get;
 154                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 155                 engine->pm.clock_set            = nv04_pm_clock_set;
 156                 engine->crypt.init              = nouveau_stub_init;
 157                 engine->crypt.takedown          = nouveau_stub_takedown;
 158                 break;
 159         case 0x20:
 160                 engine->instmem.init            = nv04_instmem_init;
 161                 engine->instmem.takedown        = nv04_instmem_takedown;
 162                 engine->instmem.suspend         = nv04_instmem_suspend;
 163                 engine->instmem.resume          = nv04_instmem_resume;
 164                 engine->instmem.populate        = nv04_instmem_populate;
 165                 engine->instmem.clear           = nv04_instmem_clear;
 166                 engine->instmem.bind            = nv04_instmem_bind;
 167                 engine->instmem.unbind          = nv04_instmem_unbind;
 168                 engine->instmem.flush           = nv04_instmem_flush;
 169                 engine->mc.init                 = nv04_mc_init;
 170                 engine->mc.takedown             = nv04_mc_takedown;
 171                 engine->timer.init              = nv04_timer_init;
 172                 engine->timer.read              = nv04_timer_read;
 173                 engine->timer.takedown          = nv04_timer_takedown;
 174                 engine->fb.init                 = nv10_fb_init;
 175                 engine->fb.takedown             = nv10_fb_takedown;
 176                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 177                 engine->graph.init              = nv20_graph_init;
 178                 engine->graph.takedown          = nv20_graph_takedown;
 179                 engine->graph.channel           = nv10_graph_channel;
 180                 engine->graph.create_context    = nv20_graph_create_context;
 181                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 182                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 183                 engine->graph.load_context      = nv20_graph_load_context;
 184                 engine->graph.unload_context    = nv20_graph_unload_context;
 185                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 186                 engine->fifo.channels           = 32;
 187                 engine->fifo.init               = nv10_fifo_init;
 188                 engine->fifo.takedown           = nouveau_stub_takedown;
 189                 engine->fifo.disable            = nv04_fifo_disable;
 190                 engine->fifo.enable             = nv04_fifo_enable;
 191                 engine->fifo.reassign           = nv04_fifo_reassign;
 192                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 193                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 194                 engine->fifo.create_context     = nv10_fifo_create_context;
 195                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 196                 engine->fifo.load_context       = nv10_fifo_load_context;
 197                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 198                 engine->display.early_init      = nv04_display_early_init;
 199                 engine->display.late_takedown   = nv04_display_late_takedown;
 200                 engine->display.create          = nv04_display_create;
 201                 engine->display.init            = nv04_display_init;
 202                 engine->display.destroy         = nv04_display_destroy;
 203                 engine->gpio.init               = nouveau_stub_init;
 204                 engine->gpio.takedown           = nouveau_stub_takedown;
 205                 engine->gpio.get                = nv10_gpio_get;
 206                 engine->gpio.set                = nv10_gpio_set;
 207                 engine->gpio.irq_enable         = NULL;
 208                 engine->pm.clock_get            = nv04_pm_clock_get;
 209                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 210                 engine->pm.clock_set            = nv04_pm_clock_set;
 211                 engine->crypt.init              = nouveau_stub_init;
 212                 engine->crypt.takedown          = nouveau_stub_takedown;
 213                 break;
 214         case 0x30:
 215                 engine->instmem.init            = nv04_instmem_init;
 216                 engine->instmem.takedown        = nv04_instmem_takedown;
 217                 engine->instmem.suspend         = nv04_instmem_suspend;
 218                 engine->instmem.resume          = nv04_instmem_resume;
 219                 engine->instmem.populate        = nv04_instmem_populate;
 220                 engine->instmem.clear           = nv04_instmem_clear;
 221                 engine->instmem.bind            = nv04_instmem_bind;
 222                 engine->instmem.unbind          = nv04_instmem_unbind;
 223                 engine->instmem.flush           = nv04_instmem_flush;
 224                 engine->mc.init                 = nv04_mc_init;
 225                 engine->mc.takedown             = nv04_mc_takedown;
 226                 engine->timer.init              = nv04_timer_init;
 227                 engine->timer.read              = nv04_timer_read;
 228                 engine->timer.takedown          = nv04_timer_takedown;
 229                 engine->fb.init                 = nv30_fb_init;
 230                 engine->fb.takedown             = nv30_fb_takedown;
 231                 engine->fb.set_region_tiling    = nv10_fb_set_region_tiling;
 232                 engine->graph.init              = nv30_graph_init;
 233                 engine->graph.takedown          = nv20_graph_takedown;
 234                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 235                 engine->graph.channel           = nv10_graph_channel;
 236                 engine->graph.create_context    = nv20_graph_create_context;
 237                 engine->graph.destroy_context   = nv20_graph_destroy_context;
 238                 engine->graph.load_context      = nv20_graph_load_context;
 239                 engine->graph.unload_context    = nv20_graph_unload_context;
 240                 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
 241                 engine->fifo.channels           = 32;
 242                 engine->fifo.init               = nv10_fifo_init;
 243                 engine->fifo.takedown           = nouveau_stub_takedown;
 244                 engine->fifo.disable            = nv04_fifo_disable;
 245                 engine->fifo.enable             = nv04_fifo_enable;
 246                 engine->fifo.reassign           = nv04_fifo_reassign;
 247                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 248                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 249                 engine->fifo.create_context     = nv10_fifo_create_context;
 250                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 251                 engine->fifo.load_context       = nv10_fifo_load_context;
 252                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 253                 engine->display.early_init      = nv04_display_early_init;
 254                 engine->display.late_takedown   = nv04_display_late_takedown;
 255                 engine->display.create          = nv04_display_create;
 256                 engine->display.init            = nv04_display_init;
 257                 engine->display.destroy         = nv04_display_destroy;
 258                 engine->gpio.init               = nouveau_stub_init;
 259                 engine->gpio.takedown           = nouveau_stub_takedown;
 260                 engine->gpio.get                = nv10_gpio_get;
 261                 engine->gpio.set                = nv10_gpio_set;
 262                 engine->gpio.irq_enable         = NULL;
 263                 engine->pm.clock_get            = nv04_pm_clock_get;
 264                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 265                 engine->pm.clock_set            = nv04_pm_clock_set;
 266                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 267                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 268                 engine->crypt.init              = nouveau_stub_init;
 269                 engine->crypt.takedown          = nouveau_stub_takedown;
 270                 break;
 271         case 0x40:
 272         case 0x60:
 273                 engine->instmem.init            = nv04_instmem_init;
 274                 engine->instmem.takedown        = nv04_instmem_takedown;
 275                 engine->instmem.suspend         = nv04_instmem_suspend;
 276                 engine->instmem.resume          = nv04_instmem_resume;
 277                 engine->instmem.populate        = nv04_instmem_populate;
 278                 engine->instmem.clear           = nv04_instmem_clear;
 279                 engine->instmem.bind            = nv04_instmem_bind;
 280                 engine->instmem.unbind          = nv04_instmem_unbind;
 281                 engine->instmem.flush           = nv04_instmem_flush;
 282                 engine->mc.init                 = nv40_mc_init;
 283                 engine->mc.takedown             = nv40_mc_takedown;
 284                 engine->timer.init              = nv04_timer_init;
 285                 engine->timer.read              = nv04_timer_read;
 286                 engine->timer.takedown          = nv04_timer_takedown;
 287                 engine->fb.init                 = nv40_fb_init;
 288                 engine->fb.takedown             = nv40_fb_takedown;
 289                 engine->fb.set_region_tiling    = nv40_fb_set_region_tiling;
 290                 engine->graph.init              = nv40_graph_init;
 291                 engine->graph.takedown          = nv40_graph_takedown;
 292                 engine->graph.fifo_access       = nv04_graph_fifo_access;
 293                 engine->graph.channel           = nv40_graph_channel;
 294                 engine->graph.create_context    = nv40_graph_create_context;
 295                 engine->graph.destroy_context   = nv40_graph_destroy_context;
 296                 engine->graph.load_context      = nv40_graph_load_context;
 297                 engine->graph.unload_context    = nv40_graph_unload_context;
 298                 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
 299                 engine->fifo.channels           = 32;
 300                 engine->fifo.init               = nv40_fifo_init;
 301                 engine->fifo.takedown           = nouveau_stub_takedown;
 302                 engine->fifo.disable            = nv04_fifo_disable;
 303                 engine->fifo.enable             = nv04_fifo_enable;
 304                 engine->fifo.reassign           = nv04_fifo_reassign;
 305                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 306                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 307                 engine->fifo.create_context     = nv40_fifo_create_context;
 308                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 309                 engine->fifo.load_context       = nv40_fifo_load_context;
 310                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 311                 engine->display.early_init      = nv04_display_early_init;
 312                 engine->display.late_takedown   = nv04_display_late_takedown;
 313                 engine->display.create          = nv04_display_create;
 314                 engine->display.init            = nv04_display_init;
 315                 engine->display.destroy         = nv04_display_destroy;
 316                 engine->gpio.init               = nouveau_stub_init;
 317                 engine->gpio.takedown           = nouveau_stub_takedown;
 318                 engine->gpio.get                = nv10_gpio_get;
 319                 engine->gpio.set                = nv10_gpio_set;
 320                 engine->gpio.irq_enable         = NULL;
 321                 engine->pm.clock_get            = nv04_pm_clock_get;
 322                 engine->pm.clock_pre            = nv04_pm_clock_pre;
 323                 engine->pm.clock_set            = nv04_pm_clock_set;
 324                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 325                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 326                 engine->pm.temp_get             = nv40_temp_get;
 327                 engine->crypt.init              = nouveau_stub_init;
 328                 engine->crypt.takedown          = nouveau_stub_takedown;
 329                 break;
 330         case 0x50:
 331         case 0x80: /* gotta love NVIDIA's consistency.. */
 332         case 0x90:
 333         case 0xA0:
 334                 engine->instmem.init            = nv50_instmem_init;
 335                 engine->instmem.takedown        = nv50_instmem_takedown;
 336                 engine->instmem.suspend         = nv50_instmem_suspend;
 337                 engine->instmem.resume          = nv50_instmem_resume;
 338                 engine->instmem.populate        = nv50_instmem_populate;
 339                 engine->instmem.clear           = nv50_instmem_clear;
 340                 engine->instmem.bind            = nv50_instmem_bind;
 341                 engine->instmem.unbind          = nv50_instmem_unbind;
 342                 if (dev_priv->chipset == 0x50)
 343                         engine->instmem.flush   = nv50_instmem_flush;
 344                 else
 345                         engine->instmem.flush   = nv84_instmem_flush;
 346                 engine->mc.init                 = nv50_mc_init;
 347                 engine->mc.takedown             = nv50_mc_takedown;
 348                 engine->timer.init              = nv04_timer_init;
 349                 engine->timer.read              = nv04_timer_read;
 350                 engine->timer.takedown          = nv04_timer_takedown;
 351                 engine->fb.init                 = nv50_fb_init;
 352                 engine->fb.takedown             = nv50_fb_takedown;
 353                 engine->graph.init              = nv50_graph_init;
 354                 engine->graph.takedown          = nv50_graph_takedown;
 355                 engine->graph.fifo_access       = nv50_graph_fifo_access;
 356                 engine->graph.channel           = nv50_graph_channel;
 357                 engine->graph.create_context    = nv50_graph_create_context;
 358                 engine->graph.destroy_context   = nv50_graph_destroy_context;
 359                 engine->graph.load_context      = nv50_graph_load_context;
 360                 engine->graph.unload_context    = nv50_graph_unload_context;
 361                 if (dev_priv->chipset != 0x86)
 362                         engine->graph.tlb_flush = nv50_graph_tlb_flush;
 363                 else {
 364                         /* from what i can see nvidia do this on every
 365                          * pre-NVA3 board except NVAC, but, we've only
 366                          * ever seen problems on NV86
 367                          */
 368                         engine->graph.tlb_flush = nv86_graph_tlb_flush;
 369                 }
 370                 engine->fifo.channels           = 128;
 371                 engine->fifo.init               = nv50_fifo_init;
 372                 engine->fifo.takedown           = nv50_fifo_takedown;
 373                 engine->fifo.disable            = nv04_fifo_disable;
 374                 engine->fifo.enable             = nv04_fifo_enable;
 375                 engine->fifo.reassign           = nv04_fifo_reassign;
 376                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 377                 engine->fifo.create_context     = nv50_fifo_create_context;
 378                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 379                 engine->fifo.load_context       = nv50_fifo_load_context;
 380                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 381                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 382                 engine->display.early_init      = nv50_display_early_init;
 383                 engine->display.late_takedown   = nv50_display_late_takedown;
 384                 engine->display.create          = nv50_display_create;
 385                 engine->display.init            = nv50_display_init;
 386                 engine->display.destroy         = nv50_display_destroy;
 387                 engine->gpio.init               = nv50_gpio_init;
 388                 engine->gpio.takedown           = nouveau_stub_takedown;
 389                 engine->gpio.get                = nv50_gpio_get;
 390                 engine->gpio.set                = nv50_gpio_set;
 391                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 392                 switch (dev_priv->chipset) {
 393                 case 0x84:
 394                 case 0x86:
 395                 case 0x92:
 396                 case 0x94:
 397                 case 0x96:
 398                 case 0x98:
 399                 case 0xa0:
 400                 case 0x50:
 401                         engine->pm.clock_get    = nv50_pm_clock_get;
 402                         engine->pm.clock_pre    = nv50_pm_clock_pre;
 403                         engine->pm.clock_set    = nv50_pm_clock_set;
 404                         break;
 405                 default:
 406                         engine->pm.clock_get    = nva3_pm_clock_get;
 407                         engine->pm.clock_pre    = nva3_pm_clock_pre;
 408                         engine->pm.clock_set    = nva3_pm_clock_set;
 409                         break;
 410                 }
 411                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 412                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 413                 if (dev_priv->chipset >= 0x84)
 414                         engine->pm.temp_get     = nv84_temp_get;
 415                 else
 416                         engine->pm.temp_get     = nv40_temp_get;
 417                 switch (dev_priv->chipset) {
 418                 case 0x84:
 419                 case 0x86:
 420                 case 0x92:
 421                 case 0x94:
 422                 case 0x96:
 423                 case 0xa0:
 424                         engine->crypt.init      = nv84_crypt_init;
 425                         engine->crypt.takedown  = nv84_crypt_fini;
 426                         engine->crypt.create_context = nv84_crypt_create_context;
 427                         engine->crypt.destroy_context = nv84_crypt_destroy_context;
 428                         break;
 429                 default:
 430                         engine->crypt.init      = nouveau_stub_init;
 431                         engine->crypt.takedown  = nouveau_stub_takedown;
 432                         break;
 433                 }
 434                 break;
 435         case 0xC0:
 436                 engine->instmem.init            = nvc0_instmem_init;
 437                 engine->instmem.takedown        = nvc0_instmem_takedown;
 438                 engine->instmem.suspend         = nvc0_instmem_suspend;
 439                 engine->instmem.resume          = nvc0_instmem_resume;
 440                 engine->instmem.populate        = nvc0_instmem_populate;
 441                 engine->instmem.clear           = nvc0_instmem_clear;
 442                 engine->instmem.bind            = nvc0_instmem_bind;
 443                 engine->instmem.unbind          = nvc0_instmem_unbind;
 444                 engine->instmem.flush           = nvc0_instmem_flush;
 445                 engine->mc.init                 = nv50_mc_init;
 446                 engine->mc.takedown             = nv50_mc_takedown;
 447                 engine->timer.init              = nv04_timer_init;
 448                 engine->timer.read              = nv04_timer_read;
 449                 engine->timer.takedown          = nv04_timer_takedown;
 450                 engine->fb.init                 = nvc0_fb_init;
 451                 engine->fb.takedown             = nvc0_fb_takedown;
 452                 engine->graph.init              = nvc0_graph_init;
 453                 engine->graph.takedown          = nvc0_graph_takedown;
 454                 engine->graph.fifo_access       = nvc0_graph_fifo_access;
 455                 engine->graph.channel           = nvc0_graph_channel;
 456                 engine->graph.create_context    = nvc0_graph_create_context;
 457                 engine->graph.destroy_context   = nvc0_graph_destroy_context;
 458                 engine->graph.load_context      = nvc0_graph_load_context;
 459                 engine->graph.unload_context    = nvc0_graph_unload_context;
 460                 engine->fifo.channels           = 128;
 461                 engine->fifo.init               = nvc0_fifo_init;
 462                 engine->fifo.takedown           = nvc0_fifo_takedown;
 463                 engine->fifo.disable            = nvc0_fifo_disable;
 464                 engine->fifo.enable             = nvc0_fifo_enable;
 465                 engine->fifo.reassign           = nvc0_fifo_reassign;
 466                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 467                 engine->fifo.create_context     = nvc0_fifo_create_context;
 468                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 469                 engine->fifo.load_context       = nvc0_fifo_load_context;
 470                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 471                 engine->display.early_init      = nv50_display_early_init;
 472                 engine->display.late_takedown   = nv50_display_late_takedown;
 473                 engine->display.create          = nv50_display_create;
 474                 engine->display.init            = nv50_display_init;
 475                 engine->display.destroy         = nv50_display_destroy;
 476                 engine->gpio.init               = nv50_gpio_init;
 477                 engine->gpio.takedown           = nouveau_stub_takedown;
 478                 engine->gpio.get                = nv50_gpio_get;
 479                 engine->gpio.set                = nv50_gpio_set;
 480                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 481                 engine->crypt.init              = nouveau_stub_init;
 482                 engine->crypt.takedown          = nouveau_stub_takedown;
 483                 break;
 484         default:
 485                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 486                 return 1;
 487         }
 488
 489         return 0;
 490 }
 491
 492 static unsigned int
 493 nouveau_vga_set_decode(void *priv, bool state)
 494 {
 495         struct drm_device *dev = priv;
 496         struct drm_nouveau_private *dev_priv = dev->dev_private;
 497
 498         if (dev_priv->chipset >= 0x40)
 499                 nv_wr32(dev, 0x88054, state);
 500         else
 501                 nv_wr32(dev, 0x1854, state);
 502
 503         if (state)
 504                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 505                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 506         else
 507                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 508 }
 509
 510 static int
 511 nouveau_card_init_channel(struct drm_device *dev)
 512 {
 513         struct drm_nouveau_private *dev_priv = dev->dev_private;
 514         struct nouveau_gpuobj *gpuobj = NULL;
 515         int ret;
 516
 517         ret = nouveau_channel_alloc(dev, &dev_priv->channel,
 518                                     (struct drm_file *)-2, NvDmaFB, NvDmaTT);
 519         if (ret)
 520                 return ret;
 521
 522         ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
 523                                      0, dev_priv->vram_size,
 524                                      NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
 525                                      &gpuobj);
 526         if (ret)
 527                 goto out_err;
 528
 529         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj);
 530         nouveau_gpuobj_ref(NULL, &gpuobj);
 531         if (ret)
 532                 goto out_err;
 533
 534         ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
 535                                           dev_priv->gart_info.aper_size,
 536                                           NV_DMA_ACCESS_RW, &gpuobj, NULL);
 537         if (ret)
 538                 goto out_err;
 539
 540         ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj);
 541         nouveau_gpuobj_ref(NULL, &gpuobj);
 542         if (ret)
 543                 goto out_err;
 544
 545         mutex_unlock(&dev_priv->channel->mutex);
 546         return 0;
 547
 548 out_err:
 549         nouveau_channel_put(&dev_priv->channel);
 550         return ret;
 551 }
 552
 553 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 554                                          enum vga_switcheroo_state state)
 555 {
 556         struct drm_device *dev = pci_get_drvdata(pdev);
 557         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 558         if (state == VGA_SWITCHEROO_ON) {
 559                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 560                 nouveau_pci_resume(pdev);
 561                 drm_kms_helper_poll_enable(dev);
 562         } else {
 563                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 564                 drm_kms_helper_poll_disable(dev);
 565                 nouveau_pci_suspend(pdev, pmm);
 566         }
 567 }
 568
 569 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 570 {
 571         struct drm_device *dev = pci_get_drvdata(pdev);
 572         bool can_switch;
 573
 574         spin_lock(&dev->count_lock);
 575         can_switch = (dev->open_count == 0);
 576         spin_unlock(&dev->count_lock);
 577         return can_switch;
 578 }
 579
 580 int
 581 nouveau_card_init(struct drm_device *dev)
 582 {
 583         struct drm_nouveau_private *dev_priv = dev->dev_private;
 584         struct nouveau_engine *engine;
 585         int ret;
 586
 587         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 588         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 589                                        nouveau_switcheroo_can_switch);
 590
 591         /* Initialise internal driver API hooks */
 592         ret = nouveau_init_engine_ptrs(dev);
 593         if (ret)
 594                 goto out;
 595         engine = &dev_priv->engine;
 596         spin_lock_init(&dev_priv->channels.lock);
 597         spin_lock_init(&dev_priv->context_switch_lock);
 598
 599         /* Make the CRTCs and I2C buses accessible */
 600         ret = engine->display.early_init(dev);
 601         if (ret)
 602                 goto out;
 603
 604         /* Parse BIOS tables / Run init tables if card not POSTed */
 605         ret = nouveau_bios_init(dev);
 606         if (ret)
 607                 goto out_display_early;
 608
 609         nouveau_pm_init(dev);
 610
 611         ret = nouveau_mem_vram_init(dev);
 612         if (ret)
 613                 goto out_bios;
 614
 615         ret = nouveau_gpuobj_init(dev);
 616         if (ret)
 617                 goto out_vram;
 618
 619         ret = engine->instmem.init(dev);
 620         if (ret)
 621                 goto out_gpuobj;
 622
 623         ret = nouveau_mem_gart_init(dev);
 624         if (ret)
 625                 goto out_instmem;
 626
 627         /* PMC */
 628         ret = engine->mc.init(dev);
 629         if (ret)
 630                 goto out_gart;
 631
 632         /* PGPIO */
 633         ret = engine->gpio.init(dev);
 634         if (ret)
 635                 goto out_mc;
 636
 637         /* PTIMER */
 638         ret = engine->timer.init(dev);
 639         if (ret)
 640                 goto out_gpio;
 641
 642         /* PFB */
 643         ret = engine->fb.init(dev);
 644         if (ret)
 645                 goto out_timer;
 646
 647         if (nouveau_noaccel)
 648                 engine->graph.accel_blocked = true;
 649         else {
 650                 /* PGRAPH */
 651                 ret = engine->graph.init(dev);
 652                 if (ret)
 653                         goto out_fb;
 654
 655                 /* PCRYPT */
 656                 ret = engine->crypt.init(dev);
 657                 if (ret)
 658                         goto out_graph;
 659
 660                 /* PFIFO */
 661                 ret = engine->fifo.init(dev);
 662                 if (ret)
 663                         goto out_crypt;
 664         }
 665
 666         ret = engine->display.create(dev);
 667         if (ret)
 668                 goto out_fifo;
 669
 670         ret = nouveau_irq_init(dev);
 671         if (ret)
 672                 goto out_display;
 673
 674         ret = drm_vblank_init(dev, 0);
 675         if (ret)
 676                 goto out_irq;
 677
 678         /* what about PVIDEO/PCRTC/PRAMDAC etc? */
 679
 680         if (!engine->graph.accel_blocked) {
 681                 ret = nouveau_fence_init(dev);
 682                 if (ret)
 683                         goto out_irq;
 684
 685                 ret = nouveau_card_init_channel(dev);
 686                 if (ret)
 687                         goto out_fence;
 688         }
 689
 690         ret = nouveau_backlight_init(dev);
 691         if (ret)
 692                 NV_ERROR(dev, "Error %d registering backlight\n", ret);
 693
 694         nouveau_fbcon_init(dev);
 695         drm_kms_helper_poll_init(dev);
 696         return 0;
 697
 698 out_fence:
 699         nouveau_fence_fini(dev);
 700 out_irq:
 701         nouveau_irq_fini(dev);
 702 out_display:
 703         engine->display.destroy(dev);
 704 out_fifo:
 705         if (!nouveau_noaccel)
 706                 engine->fifo.takedown(dev);
 707 out_crypt:
 708         if (!nouveau_noaccel)
 709                 engine->crypt.takedown(dev);
 710 out_graph:
 711         if (!nouveau_noaccel)
 712                 engine->graph.takedown(dev);
 713 out_fb:
 714         engine->fb.takedown(dev);
 715 out_timer:
 716         engine->timer.takedown(dev);
 717 out_gpio:
 718         engine->gpio.takedown(dev);
 719 out_mc:
 720         engine->mc.takedown(dev);
 721 out_gart:
 722         nouveau_mem_gart_fini(dev);
 723 out_instmem:
 724         engine->instmem.takedown(dev);
 725 out_gpuobj:
 726         nouveau_gpuobj_takedown(dev);
 727 out_vram:
 728         nouveau_mem_vram_fini(dev);
 729 out_bios:
 730         nouveau_pm_fini(dev);
 731         nouveau_bios_takedown(dev);
 732 out_display_early:
 733         engine->display.late_takedown(dev);
 734 out:
 735         vga_client_register(dev->pdev, NULL, NULL, NULL);
 736         return ret;
 737 }
 738
 739 static void nouveau_card_takedown(struct drm_device *dev)
 740 {
 741         struct drm_nouveau_private *dev_priv = dev->dev_private;
 742         struct nouveau_engine *engine = &dev_priv->engine;
 743
 744         nouveau_backlight_exit(dev);
 745
 746         if (!engine->graph.accel_blocked) {
 747                 nouveau_fence_fini(dev);
 748                 nouveau_channel_put_unlocked(&dev_priv->channel);
 749         }
 750
 751         if (!nouveau_noaccel) {
 752                 engine->fifo.takedown(dev);
 753                 engine->crypt.takedown(dev);
 754                 engine->graph.takedown(dev);
 755         }
 756         engine->fb.takedown(dev);
 757         engine->timer.takedown(dev);
 758         engine->gpio.takedown(dev);
 759         engine->mc.takedown(dev);
 760         engine->display.late_takedown(dev);
 761
 762         mutex_lock(&dev->struct_mutex);
 763         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 764         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 765         mutex_unlock(&dev->struct_mutex);
 766         nouveau_mem_gart_fini(dev);
 767
 768         engine->instmem.takedown(dev);
 769         nouveau_gpuobj_takedown(dev);
 770         nouveau_mem_vram_fini(dev);
 771
 772         nouveau_irq_fini(dev);
 773
 774         nouveau_pm_fini(dev);
 775         nouveau_bios_takedown(dev);
 776
 777         vga_client_register(dev->pdev, NULL, NULL, NULL);
 778 }
 779
 780 /* here a client dies, release the stuff that was allocated for its
 781  * file_priv */
 782 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 783 {
 784         nouveau_channel_cleanup(dev, file_priv);
 785 }
 786
 787 /* first module load, setup the mmio/fb mapping */
 788 /* KMS: we need mmio at load time, not when the first drm client opens. */
 789 int nouveau_firstopen(struct drm_device *dev)
 790 {
 791         return 0;
 792 }
 793
 794 /* if we have an OF card, copy vbios to RAMIN */
 795 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 796 {
 797 #if defined(__powerpc__)
 798         int size, i;
 799         const uint32_t *bios;
 800         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 801         if (!dn) {
 802                 NV_INFO(dev, "Unable to get the OF node\n");
 803                 return;
 804         }
 805
 806         bios = of_get_property(dn, "NVDA,BMP", &size);
 807         if (bios) {
 808                 for (i = 0; i < size; i += 4)
 809                         nv_wi32(dev, i, bios[i/4]);
 810                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 811         } else {
 812                 NV_INFO(dev, "Unable to get the OF bios\n");
 813         }
 814 #endif
 815 }
 816
 817 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 818 {
 819         struct pci_dev *pdev = dev->pdev;
 820         struct apertures_struct *aper = alloc_apertures(3);
 821         if (!aper)
 822                 return NULL;
 823
 824         aper->ranges[0].base = pci_resource_start(pdev, 1);
 825         aper->ranges[0].size = pci_resource_len(pdev, 1);
 826         aper->count = 1;
 827
 828         if (pci_resource_len(pdev, 2)) {
 829                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 830                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 831                 aper->count++;
 832         }
 833
 834         if (pci_resource_len(pdev, 3)) {
 835                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 836                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 837                 aper->count++;
 838         }
 839
 840         return aper;
 841 }
 842
 843 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 844 {
 845         struct drm_nouveau_private *dev_priv = dev->dev_private;
 846         bool primary = false;
 847         dev_priv->apertures = nouveau_get_apertures(dev);
 848         if (!dev_priv->apertures)
 849                 return -ENOMEM;
 850
 851 #ifdef CONFIG_X86
 852         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 853 #endif
 854
 855         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 856         return 0;
 857 }
 858
 859 int nouveau_load(struct drm_device *dev, unsigned long flags)
 860 {
 861         struct drm_nouveau_private *dev_priv;
 862         uint32_t reg0;
 863         resource_size_t mmio_start_offs;
 864         int ret;
 865
 866         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 867         if (!dev_priv) {
 868                 ret = -ENOMEM;
 869                 goto err_out;
 870         }
 871         dev->dev_private = dev_priv;
 872         dev_priv->dev = dev;
 873
 874         dev_priv->flags = flags & NOUVEAU_FLAGS;
 875
 876         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
 877                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
 878
 879         dev_priv->wq = create_workqueue("nouveau");
 880         if (!dev_priv->wq) {
 881                 ret = -EINVAL;
 882                 goto err_priv;
 883         }
 884
 885         /* resource 0 is mmio regs */
 886         /* resource 1 is linear FB */
 887         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
 888         /* resource 6 is bios */
 889
 890         /* map the mmio regs */
 891         mmio_start_offs = pci_resource_start(dev->pdev, 0);
 892         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
 893         if (!dev_priv->mmio) {
 894                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
 895                          "Please report your setup to " DRIVER_EMAIL "\n");
 896                 ret = -EINVAL;
 897                 goto err_wq;
 898         }
 899         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
 900                                         (unsigned long long)mmio_start_offs);
 901
 902 #ifdef __BIG_ENDIAN
 903         /* Put the card in BE mode if it's not */
 904         if (nv_rd32(dev, NV03_PMC_BOOT_1))
 905                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
 906
 907         DRM_MEMORYBARRIER();
 908 #endif
 909
 910         /* Time to determine the card architecture */
 911         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
 912
 913         /* We're dealing with >=NV10 */
 914         if ((reg0 & 0x0f000000) > 0) {
 915                 /* Bit 27-20 contain the architecture in hex */
 916                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
 917         /* NV04 or NV05 */
 918         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
 919                 if (reg0 & 0x00f00000)
 920                         dev_priv->chipset = 0x05;
 921                 else
 922                         dev_priv->chipset = 0x04;
 923         } else
 924                 dev_priv->chipset = 0xff;
 925
 926         switch (dev_priv->chipset & 0xf0) {
 927         case 0x00:
 928         case 0x10:
 929         case 0x20:
 930         case 0x30:
 931                 dev_priv->card_type = dev_priv->chipset & 0xf0;
 932                 break;
 933         case 0x40:
 934         case 0x60:
 935                 dev_priv->card_type = NV_40;
 936                 break;
 937         case 0x50:
 938         case 0x80:
 939         case 0x90:
 940         case 0xa0:
 941                 dev_priv->card_type = NV_50;
 942                 break;
 943         case 0xc0:
 944                 dev_priv->card_type = NV_C0;
 945                 break;
 946         default:
 947                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
 948                 ret = -EINVAL;
 949                 goto err_mmio;
 950         }
 951
 952         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
 953                 dev_priv->card_type, reg0);
 954
 955         ret = nouveau_remove_conflicting_drivers(dev);
 956         if (ret)
 957                 goto err_mmio;
 958
 959         /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
 960         if (dev_priv->card_type >= NV_40) {
 961                 int ramin_bar = 2;
 962                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
 963                         ramin_bar = 3;
 964
 965                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
 966                 dev_priv->ramin =
 967                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
 968                                 dev_priv->ramin_size);
 969                 if (!dev_priv->ramin) {
 970                         NV_ERROR(dev, "Failed to PRAMIN BAR");
 971                         ret = -ENOMEM;
 972                         goto err_mmio;
 973                 }
 974         } else {
 975                 dev_priv->ramin_size = 1 * 1024 * 1024;
 976                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
 977                                           dev_priv->ramin_size);
 978                 if (!dev_priv->ramin) {
 979                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
 980                         ret = -ENOMEM;
 981                         goto err_mmio;
 982                 }
 983         }
 984
 985         nouveau_OF_copy_vbios_to_ramin(dev);
 986
 987         /* Special flags */
 988         if (dev->pci_device == 0x01a0)
 989                 dev_priv->flags |= NV_NFORCE;
 990         else if (dev->pci_device == 0x01f0)
 991                 dev_priv->flags |= NV_NFORCE2;
 992
 993         /* For kernel modesetting, init card now and bring up fbcon */
 994         ret = nouveau_card_init(dev);
 995         if (ret)
 996                 goto err_ramin;
 997
 998         return 0;
 999
1000 err_ramin:
1001         iounmap(dev_priv->ramin);
1002 err_mmio:
1003         iounmap(dev_priv->mmio);
1004 err_wq:
1005         destroy_workqueue(dev_priv->wq);
1006 err_priv:
1007         kfree(dev_priv);
1008         dev->dev_private = NULL;
1009 err_out:
1010         return ret;
1011 }
1012
1013 void nouveau_lastclose(struct drm_device *dev)
1014 {
1015 }
1016
1017 int nouveau_unload(struct drm_device *dev)
1018 {
1019         struct drm_nouveau_private *dev_priv = dev->dev_private;
1020         struct nouveau_engine *engine = &dev_priv->engine;
1021
1022         drm_kms_helper_poll_fini(dev);
1023         nouveau_fbcon_fini(dev);
1024         engine->display.destroy(dev);
1025         nouveau_card_takedown(dev);
1026
1027         iounmap(dev_priv->mmio);
1028         iounmap(dev_priv->ramin);
1029
1030         kfree(dev_priv);
1031         dev->dev_private = NULL;
1032         return 0;
1033 }
1034
1035 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1036                                                 struct drm_file *file_priv)
1037 {
1038         struct drm_nouveau_private *dev_priv = dev->dev_private;
1039         struct drm_nouveau_getparam *getparam = data;
1040
1041         switch (getparam->param) {
1042         case NOUVEAU_GETPARAM_CHIPSET_ID:
1043                 getparam->value = dev_priv->chipset;
1044                 break;
1045         case NOUVEAU_GETPARAM_PCI_VENDOR:
1046                 getparam->value = dev->pci_vendor;
1047                 break;
1048         case NOUVEAU_GETPARAM_PCI_DEVICE:
1049                 getparam->value = dev->pci_device;
1050                 break;
1051         case NOUVEAU_GETPARAM_BUS_TYPE:
1052                 if (drm_device_is_agp(dev))
1053                         getparam->value = NV_AGP;
1054                 else if (drm_device_is_pcie(dev))
1055                         getparam->value = NV_PCIE;
1056                 else
1057                         getparam->value = NV_PCI;
1058                 break;
1059         case NOUVEAU_GETPARAM_FB_PHYSICAL:
1060                 getparam->value = dev_priv->fb_phys;
1061                 break;
1062         case NOUVEAU_GETPARAM_AGP_PHYSICAL:
1063                 getparam->value = dev_priv->gart_info.aper_base;
1064                 break;
1065         case NOUVEAU_GETPARAM_PCI_PHYSICAL:
1066                 if (dev->sg) {
1067                         getparam->value = (unsigned long)dev->sg->virtual;
1068                 } else {
1069                         NV_ERROR(dev, "Requested PCIGART address, "
1070                                         "while no PCIGART was created\n");
1071                         return -EINVAL;
1072                 }
1073                 break;
1074         case NOUVEAU_GETPARAM_FB_SIZE:
1075                 getparam->value = dev_priv->fb_available_size;
1076                 break;
1077         case NOUVEAU_GETPARAM_AGP_SIZE:
1078                 getparam->value = dev_priv->gart_info.aper_size;
1079                 break;
1080         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1081                 getparam->value = dev_priv->vm_vram_base;
1082                 break;
1083         case NOUVEAU_GETPARAM_PTIMER_TIME:
1084                 getparam->value = dev_priv->engine.timer.read(dev);
1085                 break;
1086         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1087                 getparam->value = 1;
1088                 break;
1089         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1090                 /* NV40 and NV50 versions are quite different, but register
1091                  * address is the same. User is supposed to know the card
1092                  * family anyway... */
1093                 if (dev_priv->chipset >= 0x40) {
1094                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1095                         break;
1096                 }
1097                 /* FALLTHRU */
1098         default:
1099                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1100                 return -EINVAL;
1101         }
1102
1103         return 0;
1104 }
1105
1106 int
1107 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1108                        struct drm_file *file_priv)
1109 {
1110         struct drm_nouveau_setparam *setparam = data;
1111
1112         switch (setparam->param) {
1113         default:
1114                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1115                 return -EINVAL;
1116         }
1117
1118         return 0;
1119 }
1120
1121 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1122 bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
1123                         uint32_t reg, uint32_t mask, uint32_t val)
1124 {
1125         struct drm_nouveau_private *dev_priv = dev->dev_private;
1126         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1127         uint64_t start = ptimer->read(dev);
1128
1129         do {
1130                 if ((nv_rd32(dev, reg) & mask) == val)
1131                         return true;
1132         } while (ptimer->read(dev) - start < timeout);
1133
1134         return false;
1135 }
1136
1137 /* Waits for PGRAPH to go completely idle */
1138 bool nouveau_wait_for_idle(struct drm_device *dev)
1139 {
1140         struct drm_nouveau_private *dev_priv = dev->dev_private;
1141         uint32_t mask = ~0;
1142
1143         if (dev_priv->card_type == NV_40)
1144                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1145
1146         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1147                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1148                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1149                 return false;
1150         }
1151
1152         return true;
1153 }
1154