drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31
  32 #include <nvif/class.h>
  33
  34 #include "nouveau_drm.h"
  35 #include "nouveau_dma.h"
  36 #include "nouveau_gem.h"
  37 #include "nouveau_connector.h"
  38 #include "nouveau_encoder.h"
  39 #include "nouveau_crtc.h"
  40 #include "nouveau_fence.h"
  41 #include "nv50_display.h"
  42
  43 #define EVO_DMA_NR 9
  44
  45 #define EVO_MASTER  (0x00)
  46 #define EVO_FLIP(c) (0x01 + (c))
  47 #define EVO_OVLY(c) (0x05 + (c))
  48 #define EVO_OIMM(c) (0x09 + (c))
  49 #define EVO_CURS(c) (0x0d + (c))
  50
  51 /* offsets in shared sync bo of various structures */
  52 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  53 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  54 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  55 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  56
  57 /******************************************************************************
  58  * EVO channel
  59  *****************************************************************************/
  60
  61 struct nv50_chan {
  62         struct nvif_object user;
  63 };
  64
  65 static int
  66 nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
  67                  void *data, u32 size, struct nv50_chan *chan)
  68 {
  69         const u32 handle = (oclass[0] << 16) | head;
  70         u32 sclass[8];
  71         int ret, i;
  72
  73         ret = nvif_object_sclass(disp, sclass, ARRAY_SIZE(sclass));
  74         WARN_ON(ret > ARRAY_SIZE(sclass));
  75         if (ret < 0)
  76                 return ret;
  77
  78         while (oclass[0]) {
  79                 for (i = 0; i < ARRAY_SIZE(sclass); i++) {
  80                         if (sclass[i] == oclass[0]) {
  81                                 ret = nvif_object_init(disp, NULL, handle,
  82                                                        oclass[0], data, size,
  83                                                        &chan->user);
  84                                 if (ret == 0)
  85                                         nvif_object_map(&chan->user);
  86                                 return ret;
  87                         }
  88                 }
  89                 oclass++;
  90         }
  91
  92         return -ENOSYS;
  93 }
  94
  95 static void
  96 nv50_chan_destroy(struct nv50_chan *chan)
  97 {
  98         nvif_object_fini(&chan->user);
  99 }
 100
 101 /******************************************************************************
 102  * PIO EVO channel
 103  *****************************************************************************/
 104
 105 struct nv50_pioc {
 106         struct nv50_chan base;
 107 };
 108
 109 static void
 110 nv50_pioc_destroy(struct nv50_pioc *pioc)
 111 {
 112         nv50_chan_destroy(&pioc->base);
 113 }
 114
 115 static int
 116 nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
 117                  void *data, u32 size, struct nv50_pioc *pioc)
 118 {
 119         return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
 120 }
 121
 122 /******************************************************************************
 123  * Cursor Immediate
 124  *****************************************************************************/
 125
 126 struct nv50_curs {
 127         struct nv50_pioc base;
 128 };
 129
 130 static int
 131 nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
 132 {
 133         struct nv50_disp_cursor_v0 args = {
 134                 .head = head,
 135         };
 136         static const u32 oclass[] = {
 137                 GK104_DISP_CURSOR,
 138                 GF110_DISP_CURSOR,
 139                 GT214_DISP_CURSOR,
 140                 G82_DISP_CURSOR,
 141                 NV50_DISP_CURSOR,
 142                 0
 143         };
 144
 145         return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
 146                                &curs->base);
 147 }
 148
 149 /******************************************************************************
 150  * Overlay Immediate
 151  *****************************************************************************/
 152
 153 struct nv50_oimm {
 154         struct nv50_pioc base;
 155 };
 156
 157 static int
 158 nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
 159 {
 160         struct nv50_disp_cursor_v0 args = {
 161                 .head = head,
 162         };
 163         static const u32 oclass[] = {
 164                 GK104_DISP_OVERLAY,
 165                 GF110_DISP_OVERLAY,
 166                 GT214_DISP_OVERLAY,
 167                 G82_DISP_OVERLAY,
 168                 NV50_DISP_OVERLAY,
 169                 0
 170         };
 171
 172         return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
 173                                &oimm->base);
 174 }
 175
 176 /******************************************************************************
 177  * DMA EVO channel
 178  *****************************************************************************/
 179
 180 struct nv50_dmac {
 181         struct nv50_chan base;
 182         dma_addr_t handle;
 183         u32 *ptr;
 184
 185         struct nvif_object sync;
 186         struct nvif_object vram;
 187
 188         /* Protects against concurrent pushbuf access to this channel, lock is
 189          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 190          * dropped again by evo_kick. */
 191         struct mutex lock;
 192 };
 193
 194 static void
 195 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 196 {
 197         nvif_object_fini(&dmac->vram);
 198         nvif_object_fini(&dmac->sync);
 199
 200         nv50_chan_destroy(&dmac->base);
 201
 202         if (dmac->ptr) {
 203                 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
 204                 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
 205         }
 206 }
 207
 208 static int
 209 nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
 210                  void *data, u32 size, u64 syncbuf,
 211                  struct nv50_dmac *dmac)
 212 {
 213         struct nvif_device *device = nvif_device(disp);
 214         struct nv50_disp_core_channel_dma_v0 *args = data;
 215         struct nvif_object pushbuf;
 216         int ret;
 217
 218         mutex_init(&dmac->lock);
 219
 220         dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
 221                                          PAGE_SIZE, &dmac->handle);
 222         if (!dmac->ptr)
 223                 return -ENOMEM;
 224
 225         ret = nvif_object_init(nvif_object(device), NULL,
 226                                args->pushbuf, NV_DMA_FROM_MEMORY,
 227                                &(struct nv_dma_v0) {
 228                                         .target = NV_DMA_V0_TARGET_PCI_US,
 229                                         .access = NV_DMA_V0_ACCESS_RD,
 230                                         .start = dmac->handle + 0x0000,
 231                                         .limit = dmac->handle + 0x0fff,
 232                                }, sizeof(struct nv_dma_v0), &pushbuf);
 233         if (ret)
 234                 return ret;
 235
 236         ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
 237         nvif_object_fini(&pushbuf);
 238         if (ret)
 239                 return ret;
 240
 241         ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
 242                                NV_DMA_IN_MEMORY,
 243                                &(struct nv_dma_v0) {
 244                                         .target = NV_DMA_V0_TARGET_VRAM,
 245                                         .access = NV_DMA_V0_ACCESS_RDWR,
 246                                         .start = syncbuf + 0x0000,
 247                                         .limit = syncbuf + 0x0fff,
 248                                }, sizeof(struct nv_dma_v0),
 249                                &dmac->sync);
 250         if (ret)
 251                 return ret;
 252
 253         ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
 254                                NV_DMA_IN_MEMORY,
 255                                &(struct nv_dma_v0) {
 256                                         .target = NV_DMA_V0_TARGET_VRAM,
 257                                         .access = NV_DMA_V0_ACCESS_RDWR,
 258                                         .start = 0,
 259                                         .limit = device->info.ram_user - 1,
 260                                }, sizeof(struct nv_dma_v0),
 261                                &dmac->vram);
 262         if (ret)
 263                 return ret;
 264
 265         return ret;
 266 }
 267
 268 /******************************************************************************
 269  * Core
 270  *****************************************************************************/
 271
 272 struct nv50_mast {
 273         struct nv50_dmac base;
 274 };
 275
 276 static int
 277 nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
 278 {
 279         struct nv50_disp_core_channel_dma_v0 args = {
 280                 .pushbuf = 0xb0007d00,
 281         };
 282         static const u32 oclass[] = {
 283                 GM204_DISP_CORE_CHANNEL_DMA,
 284                 GM107_DISP_CORE_CHANNEL_DMA,
 285                 GK110_DISP_CORE_CHANNEL_DMA,
 286                 GK104_DISP_CORE_CHANNEL_DMA,
 287                 GF110_DISP_CORE_CHANNEL_DMA,
 288                 GT214_DISP_CORE_CHANNEL_DMA,
 289                 GT206_DISP_CORE_CHANNEL_DMA,
 290                 GT200_DISP_CORE_CHANNEL_DMA,
 291                 G82_DISP_CORE_CHANNEL_DMA,
 292                 NV50_DISP_CORE_CHANNEL_DMA,
 293                 0
 294         };
 295
 296         return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
 297                                &core->base);
 298 }
 299
 300 /******************************************************************************
 301  * Base
 302  *****************************************************************************/
 303
 304 struct nv50_sync {
 305         struct nv50_dmac base;
 306         u32 addr;
 307         u32 data;
 308 };
 309
 310 static int
 311 nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
 312                  struct nv50_sync *base)
 313 {
 314         struct nv50_disp_base_channel_dma_v0 args = {
 315                 .pushbuf = 0xb0007c00 | head,
 316                 .head = head,
 317         };
 318         static const u32 oclass[] = {
 319                 GK110_DISP_BASE_CHANNEL_DMA,
 320                 GK104_DISP_BASE_CHANNEL_DMA,
 321                 GF110_DISP_BASE_CHANNEL_DMA,
 322                 GT214_DISP_BASE_CHANNEL_DMA,
 323                 GT200_DISP_BASE_CHANNEL_DMA,
 324                 G82_DISP_BASE_CHANNEL_DMA,
 325                 NV50_DISP_BASE_CHANNEL_DMA,
 326                 0
 327         };
 328
 329         return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
 330                                 syncbuf, &base->base);
 331 }
 332
 333 /******************************************************************************
 334  * Overlay
 335  *****************************************************************************/
 336
 337 struct nv50_ovly {
 338         struct nv50_dmac base;
 339 };
 340
 341 static int
 342 nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
 343                  struct nv50_ovly *ovly)
 344 {
 345         struct nv50_disp_overlay_channel_dma_v0 args = {
 346                 .pushbuf = 0xb0007e00 | head,
 347                 .head = head,
 348         };
 349         static const u32 oclass[] = {
 350                 GK104_DISP_OVERLAY_CONTROL_DMA,
 351                 GF110_DISP_OVERLAY_CONTROL_DMA,
 352                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 353                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 354                 G82_DISP_OVERLAY_CHANNEL_DMA,
 355                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 356                 0
 357         };
 358
 359         return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
 360                                 syncbuf, &ovly->base);
 361 }
 362
 363 struct nv50_head {
 364         struct nouveau_crtc base;
 365         struct nouveau_bo *image;
 366         struct nv50_curs curs;
 367         struct nv50_sync sync;
 368         struct nv50_ovly ovly;
 369         struct nv50_oimm oimm;
 370 };
 371
 372 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 373 #define nv50_curs(c) (&nv50_head(c)->curs)
 374 #define nv50_sync(c) (&nv50_head(c)->sync)
 375 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 376 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 377 #define nv50_chan(c) (&(c)->base.base)
 378 #define nv50_vers(c) nv50_chan(c)->user.oclass
 379
 380 struct nv50_fbdma {
 381         struct list_head head;
 382         struct nvif_object core;
 383         struct nvif_object base[4];
 384 };
 385
 386 struct nv50_disp {
 387         struct nvif_object *disp;
 388         struct nv50_mast mast;
 389
 390         struct list_head fbdma;
 391
 392         struct nouveau_bo *sync;
 393 };
 394
 395 static struct nv50_disp *
 396 nv50_disp(struct drm_device *dev)
 397 {
 398         return nouveau_display(dev)->priv;
 399 }
 400
 401 #define nv50_mast(d) (&nv50_disp(d)->mast)
 402
 403 static struct drm_crtc *
 404 nv50_display_crtc_get(struct drm_encoder *encoder)
 405 {
 406         return nouveau_encoder(encoder)->crtc;
 407 }
 408
 409 /******************************************************************************
 410  * EVO channel helpers
 411  *****************************************************************************/
 412 static u32 *
 413 evo_wait(void *evoc, int nr)
 414 {
 415         struct nv50_dmac *dmac = evoc;
 416         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 417
 418         mutex_lock(&dmac->lock);
 419         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 420                 dmac->ptr[put] = 0x20000000;
 421
 422                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 423                 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
 424                         mutex_unlock(&dmac->lock);
 425                         nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
 426                         return NULL;
 427                 }
 428
 429                 put = 0;
 430         }
 431
 432         return dmac->ptr + put;
 433 }
 434
 435 static void
 436 evo_kick(u32 *push, void *evoc)
 437 {
 438         struct nv50_dmac *dmac = evoc;
 439         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 440         mutex_unlock(&dmac->lock);
 441 }
 442
 443 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 444 #define evo_data(p,d)   *((p)++) = (d)
 445
 446 static bool
 447 evo_sync_wait(void *data)
 448 {
 449         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 450                 return true;
 451         usleep_range(1, 2);
 452         return false;
 453 }
 454
 455 static int
 456 evo_sync(struct drm_device *dev)
 457 {
 458         struct nvif_device *device = &nouveau_drm(dev)->device;
 459         struct nv50_disp *disp = nv50_disp(dev);
 460         struct nv50_mast *mast = nv50_mast(dev);
 461         u32 *push = evo_wait(mast, 8);
 462         if (push) {
 463                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 464                 evo_mthd(push, 0x0084, 1);
 465                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 466                 evo_mthd(push, 0x0080, 2);
 467                 evo_data(push, 0x00000000);
 468                 evo_data(push, 0x00000000);
 469                 evo_kick(push, mast);
 470                 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
 471                         return 0;
 472         }
 473
 474         return -EBUSY;
 475 }
 476
 477 /******************************************************************************
 478  * Page flipping channel
 479  *****************************************************************************/
 480 struct nouveau_bo *
 481 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 482 {
 483         return nv50_disp(dev)->sync;
 484 }
 485
 486 struct nv50_display_flip {
 487         struct nv50_disp *disp;
 488         struct nv50_sync *chan;
 489 };
 490
 491 static bool
 492 nv50_display_flip_wait(void *data)
 493 {
 494         struct nv50_display_flip *flip = data;
 495         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 496                                               flip->chan->data)
 497                 return true;
 498         usleep_range(1, 2);
 499         return false;
 500 }
 501
 502 void
 503 nv50_display_flip_stop(struct drm_crtc *crtc)
 504 {
 505         struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
 506         struct nv50_display_flip flip = {
 507                 .disp = nv50_disp(crtc->dev),
 508                 .chan = nv50_sync(crtc),
 509         };
 510         u32 *push;
 511
 512         push = evo_wait(flip.chan, 8);
 513         if (push) {
 514                 evo_mthd(push, 0x0084, 1);
 515                 evo_data(push, 0x00000000);
 516                 evo_mthd(push, 0x0094, 1);
 517                 evo_data(push, 0x00000000);
 518                 evo_mthd(push, 0x00c0, 1);
 519                 evo_data(push, 0x00000000);
 520                 evo_mthd(push, 0x0080, 1);
 521                 evo_data(push, 0x00000000);
 522                 evo_kick(push, flip.chan);
 523         }
 524
 525         nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
 526 }
 527
 528 int
 529 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 530                        struct nouveau_channel *chan, u32 swap_interval)
 531 {
 532         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 533         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 534         struct nv50_head *head = nv50_head(crtc);
 535         struct nv50_sync *sync = nv50_sync(crtc);
 536         u32 *push;
 537         int ret;
 538
 539         swap_interval <<= 4;
 540         if (swap_interval == 0)
 541                 swap_interval |= 0x100;
 542         if (chan == NULL)
 543                 evo_sync(crtc->dev);
 544
 545         push = evo_wait(sync, 128);
 546         if (unlikely(push == NULL))
 547                 return -EBUSY;
 548
 549         if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
 550                 ret = RING_SPACE(chan, 8);
 551                 if (ret)
 552                         return ret;
 553
 554                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 555                 OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 556                 OUT_RING  (chan, sync->addr ^ 0x10);
 557                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 558                 OUT_RING  (chan, sync->data + 1);
 559                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 560                 OUT_RING  (chan, sync->addr);
 561                 OUT_RING  (chan, sync->data);
 562         } else
 563         if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
 564                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 565                 ret = RING_SPACE(chan, 12);
 566                 if (ret)
 567                         return ret;
 568
 569                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 570                 OUT_RING  (chan, chan->vram.handle);
 571                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 572                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 573                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 574                 OUT_RING  (chan, sync->data + 1);
 575                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 576                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 577                 OUT_RING  (chan, upper_32_bits(addr));
 578                 OUT_RING  (chan, lower_32_bits(addr));
 579                 OUT_RING  (chan, sync->data);
 580                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 581         } else
 582         if (chan) {
 583                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 584                 ret = RING_SPACE(chan, 10);
 585                 if (ret)
 586                         return ret;
 587
 588                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 589                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 590                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 591                 OUT_RING  (chan, sync->data + 1);
 592                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 593                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 594                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 595                 OUT_RING  (chan, upper_32_bits(addr));
 596                 OUT_RING  (chan, lower_32_bits(addr));
 597                 OUT_RING  (chan, sync->data);
 598                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 599                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 600         }
 601
 602         if (chan) {
 603                 sync->addr ^= 0x10;
 604                 sync->data++;
 605                 FIRE_RING (chan);
 606         }
 607
 608         /* queue the flip */
 609         evo_mthd(push, 0x0100, 1);
 610         evo_data(push, 0xfffe0000);
 611         evo_mthd(push, 0x0084, 1);
 612         evo_data(push, swap_interval);
 613         if (!(swap_interval & 0x00000100)) {
 614                 evo_mthd(push, 0x00e0, 1);
 615                 evo_data(push, 0x40000000);
 616         }
 617         evo_mthd(push, 0x0088, 4);
 618         evo_data(push, sync->addr);
 619         evo_data(push, sync->data++);
 620         evo_data(push, sync->data);
 621         evo_data(push, sync->base.sync.handle);
 622         evo_mthd(push, 0x00a0, 2);
 623         evo_data(push, 0x00000000);
 624         evo_data(push, 0x00000000);
 625         evo_mthd(push, 0x00c0, 1);
 626         evo_data(push, nv_fb->r_handle);
 627         evo_mthd(push, 0x0110, 2);
 628         evo_data(push, 0x00000000);
 629         evo_data(push, 0x00000000);
 630         if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
 631                 evo_mthd(push, 0x0800, 5);
 632                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 633                 evo_data(push, 0);
 634                 evo_data(push, (fb->height << 16) | fb->width);
 635                 evo_data(push, nv_fb->r_pitch);
 636                 evo_data(push, nv_fb->r_format);
 637         } else {
 638                 evo_mthd(push, 0x0400, 5);
 639                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 640                 evo_data(push, 0);
 641                 evo_data(push, (fb->height << 16) | fb->width);
 642                 evo_data(push, nv_fb->r_pitch);
 643                 evo_data(push, nv_fb->r_format);
 644         }
 645         evo_mthd(push, 0x0080, 1);
 646         evo_data(push, 0x00000000);
 647         evo_kick(push, sync);
 648
 649         nouveau_bo_ref(nv_fb->nvbo, &head->image);
 650         return 0;
 651 }
 652
 653 /******************************************************************************
 654  * CRTC
 655  *****************************************************************************/
 656 static int
 657 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 658 {
 659         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 660         struct nouveau_connector *nv_connector;
 661         struct drm_connector *connector;
 662         u32 *push, mode = 0x00;
 663
 664         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 665         connector = &nv_connector->base;
 666         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 667                 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
 668                         mode = DITHERING_MODE_DYNAMIC2X2;
 669         } else {
 670                 mode = nv_connector->dithering_mode;
 671         }
 672
 673         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 674                 if (connector->display_info.bpc >= 8)
 675                         mode |= DITHERING_DEPTH_8BPC;
 676         } else {
 677                 mode |= nv_connector->dithering_depth;
 678         }
 679
 680         push = evo_wait(mast, 4);
 681         if (push) {
 682                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 683                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 684                         evo_data(push, mode);
 685                 } else
 686                 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
 687                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 688                         evo_data(push, mode);
 689                 } else {
 690                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 691                         evo_data(push, mode);
 692                 }
 693
 694                 if (update) {
 695                         evo_mthd(push, 0x0080, 1);
 696                         evo_data(push, 0x00000000);
 697                 }
 698                 evo_kick(push, mast);
 699         }
 700
 701         return 0;
 702 }
 703
 704 static int
 705 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 706 {
 707         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 708         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 709         struct drm_crtc *crtc = &nv_crtc->base;
 710         struct nouveau_connector *nv_connector;
 711         int mode = DRM_MODE_SCALE_NONE;
 712         u32 oX, oY, *push;
 713
 714         /* start off at the resolution we programmed the crtc for, this
 715          * effectively handles NONE/FULL scaling
 716          */
 717         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 718         if (nv_connector && nv_connector->native_mode)
 719                 mode = nv_connector->scaling_mode;
 720
 721         if (mode != DRM_MODE_SCALE_NONE)
 722                 omode = nv_connector->native_mode;
 723         else
 724                 omode = umode;
 725
 726         oX = omode->hdisplay;
 727         oY = omode->vdisplay;
 728         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 729                 oY *= 2;
 730
 731         /* add overscan compensation if necessary, will keep the aspect
 732          * ratio the same as the backend mode unless overridden by the
 733          * user setting both hborder and vborder properties.
 734          */
 735         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 736                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 737                               nv_connector->edid &&
 738                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 739                 u32 bX = nv_connector->underscan_hborder;
 740                 u32 bY = nv_connector->underscan_vborder;
 741                 u32 aspect = (oY << 19) / oX;
 742
 743                 if (bX) {
 744                         oX -= (bX * 2);
 745                         if (bY) oY -= (bY * 2);
 746                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 747                 } else {
 748                         oX -= (oX >> 4) + 32;
 749                         if (bY) oY -= (bY * 2);
 750                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 751                 }
 752         }
 753
 754         /* handle CENTER/ASPECT scaling, taking into account the areas
 755          * removed already for overscan compensation
 756          */
 757         switch (mode) {
 758         case DRM_MODE_SCALE_CENTER:
 759                 oX = min((u32)umode->hdisplay, oX);
 760                 oY = min((u32)umode->vdisplay, oY);
 761                 /* fall-through */
 762         case DRM_MODE_SCALE_ASPECT:
 763                 if (oY < oX) {
 764                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 765                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 766                 } else {
 767                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 768                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 769                 }
 770                 break;
 771         default:
 772                 break;
 773         }
 774
 775         push = evo_wait(mast, 8);
 776         if (push) {
 777                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 778                         /*XXX: SCALE_CTRL_ACTIVE??? */
 779                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 780                         evo_data(push, (oY << 16) | oX);
 781                         evo_data(push, (oY << 16) | oX);
 782                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 783                         evo_data(push, 0x00000000);
 784                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 785                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 786                 } else {
 787                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 788                         evo_data(push, (oY << 16) | oX);
 789                         evo_data(push, (oY << 16) | oX);
 790                         evo_data(push, (oY << 16) | oX);
 791                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 792                         evo_data(push, 0x00000000);
 793                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 794                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 795                 }
 796
 797                 evo_kick(push, mast);
 798
 799                 if (update) {
 800                         nv50_display_flip_stop(crtc);
 801                         nv50_display_flip_next(crtc, crtc->primary->fb,
 802                                                NULL, 1);
 803                 }
 804         }
 805
 806         return 0;
 807 }
 808
 809 static int
 810 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 811 {
 812         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 813         u32 *push, hue, vib;
 814         int adj;
 815
 816         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 817         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 818         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 819
 820         push = evo_wait(mast, 16);
 821         if (push) {
 822                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 823                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 824                         evo_data(push, (hue << 20) | (vib << 8));
 825                 } else {
 826                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 827                         evo_data(push, (hue << 20) | (vib << 8));
 828                 }
 829
 830                 if (update) {
 831                         evo_mthd(push, 0x0080, 1);
 832                         evo_data(push, 0x00000000);
 833                 }
 834                 evo_kick(push, mast);
 835         }
 836
 837         return 0;
 838 }
 839
 840 static int
 841 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 842                     int x, int y, bool update)
 843 {
 844         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 845         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 846         u32 *push;
 847
 848         push = evo_wait(mast, 16);
 849         if (push) {
 850                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 851                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 852                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 853                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 854                         evo_data(push, (fb->height << 16) | fb->width);
 855                         evo_data(push, nvfb->r_pitch);
 856                         evo_data(push, nvfb->r_format);
 857                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 858                         evo_data(push, (y << 16) | x);
 859                         if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
 860                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 861                                 evo_data(push, nvfb->r_handle);
 862                         }
 863                 } else {
 864                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 865                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 866                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 867                         evo_data(push, (fb->height << 16) | fb->width);
 868                         evo_data(push, nvfb->r_pitch);
 869                         evo_data(push, nvfb->r_format);
 870                         evo_data(push, nvfb->r_handle);
 871                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 872                         evo_data(push, (y << 16) | x);
 873                 }
 874
 875                 if (update) {
 876                         evo_mthd(push, 0x0080, 1);
 877                         evo_data(push, 0x00000000);
 878                 }
 879                 evo_kick(push, mast);
 880         }
 881
 882         nv_crtc->fb.handle = nvfb->r_handle;
 883         return 0;
 884 }
 885
 886 static void
 887 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 888 {
 889         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 890         u32 *push = evo_wait(mast, 16);
 891         if (push) {
 892                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 893                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 894                         evo_data(push, 0x85000000);
 895                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 896                 } else
 897                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 898                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 899                         evo_data(push, 0x85000000);
 900                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 901                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 902                         evo_data(push, mast->base.vram.handle);
 903                 } else {
 904                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 905                         evo_data(push, 0x85000000);
 906                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 907                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 908                         evo_data(push, mast->base.vram.handle);
 909                 }
 910                 evo_kick(push, mast);
 911         }
 912 }
 913
 914 static void
 915 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 916 {
 917         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 918         u32 *push = evo_wait(mast, 16);
 919         if (push) {
 920                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 921                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 922                         evo_data(push, 0x05000000);
 923                 } else
 924                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 925                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 926                         evo_data(push, 0x05000000);
 927                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 928                         evo_data(push, 0x00000000);
 929                 } else {
 930                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 931                         evo_data(push, 0x05000000);
 932                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 933                         evo_data(push, 0x00000000);
 934                 }
 935                 evo_kick(push, mast);
 936         }
 937 }
 938
 939 static void
 940 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 941 {
 942         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 943
 944         if (show)
 945                 nv50_crtc_cursor_show(nv_crtc);
 946         else
 947                 nv50_crtc_cursor_hide(nv_crtc);
 948
 949         if (update) {
 950                 u32 *push = evo_wait(mast, 2);
 951                 if (push) {
 952                         evo_mthd(push, 0x0080, 1);
 953                         evo_data(push, 0x00000000);
 954                         evo_kick(push, mast);
 955                 }
 956         }
 957 }
 958
 959 static void
 960 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 961 {
 962 }
 963
 964 static void
 965 nv50_crtc_prepare(struct drm_crtc *crtc)
 966 {
 967         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 968         struct nv50_mast *mast = nv50_mast(crtc->dev);
 969         u32 *push;
 970
 971         nv50_display_flip_stop(crtc);
 972
 973         push = evo_wait(mast, 6);
 974         if (push) {
 975                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 976                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 977                         evo_data(push, 0x00000000);
 978                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 979                         evo_data(push, 0x40000000);
 980                 } else
 981                 if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
 982                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 983                         evo_data(push, 0x00000000);
 984                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 985                         evo_data(push, 0x40000000);
 986                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 987                         evo_data(push, 0x00000000);
 988                 } else {
 989                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 990                         evo_data(push, 0x00000000);
 991                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 992                         evo_data(push, 0x03000000);
 993                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 994                         evo_data(push, 0x00000000);
 995                 }
 996
 997                 evo_kick(push, mast);
 998         }
 999
1000         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1001 }
1002
1003 static void
1004 nv50_crtc_commit(struct drm_crtc *crtc)
1005 {
1006         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1007         struct nv50_mast *mast = nv50_mast(crtc->dev);
1008         u32 *push;
1009
1010         push = evo_wait(mast, 32);
1011         if (push) {
1012                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1013                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1014                         evo_data(push, nv_crtc->fb.handle);
1015                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1016                         evo_data(push, 0xc0000000);
1017                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1018                 } else
1019                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1020                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1021                         evo_data(push, nv_crtc->fb.handle);
1022                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1023                         evo_data(push, 0xc0000000);
1024                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1025                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1026                         evo_data(push, mast->base.vram.handle);
1027                 } else {
1028                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1029                         evo_data(push, nv_crtc->fb.handle);
1030                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1031                         evo_data(push, 0x83000000);
1032                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1033                         evo_data(push, 0x00000000);
1034                         evo_data(push, 0x00000000);
1035                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1036                         evo_data(push, mast->base.vram.handle);
1037                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1038                         evo_data(push, 0xffffff00);
1039                 }
1040
1041                 evo_kick(push, mast);
1042         }
1043
1044         nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1045         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1046 }
1047
1048 static bool
1049 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1050                      struct drm_display_mode *adjusted_mode)
1051 {
1052         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1053         return true;
1054 }
1055
1056 static int
1057 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1058 {
1059         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1060         struct nv50_head *head = nv50_head(crtc);
1061         int ret;
1062
1063         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1064         if (ret == 0) {
1065                 if (head->image)
1066                         nouveau_bo_unpin(head->image);
1067                 nouveau_bo_ref(nvfb->nvbo, &head->image);
1068         }
1069
1070         return ret;
1071 }
1072
1073 static int
1074 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1075                    struct drm_display_mode *mode, int x, int y,
1076                    struct drm_framebuffer *old_fb)
1077 {
1078         struct nv50_mast *mast = nv50_mast(crtc->dev);
1079         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1080         struct nouveau_connector *nv_connector;
1081         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1082         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1083         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1084         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1085         u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1086         u32 *push;
1087         int ret;
1088
1089         hactive = mode->htotal;
1090         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1091         hbackp  = mode->htotal - mode->hsync_end;
1092         hblanke = hsynce + hbackp;
1093         hfrontp = mode->hsync_start - mode->hdisplay;
1094         hblanks = mode->htotal - hfrontp - 1;
1095
1096         vactive = mode->vtotal * vscan / ilace;
1097         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1098         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1099         vblanke = vsynce + vbackp;
1100         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1101         vblanks = vactive - vfrontp - 1;
1102         /* XXX: Safe underestimate, even "0" works */
1103         vblankus = (vactive - mode->vdisplay - 2) * hactive;
1104         vblankus *= 1000;
1105         vblankus /= mode->clock;
1106
1107         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1108                 vblan2e = vactive + vsynce + vbackp;
1109                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1110                 vactive = (vactive * 2) + 1;
1111         }
1112
1113         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1114         if (ret)
1115                 return ret;
1116
1117         push = evo_wait(mast, 64);
1118         if (push) {
1119                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1120                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1121                         evo_data(push, 0x00800000 | mode->clock);
1122                         evo_data(push, (ilace == 2) ? 2 : 0);
1123                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 8);
1124                         evo_data(push, 0x00000000);
1125                         evo_data(push, (vactive << 16) | hactive);
1126                         evo_data(push, ( vsynce << 16) | hsynce);
1127                         evo_data(push, (vblanke << 16) | hblanke);
1128                         evo_data(push, (vblanks << 16) | hblanks);
1129                         evo_data(push, (vblan2e << 16) | vblan2s);
1130                         evo_data(push, vblankus);
1131                         evo_data(push, 0x00000000);
1132                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1133                         evo_data(push, 0x00000311);
1134                         evo_data(push, 0x00000100);
1135                 } else {
1136                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1137                         evo_data(push, 0x00000000);
1138                         evo_data(push, (vactive << 16) | hactive);
1139                         evo_data(push, ( vsynce << 16) | hsynce);
1140                         evo_data(push, (vblanke << 16) | hblanke);
1141                         evo_data(push, (vblanks << 16) | hblanks);
1142                         evo_data(push, (vblan2e << 16) | vblan2s);
1143                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1144                         evo_data(push, 0x00000000); /* ??? */
1145                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1146                         evo_data(push, mode->clock * 1000);
1147                         evo_data(push, 0x00200000); /* ??? */
1148                         evo_data(push, mode->clock * 1000);
1149                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1150                         evo_data(push, 0x00000311);
1151                         evo_data(push, 0x00000100);
1152                 }
1153
1154                 evo_kick(push, mast);
1155         }
1156
1157         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1158         nv50_crtc_set_dither(nv_crtc, false);
1159         nv50_crtc_set_scale(nv_crtc, false);
1160         nv50_crtc_set_color_vibrance(nv_crtc, false);
1161         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1162         return 0;
1163 }
1164
1165 static int
1166 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1167                         struct drm_framebuffer *old_fb)
1168 {
1169         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1170         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1171         int ret;
1172
1173         if (!crtc->primary->fb) {
1174                 NV_DEBUG(drm, "No FB bound\n");
1175                 return 0;
1176         }
1177
1178         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1179         if (ret)
1180                 return ret;
1181
1182         nv50_display_flip_stop(crtc);
1183         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1184         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1185         return 0;
1186 }
1187
1188 static int
1189 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1190                                struct drm_framebuffer *fb, int x, int y,
1191                                enum mode_set_atomic state)
1192 {
1193         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1194         nv50_display_flip_stop(crtc);
1195         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1196         return 0;
1197 }
1198
1199 static void
1200 nv50_crtc_lut_load(struct drm_crtc *crtc)
1201 {
1202         struct nv50_disp *disp = nv50_disp(crtc->dev);
1203         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1204         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1205         int i;
1206
1207         for (i = 0; i < 256; i++) {
1208                 u16 r = nv_crtc->lut.r[i] >> 2;
1209                 u16 g = nv_crtc->lut.g[i] >> 2;
1210                 u16 b = nv_crtc->lut.b[i] >> 2;
1211
1212                 if (disp->disp->oclass < GF110_DISP) {
1213                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1214                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1215                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1216                 } else {
1217                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1218                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1219                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1220                 }
1221         }
1222 }
1223
1224 static void
1225 nv50_crtc_disable(struct drm_crtc *crtc)
1226 {
1227         struct nv50_head *head = nv50_head(crtc);
1228         evo_sync(crtc->dev);
1229         if (head->image)
1230                 nouveau_bo_unpin(head->image);
1231         nouveau_bo_ref(NULL, &head->image);
1232 }
1233
1234 static int
1235 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1236                      uint32_t handle, uint32_t width, uint32_t height)
1237 {
1238         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1239         struct drm_device *dev = crtc->dev;
1240         struct drm_gem_object *gem;
1241         struct nouveau_bo *nvbo;
1242         bool visible = (handle != 0);
1243         int i, ret = 0;
1244
1245         if (visible) {
1246                 if (width != 64 || height != 64)
1247                         return -EINVAL;
1248
1249                 gem = drm_gem_object_lookup(dev, file_priv, handle);
1250                 if (unlikely(!gem))
1251                         return -ENOENT;
1252                 nvbo = nouveau_gem_object(gem);
1253
1254                 ret = nouveau_bo_map(nvbo);
1255                 if (ret == 0) {
1256                         for (i = 0; i < 64 * 64; i++) {
1257                                 u32 v = nouveau_bo_rd32(nvbo, i);
1258                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1259                         }
1260                         nouveau_bo_unmap(nvbo);
1261                 }
1262
1263                 drm_gem_object_unreference_unlocked(gem);
1264         }
1265
1266         if (visible != nv_crtc->cursor.visible) {
1267                 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1268                 nv_crtc->cursor.visible = visible;
1269         }
1270
1271         return ret;
1272 }
1273
1274 static int
1275 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1276 {
1277         struct nv50_curs *curs = nv50_curs(crtc);
1278         struct nv50_chan *chan = nv50_chan(curs);
1279         nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1280         nvif_wr32(&chan->user, 0x0080, 0x00000000);
1281         return 0;
1282 }
1283
1284 static void
1285 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1286                     uint32_t start, uint32_t size)
1287 {
1288         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1289         u32 end = min_t(u32, start + size, 256);
1290         u32 i;
1291
1292         for (i = start; i < end; i++) {
1293                 nv_crtc->lut.r[i] = r[i];
1294                 nv_crtc->lut.g[i] = g[i];
1295                 nv_crtc->lut.b[i] = b[i];
1296         }
1297
1298         nv50_crtc_lut_load(crtc);
1299 }
1300
1301 static void
1302 nv50_crtc_destroy(struct drm_crtc *crtc)
1303 {
1304         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1305         struct nv50_disp *disp = nv50_disp(crtc->dev);
1306         struct nv50_head *head = nv50_head(crtc);
1307         struct nv50_fbdma *fbdma;
1308
1309         list_for_each_entry(fbdma, &disp->fbdma, head) {
1310                 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1311         }
1312
1313         nv50_dmac_destroy(&head->ovly.base, disp->disp);
1314         nv50_pioc_destroy(&head->oimm.base);
1315         nv50_dmac_destroy(&head->sync.base, disp->disp);
1316         nv50_pioc_destroy(&head->curs.base);
1317
1318         /*XXX: this shouldn't be necessary, but the core doesn't call
1319          *     disconnect() during the cleanup paths
1320          */
1321         if (head->image)
1322                 nouveau_bo_unpin(head->image);
1323         nouveau_bo_ref(NULL, &head->image);
1324
1325         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1326         if (nv_crtc->cursor.nvbo)
1327                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1328         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1329
1330         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1331         if (nv_crtc->lut.nvbo)
1332                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1333         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1334
1335         drm_crtc_cleanup(crtc);
1336         kfree(crtc);
1337 }
1338
1339 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1340         .dpms = nv50_crtc_dpms,
1341         .prepare = nv50_crtc_prepare,
1342         .commit = nv50_crtc_commit,
1343         .mode_fixup = nv50_crtc_mode_fixup,
1344         .mode_set = nv50_crtc_mode_set,
1345         .mode_set_base = nv50_crtc_mode_set_base,
1346         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1347         .load_lut = nv50_crtc_lut_load,
1348         .disable = nv50_crtc_disable,
1349 };
1350
1351 static const struct drm_crtc_funcs nv50_crtc_func = {
1352         .cursor_set = nv50_crtc_cursor_set,
1353         .cursor_move = nv50_crtc_cursor_move,
1354         .gamma_set = nv50_crtc_gamma_set,
1355         .set_config = nouveau_crtc_set_config,
1356         .destroy = nv50_crtc_destroy,
1357         .page_flip = nouveau_crtc_page_flip,
1358 };
1359
1360 static int
1361 nv50_crtc_create(struct drm_device *dev, int index)
1362 {
1363         struct nv50_disp *disp = nv50_disp(dev);
1364         struct nv50_head *head;
1365         struct drm_crtc *crtc;
1366         int ret, i;
1367
1368         head = kzalloc(sizeof(*head), GFP_KERNEL);
1369         if (!head)
1370                 return -ENOMEM;
1371
1372         head->base.index = index;
1373         head->base.set_dither = nv50_crtc_set_dither;
1374         head->base.set_scale = nv50_crtc_set_scale;
1375         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1376         head->base.color_vibrance = 50;
1377         head->base.vibrant_hue = 0;
1378         for (i = 0; i < 256; i++) {
1379                 head->base.lut.r[i] = i << 8;
1380                 head->base.lut.g[i] = i << 8;
1381                 head->base.lut.b[i] = i << 8;
1382         }
1383
1384         crtc = &head->base.base;
1385         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1386         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1387         drm_mode_crtc_set_gamma_size(crtc, 256);
1388
1389         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1390                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1391         if (!ret) {
1392                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1393                 if (!ret) {
1394                         ret = nouveau_bo_map(head->base.lut.nvbo);
1395                         if (ret)
1396                                 nouveau_bo_unpin(head->base.lut.nvbo);
1397                 }
1398                 if (ret)
1399                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1400         }
1401
1402         if (ret)
1403                 goto out;
1404
1405         nv50_crtc_lut_load(crtc);
1406
1407         /* allocate cursor resources */
1408         ret = nv50_curs_create(disp->disp, index, &head->curs);
1409         if (ret)
1410                 goto out;
1411
1412         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1413                              0, 0x0000, NULL, NULL, &head->base.cursor.nvbo);
1414         if (!ret) {
1415                 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1416                 if (!ret) {
1417                         ret = nouveau_bo_map(head->base.cursor.nvbo);
1418                         if (ret)
1419                                 nouveau_bo_unpin(head->base.lut.nvbo);
1420                 }
1421                 if (ret)
1422                         nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1423         }
1424
1425         if (ret)
1426                 goto out;
1427
1428         /* allocate page flip / sync resources */
1429         ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1430                               &head->sync);
1431         if (ret)
1432                 goto out;
1433
1434         head->sync.addr = EVO_FLIP_SEM0(index);
1435         head->sync.data = 0x00000000;
1436
1437         /* allocate overlay resources */
1438         ret = nv50_oimm_create(disp->disp, index, &head->oimm);
1439         if (ret)
1440                 goto out;
1441
1442         ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1443                               &head->ovly);
1444         if (ret)
1445                 goto out;
1446
1447 out:
1448         if (ret)
1449                 nv50_crtc_destroy(crtc);
1450         return ret;
1451 }
1452
1453 /******************************************************************************
1454  * DAC
1455  *****************************************************************************/
1456 static void
1457 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1458 {
1459         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1460         struct nv50_disp *disp = nv50_disp(encoder->dev);
1461         struct {
1462                 struct nv50_disp_mthd_v1 base;
1463                 struct nv50_disp_dac_pwr_v0 pwr;
1464         } args = {
1465                 .base.version = 1,
1466                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1467                 .base.hasht  = nv_encoder->dcb->hasht,
1468                 .base.hashm  = nv_encoder->dcb->hashm,
1469                 .pwr.state = 1,
1470                 .pwr.data  = 1,
1471                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1472                               mode != DRM_MODE_DPMS_OFF),
1473                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1474                               mode != DRM_MODE_DPMS_OFF),
1475         };
1476
1477         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1478 }
1479
1480 static bool
1481 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1482                     const struct drm_display_mode *mode,
1483                     struct drm_display_mode *adjusted_mode)
1484 {
1485         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1486         struct nouveau_connector *nv_connector;
1487
1488         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1489         if (nv_connector && nv_connector->native_mode) {
1490                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1491                         int id = adjusted_mode->base.id;
1492                         *adjusted_mode = *nv_connector->native_mode;
1493                         adjusted_mode->base.id = id;
1494                 }
1495         }
1496
1497         return true;
1498 }
1499
1500 static void
1501 nv50_dac_commit(struct drm_encoder *encoder)
1502 {
1503 }
1504
1505 static void
1506 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1507                   struct drm_display_mode *adjusted_mode)
1508 {
1509         struct nv50_mast *mast = nv50_mast(encoder->dev);
1510         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1511         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1512         u32 *push;
1513
1514         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1515
1516         push = evo_wait(mast, 8);
1517         if (push) {
1518                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1519                         u32 syncs = 0x00000000;
1520
1521                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1522                                 syncs |= 0x00000001;
1523                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1524                                 syncs |= 0x00000002;
1525
1526                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1527                         evo_data(push, 1 << nv_crtc->index);
1528                         evo_data(push, syncs);
1529                 } else {
1530                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1531                         u32 syncs = 0x00000001;
1532
1533                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1534                                 syncs |= 0x00000008;
1535                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1536                                 syncs |= 0x00000010;
1537
1538                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1539                                 magic |= 0x00000001;
1540
1541                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1542                         evo_data(push, syncs);
1543                         evo_data(push, magic);
1544                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1545                         evo_data(push, 1 << nv_crtc->index);
1546                 }
1547
1548                 evo_kick(push, mast);
1549         }
1550
1551         nv_encoder->crtc = encoder->crtc;
1552 }
1553
1554 static void
1555 nv50_dac_disconnect(struct drm_encoder *encoder)
1556 {
1557         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1558         struct nv50_mast *mast = nv50_mast(encoder->dev);
1559         const int or = nv_encoder->or;
1560         u32 *push;
1561
1562         if (nv_encoder->crtc) {
1563                 nv50_crtc_prepare(nv_encoder->crtc);
1564
1565                 push = evo_wait(mast, 4);
1566                 if (push) {
1567                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1568                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1569                                 evo_data(push, 0x00000000);
1570                         } else {
1571                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1572                                 evo_data(push, 0x00000000);
1573                         }
1574                         evo_kick(push, mast);
1575                 }
1576         }
1577
1578         nv_encoder->crtc = NULL;
1579 }
1580
1581 static enum drm_connector_status
1582 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1583 {
1584         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1585         struct nv50_disp *disp = nv50_disp(encoder->dev);
1586         struct {
1587                 struct nv50_disp_mthd_v1 base;
1588                 struct nv50_disp_dac_load_v0 load;
1589         } args = {
1590                 .base.version = 1,
1591                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1592                 .base.hasht  = nv_encoder->dcb->hasht,
1593                 .base.hashm  = nv_encoder->dcb->hashm,
1594         };
1595         int ret;
1596
1597         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1598         if (args.load.data == 0)
1599                 args.load.data = 340;
1600
1601         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1602         if (ret || !args.load.load)
1603                 return connector_status_disconnected;
1604
1605         return connector_status_connected;
1606 }
1607
1608 static void
1609 nv50_dac_destroy(struct drm_encoder *encoder)
1610 {
1611         drm_encoder_cleanup(encoder);
1612         kfree(encoder);
1613 }
1614
1615 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1616         .dpms = nv50_dac_dpms,
1617         .mode_fixup = nv50_dac_mode_fixup,
1618         .prepare = nv50_dac_disconnect,
1619         .commit = nv50_dac_commit,
1620         .mode_set = nv50_dac_mode_set,
1621         .disable = nv50_dac_disconnect,
1622         .get_crtc = nv50_display_crtc_get,
1623         .detect = nv50_dac_detect
1624 };
1625
1626 static const struct drm_encoder_funcs nv50_dac_func = {
1627         .destroy = nv50_dac_destroy,
1628 };
1629
1630 static int
1631 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1632 {
1633         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1634         struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
1635         struct nouveau_encoder *nv_encoder;
1636         struct drm_encoder *encoder;
1637         int type = DRM_MODE_ENCODER_DAC;
1638
1639         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1640         if (!nv_encoder)
1641                 return -ENOMEM;
1642         nv_encoder->dcb = dcbe;
1643         nv_encoder->or = ffs(dcbe->or) - 1;
1644         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1645
1646         encoder = to_drm_encoder(nv_encoder);
1647         encoder->possible_crtcs = dcbe->heads;
1648         encoder->possible_clones = 0;
1649         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1650         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1651
1652         drm_mode_connector_attach_encoder(connector, encoder);
1653         return 0;
1654 }
1655
1656 /******************************************************************************
1657  * Audio
1658  *****************************************************************************/
1659 static void
1660 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1661 {
1662         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1663         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1664         struct nouveau_connector *nv_connector;
1665         struct nv50_disp *disp = nv50_disp(encoder->dev);
1666         struct __packed {
1667                 struct {
1668                         struct nv50_disp_mthd_v1 mthd;
1669                         struct nv50_disp_sor_hda_eld_v0 eld;
1670                 } base;
1671                 u8 data[sizeof(nv_connector->base.eld)];
1672         } args = {
1673                 .base.mthd.version = 1,
1674                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1675                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
1676                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1677                                      (0x0100 << nv_crtc->index),
1678         };
1679
1680         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1681         if (!drm_detect_monitor_audio(nv_connector->edid))
1682                 return;
1683
1684         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1685         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1686
1687         nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4);
1688 }
1689
1690 static void
1691 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1692 {
1693         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1694         struct nv50_disp *disp = nv50_disp(encoder->dev);
1695         struct {
1696                 struct nv50_disp_mthd_v1 base;
1697                 struct nv50_disp_sor_hda_eld_v0 eld;
1698         } args = {
1699                 .base.version = 1,
1700                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1701                 .base.hasht   = nv_encoder->dcb->hasht,
1702                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1703                                 (0x0100 << nv_crtc->index),
1704         };
1705
1706         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1707 }
1708
1709 /******************************************************************************
1710  * HDMI
1711  *****************************************************************************/
1712 static void
1713 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1714 {
1715         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1716         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1717         struct nv50_disp *disp = nv50_disp(encoder->dev);
1718         struct {
1719                 struct nv50_disp_mthd_v1 base;
1720                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1721         } args = {
1722                 .base.version = 1,
1723                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1724                 .base.hasht  = nv_encoder->dcb->hasht,
1725                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1726                                (0x0100 << nv_crtc->index),
1727                 .pwr.state = 1,
1728                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1729         };
1730         struct nouveau_connector *nv_connector;
1731         u32 max_ac_packet;
1732
1733         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1734         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1735                 return;
1736
1737         max_ac_packet  = mode->htotal - mode->hdisplay;
1738         max_ac_packet -= args.pwr.rekey;
1739         max_ac_packet -= 18; /* constant from tegra */
1740         args.pwr.max_ac_packet = max_ac_packet / 32;
1741
1742         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1743         nv50_audio_mode_set(encoder, mode);
1744 }
1745
1746 static void
1747 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1748 {
1749         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1750         struct nv50_disp *disp = nv50_disp(encoder->dev);
1751         struct {
1752                 struct nv50_disp_mthd_v1 base;
1753                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1754         } args = {
1755                 .base.version = 1,
1756                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1757                 .base.hasht  = nv_encoder->dcb->hasht,
1758                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1759                                (0x0100 << nv_crtc->index),
1760         };
1761
1762         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1763 }
1764
1765 /******************************************************************************
1766  * SOR
1767  *****************************************************************************/
1768 static void
1769 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1770 {
1771         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1772         struct nv50_disp *disp = nv50_disp(encoder->dev);
1773         struct {
1774                 struct nv50_disp_mthd_v1 base;
1775                 struct nv50_disp_sor_pwr_v0 pwr;
1776         } args = {
1777                 .base.version = 1,
1778                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1779                 .base.hasht  = nv_encoder->dcb->hasht,
1780                 .base.hashm  = nv_encoder->dcb->hashm,
1781                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1782         };
1783         struct {
1784                 struct nv50_disp_mthd_v1 base;
1785                 struct nv50_disp_sor_dp_pwr_v0 pwr;
1786         } link = {
1787                 .base.version = 1,
1788                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1789                 .base.hasht  = nv_encoder->dcb->hasht,
1790                 .base.hashm  = nv_encoder->dcb->hashm,
1791                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1792         };
1793         struct drm_device *dev = encoder->dev;
1794         struct drm_encoder *partner;
1795
1796         nv_encoder->last_dpms = mode;
1797
1798         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1799                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1800
1801                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1802                         continue;
1803
1804                 if (nv_partner != nv_encoder &&
1805                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1806                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1807                                 return;
1808                         break;
1809                 }
1810         }
1811
1812         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1813                 args.pwr.state = 1;
1814                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1815                 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1816         } else {
1817                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1818         }
1819 }
1820
1821 static bool
1822 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1823                     const struct drm_display_mode *mode,
1824                     struct drm_display_mode *adjusted_mode)
1825 {
1826         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1827         struct nouveau_connector *nv_connector;
1828
1829         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1830         if (nv_connector && nv_connector->native_mode) {
1831                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1832                         int id = adjusted_mode->base.id;
1833                         *adjusted_mode = *nv_connector->native_mode;
1834                         adjusted_mode->base.id = id;
1835                 }
1836         }
1837
1838         return true;
1839 }
1840
1841 static void
1842 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1843 {
1844         struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1845         u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1846         if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1847                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1848                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1849                         evo_data(push, (nv_encoder->ctrl = temp));
1850                 } else {
1851                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1852                         evo_data(push, (nv_encoder->ctrl = temp));
1853                 }
1854                 evo_kick(push, mast);
1855         }
1856 }
1857
1858 static void
1859 nv50_sor_disconnect(struct drm_encoder *encoder)
1860 {
1861         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1862         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1863
1864         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1865         nv_encoder->crtc = NULL;
1866
1867         if (nv_crtc) {
1868                 nv50_crtc_prepare(&nv_crtc->base);
1869                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1870                 nv50_audio_disconnect(encoder, nv_crtc);
1871                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1872         }
1873 }
1874
1875 static void
1876 nv50_sor_commit(struct drm_encoder *encoder)
1877 {
1878 }
1879
1880 static void
1881 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1882                   struct drm_display_mode *mode)
1883 {
1884         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1885         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1886         struct {
1887                 struct nv50_disp_mthd_v1 base;
1888                 struct nv50_disp_sor_lvds_script_v0 lvds;
1889         } lvds = {
1890                 .base.version = 1,
1891                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1892                 .base.hasht   = nv_encoder->dcb->hasht,
1893                 .base.hashm   = nv_encoder->dcb->hashm,
1894         };
1895         struct nv50_disp *disp = nv50_disp(encoder->dev);
1896         struct nv50_mast *mast = nv50_mast(encoder->dev);
1897         struct drm_device *dev = encoder->dev;
1898         struct nouveau_drm *drm = nouveau_drm(dev);
1899         struct nouveau_connector *nv_connector;
1900         struct nvbios *bios = &drm->vbios;
1901         u32 mask, ctrl;
1902         u8 owner = 1 << nv_crtc->index;
1903         u8 proto = 0xf;
1904         u8 depth = 0x0;
1905
1906         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1907         nv_encoder->crtc = encoder->crtc;
1908
1909         switch (nv_encoder->dcb->type) {
1910         case DCB_OUTPUT_TMDS:
1911                 if (nv_encoder->dcb->sorconf.link & 1) {
1912                         if (mode->clock < 165000)
1913                                 proto = 0x1;
1914                         else
1915                                 proto = 0x5;
1916                 } else {
1917                         proto = 0x2;
1918                 }
1919
1920                 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1921                 break;
1922         case DCB_OUTPUT_LVDS:
1923                 proto = 0x0;
1924
1925                 if (bios->fp_no_ddc) {
1926                         if (bios->fp.dual_link)
1927                                 lvds.lvds.script |= 0x0100;
1928                         if (bios->fp.if_is_24bit)
1929                                 lvds.lvds.script |= 0x0200;
1930                 } else {
1931                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1932                                 if (((u8 *)nv_connector->edid)[121] == 2)
1933                                         lvds.lvds.script |= 0x0100;
1934                         } else
1935                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1936                                 lvds.lvds.script |= 0x0100;
1937                         }
1938
1939                         if (lvds.lvds.script & 0x0100) {
1940                                 if (bios->fp.strapless_is_24bit & 2)
1941                                         lvds.lvds.script |= 0x0200;
1942                         } else {
1943                                 if (bios->fp.strapless_is_24bit & 1)
1944                                         lvds.lvds.script |= 0x0200;
1945                         }
1946
1947                         if (nv_connector->base.display_info.bpc == 8)
1948                                 lvds.lvds.script |= 0x0200;
1949                 }
1950
1951                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
1952                 break;
1953         case DCB_OUTPUT_DP:
1954                 if (nv_connector->base.display_info.bpc == 6) {
1955                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1956                         depth = 0x2;
1957                 } else
1958                 if (nv_connector->base.display_info.bpc == 8) {
1959                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1960                         depth = 0x5;
1961                 } else {
1962                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
1963                         depth = 0x6;
1964                 }
1965
1966                 if (nv_encoder->dcb->sorconf.link & 1)
1967                         proto = 0x8;
1968                 else
1969                         proto = 0x9;
1970                 nv50_audio_mode_set(encoder, mode);
1971                 break;
1972         default:
1973                 BUG_ON(1);
1974                 break;
1975         }
1976
1977         nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
1978
1979         if (nv50_vers(mast) >= GF110_DISP) {
1980                 u32 *push = evo_wait(mast, 3);
1981                 if (push) {
1982                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1983                         u32 syncs = 0x00000001;
1984
1985                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1986                                 syncs |= 0x00000008;
1987                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1988                                 syncs |= 0x00000010;
1989
1990                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1991                                 magic |= 0x00000001;
1992
1993                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1994                         evo_data(push, syncs | (depth << 6));
1995                         evo_data(push, magic);
1996                         evo_kick(push, mast);
1997                 }
1998
1999                 ctrl = proto << 8;
2000                 mask = 0x00000f00;
2001         } else {
2002                 ctrl = (depth << 16) | (proto << 8);
2003                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2004                         ctrl |= 0x00001000;
2005                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2006                         ctrl |= 0x00002000;
2007                 mask = 0x000f3f00;
2008         }
2009
2010         nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2011 }
2012
2013 static void
2014 nv50_sor_destroy(struct drm_encoder *encoder)
2015 {
2016         drm_encoder_cleanup(encoder);
2017         kfree(encoder);
2018 }
2019
2020 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2021         .dpms = nv50_sor_dpms,
2022         .mode_fixup = nv50_sor_mode_fixup,
2023         .prepare = nv50_sor_disconnect,
2024         .commit = nv50_sor_commit,
2025         .mode_set = nv50_sor_mode_set,
2026         .disable = nv50_sor_disconnect,
2027         .get_crtc = nv50_display_crtc_get,
2028 };
2029
2030 static const struct drm_encoder_funcs nv50_sor_func = {
2031         .destroy = nv50_sor_destroy,
2032 };
2033
2034 static int
2035 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2036 {
2037         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2038         struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2039         struct nouveau_encoder *nv_encoder;
2040         struct drm_encoder *encoder;
2041         int type;
2042
2043         switch (dcbe->type) {
2044         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2045         case DCB_OUTPUT_TMDS:
2046         case DCB_OUTPUT_DP:
2047         default:
2048                 type = DRM_MODE_ENCODER_TMDS;
2049                 break;
2050         }
2051
2052         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2053         if (!nv_encoder)
2054                 return -ENOMEM;
2055         nv_encoder->dcb = dcbe;
2056         nv_encoder->or = ffs(dcbe->or) - 1;
2057         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
2058         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2059
2060         encoder = to_drm_encoder(nv_encoder);
2061         encoder->possible_crtcs = dcbe->heads;
2062         encoder->possible_clones = 0;
2063         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
2064         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2065
2066         drm_mode_connector_attach_encoder(connector, encoder);
2067         return 0;
2068 }
2069
2070 /******************************************************************************
2071  * PIOR
2072  *****************************************************************************/
2073
2074 static void
2075 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2076 {
2077         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2078         struct nv50_disp *disp = nv50_disp(encoder->dev);
2079         struct {
2080                 struct nv50_disp_mthd_v1 base;
2081                 struct nv50_disp_pior_pwr_v0 pwr;
2082         } args = {
2083                 .base.version = 1,
2084                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2085                 .base.hasht  = nv_encoder->dcb->hasht,
2086                 .base.hashm  = nv_encoder->dcb->hashm,
2087                 .pwr.state = mode == DRM_MODE_DPMS_ON,
2088                 .pwr.type = nv_encoder->dcb->type,
2089         };
2090
2091         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2092 }
2093
2094 static bool
2095 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2096                      const struct drm_display_mode *mode,
2097                      struct drm_display_mode *adjusted_mode)
2098 {
2099         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2100         struct nouveau_connector *nv_connector;
2101
2102         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2103         if (nv_connector && nv_connector->native_mode) {
2104                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2105                         int id = adjusted_mode->base.id;
2106                         *adjusted_mode = *nv_connector->native_mode;
2107                         adjusted_mode->base.id = id;
2108                 }
2109         }
2110
2111         adjusted_mode->clock *= 2;
2112         return true;
2113 }
2114
2115 static void
2116 nv50_pior_commit(struct drm_encoder *encoder)
2117 {
2118 }
2119
2120 static void
2121 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2122                    struct drm_display_mode *adjusted_mode)
2123 {
2124         struct nv50_mast *mast = nv50_mast(encoder->dev);
2125         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2126         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2127         struct nouveau_connector *nv_connector;
2128         u8 owner = 1 << nv_crtc->index;
2129         u8 proto, depth;
2130         u32 *push;
2131
2132         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2133         switch (nv_connector->base.display_info.bpc) {
2134         case 10: depth = 0x6; break;
2135         case  8: depth = 0x5; break;
2136         case  6: depth = 0x2; break;
2137         default: depth = 0x0; break;
2138         }
2139
2140         switch (nv_encoder->dcb->type) {
2141         case DCB_OUTPUT_TMDS:
2142         case DCB_OUTPUT_DP:
2143                 proto = 0x0;
2144                 break;
2145         default:
2146                 BUG_ON(1);
2147                 break;
2148         }
2149
2150         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2151
2152         push = evo_wait(mast, 8);
2153         if (push) {
2154                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2155                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2156                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2157                                 ctrl |= 0x00001000;
2158                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2159                                 ctrl |= 0x00002000;
2160                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2161                         evo_data(push, ctrl);
2162                 }
2163
2164                 evo_kick(push, mast);
2165         }
2166
2167         nv_encoder->crtc = encoder->crtc;
2168 }
2169
2170 static void
2171 nv50_pior_disconnect(struct drm_encoder *encoder)
2172 {
2173         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2174         struct nv50_mast *mast = nv50_mast(encoder->dev);
2175         const int or = nv_encoder->or;
2176         u32 *push;
2177
2178         if (nv_encoder->crtc) {
2179                 nv50_crtc_prepare(nv_encoder->crtc);
2180
2181                 push = evo_wait(mast, 4);
2182                 if (push) {
2183                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2184                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2185                                 evo_data(push, 0x00000000);
2186                         }
2187                         evo_kick(push, mast);
2188                 }
2189         }
2190
2191         nv_encoder->crtc = NULL;
2192 }
2193
2194 static void
2195 nv50_pior_destroy(struct drm_encoder *encoder)
2196 {
2197         drm_encoder_cleanup(encoder);
2198         kfree(encoder);
2199 }
2200
2201 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2202         .dpms = nv50_pior_dpms,
2203         .mode_fixup = nv50_pior_mode_fixup,
2204         .prepare = nv50_pior_disconnect,
2205         .commit = nv50_pior_commit,
2206         .mode_set = nv50_pior_mode_set,
2207         .disable = nv50_pior_disconnect,
2208         .get_crtc = nv50_display_crtc_get,
2209 };
2210
2211 static const struct drm_encoder_funcs nv50_pior_func = {
2212         .destroy = nv50_pior_destroy,
2213 };
2214
2215 static int
2216 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2217 {
2218         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2219         struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2220         struct nouveau_i2c_port *ddc = NULL;
2221         struct nouveau_encoder *nv_encoder;
2222         struct drm_encoder *encoder;
2223         int type;
2224
2225         switch (dcbe->type) {
2226         case DCB_OUTPUT_TMDS:
2227                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2228                 type = DRM_MODE_ENCODER_TMDS;
2229                 break;
2230         case DCB_OUTPUT_DP:
2231                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2232                 type = DRM_MODE_ENCODER_TMDS;
2233                 break;
2234         default:
2235                 return -ENODEV;
2236         }
2237
2238         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2239         if (!nv_encoder)
2240                 return -ENOMEM;
2241         nv_encoder->dcb = dcbe;
2242         nv_encoder->or = ffs(dcbe->or) - 1;
2243         nv_encoder->i2c = ddc;
2244
2245         encoder = to_drm_encoder(nv_encoder);
2246         encoder->possible_crtcs = dcbe->heads;
2247         encoder->possible_clones = 0;
2248         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2249         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2250
2251         drm_mode_connector_attach_encoder(connector, encoder);
2252         return 0;
2253 }
2254
2255 /******************************************************************************
2256  * Framebuffer
2257  *****************************************************************************/
2258
2259 static void
2260 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2261 {
2262         int i;
2263         for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2264                 nvif_object_fini(&fbdma->base[i]);
2265         nvif_object_fini(&fbdma->core);
2266         list_del(&fbdma->head);
2267         kfree(fbdma);
2268 }
2269
2270 static int
2271 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2272 {
2273         struct nouveau_drm *drm = nouveau_drm(dev);
2274         struct nv50_disp *disp = nv50_disp(dev);
2275         struct nv50_mast *mast = nv50_mast(dev);
2276         struct __attribute__ ((packed)) {
2277                 struct nv_dma_v0 base;
2278                 union {
2279                         struct nv50_dma_v0 nv50;
2280                         struct gf100_dma_v0 gf100;
2281                         struct gf110_dma_v0 gf110;
2282                 };
2283         } args = {};
2284         struct nv50_fbdma *fbdma;
2285         struct drm_crtc *crtc;
2286         u32 size = sizeof(args.base);
2287         int ret;
2288
2289         list_for_each_entry(fbdma, &disp->fbdma, head) {
2290                 if (fbdma->core.handle == name)
2291                         return 0;
2292         }
2293
2294         fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2295         if (!fbdma)
2296                 return -ENOMEM;
2297         list_add(&fbdma->head, &disp->fbdma);
2298
2299         args.base.target = NV_DMA_V0_TARGET_VRAM;
2300         args.base.access = NV_DMA_V0_ACCESS_RDWR;
2301         args.base.start = offset;
2302         args.base.limit = offset + length - 1;
2303
2304         if (drm->device.info.chipset < 0x80) {
2305                 args.nv50.part = NV50_DMA_V0_PART_256;
2306                 size += sizeof(args.nv50);
2307         } else
2308         if (drm->device.info.chipset < 0xc0) {
2309                 args.nv50.part = NV50_DMA_V0_PART_256;
2310                 args.nv50.kind = kind;
2311                 size += sizeof(args.nv50);
2312         } else
2313         if (drm->device.info.chipset < 0xd0) {
2314                 args.gf100.kind = kind;
2315                 size += sizeof(args.gf100);
2316         } else {
2317                 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2318                 args.gf110.kind = kind;
2319                 size += sizeof(args.gf110);
2320         }
2321
2322         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2323                 struct nv50_head *head = nv50_head(crtc);
2324                 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
2325                                             name, NV_DMA_IN_MEMORY, &args, size,
2326                                            &fbdma->base[head->base.index]);
2327                 if (ret) {
2328                         nv50_fbdma_fini(fbdma);
2329                         return ret;
2330                 }
2331         }
2332
2333         ret = nvif_object_init(&mast->base.base.user, NULL, name,
2334                                 NV_DMA_IN_MEMORY, &args, size,
2335                                &fbdma->core);
2336         if (ret) {
2337                 nv50_fbdma_fini(fbdma);
2338                 return ret;
2339         }
2340
2341         return 0;
2342 }
2343
2344 static void
2345 nv50_fb_dtor(struct drm_framebuffer *fb)
2346 {
2347 }
2348
2349 static int
2350 nv50_fb_ctor(struct drm_framebuffer *fb)
2351 {
2352         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2353         struct nouveau_drm *drm = nouveau_drm(fb->dev);
2354         struct nouveau_bo *nvbo = nv_fb->nvbo;
2355         struct nv50_disp *disp = nv50_disp(fb->dev);
2356         u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2357         u8 tile = nvbo->tile_mode;
2358
2359         if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
2360                 NV_ERROR(drm, "framebuffer requires contiguous bo\n");
2361                 return -EINVAL;
2362         }
2363
2364         if (drm->device.info.chipset >= 0xc0)
2365                 tile >>= 4; /* yep.. */
2366
2367         switch (fb->depth) {
2368         case  8: nv_fb->r_format = 0x1e00; break;
2369         case 15: nv_fb->r_format = 0xe900; break;
2370         case 16: nv_fb->r_format = 0xe800; break;
2371         case 24:
2372         case 32: nv_fb->r_format = 0xcf00; break;
2373         case 30: nv_fb->r_format = 0xd100; break;
2374         default:
2375                  NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2376                  return -EINVAL;
2377         }
2378
2379         if (disp->disp->oclass < G82_DISP) {
2380                 nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2381                                             (fb->pitches[0] | 0x00100000);
2382                 nv_fb->r_format |= kind << 16;
2383         } else
2384         if (disp->disp->oclass < GF110_DISP) {
2385                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2386                                            (fb->pitches[0] | 0x00100000);
2387         } else {
2388                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2389                                            (fb->pitches[0] | 0x01000000);
2390         }
2391         nv_fb->r_handle = 0xffff0000 | kind;
2392
2393         return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2394                                drm->device.info.ram_user, kind);
2395 }
2396
2397 /******************************************************************************
2398  * Init
2399  *****************************************************************************/
2400
2401 void
2402 nv50_display_fini(struct drm_device *dev)
2403 {
2404 }
2405
2406 int
2407 nv50_display_init(struct drm_device *dev)
2408 {
2409         struct nv50_disp *disp = nv50_disp(dev);
2410         struct drm_crtc *crtc;
2411         u32 *push;
2412
2413         push = evo_wait(nv50_mast(dev), 32);
2414         if (!push)
2415                 return -EBUSY;
2416
2417         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2418                 struct nv50_sync *sync = nv50_sync(crtc);
2419                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2420         }
2421
2422         evo_mthd(push, 0x0088, 1);
2423         evo_data(push, nv50_mast(dev)->base.sync.handle);
2424         evo_kick(push, nv50_mast(dev));
2425         return 0;
2426 }
2427
2428 void
2429 nv50_display_destroy(struct drm_device *dev)
2430 {
2431         struct nv50_disp *disp = nv50_disp(dev);
2432         struct nv50_fbdma *fbdma, *fbtmp;
2433
2434         list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2435                 nv50_fbdma_fini(fbdma);
2436         }
2437
2438         nv50_dmac_destroy(&disp->mast.base, disp->disp);
2439
2440         nouveau_bo_unmap(disp->sync);
2441         if (disp->sync)
2442                 nouveau_bo_unpin(disp->sync);
2443         nouveau_bo_ref(NULL, &disp->sync);
2444
2445         nouveau_display(dev)->priv = NULL;
2446         kfree(disp);
2447 }
2448
2449 int
2450 nv50_display_create(struct drm_device *dev)
2451 {
2452         struct nvif_device *device = &nouveau_drm(dev)->device;
2453         struct nouveau_drm *drm = nouveau_drm(dev);
2454         struct dcb_table *dcb = &drm->vbios.dcb;
2455         struct drm_connector *connector, *tmp;
2456         struct nv50_disp *disp;
2457         struct dcb_output *dcbe;
2458         int crtcs, ret, i;
2459
2460         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2461         if (!disp)
2462                 return -ENOMEM;
2463         INIT_LIST_HEAD(&disp->fbdma);
2464
2465         nouveau_display(dev)->priv = disp;
2466         nouveau_display(dev)->dtor = nv50_display_destroy;
2467         nouveau_display(dev)->init = nv50_display_init;
2468         nouveau_display(dev)->fini = nv50_display_fini;
2469         nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2470         nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2471         disp->disp = &nouveau_display(dev)->disp;
2472
2473         /* small shared memory area we use for notifiers and semaphores */
2474         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2475                              0, 0x0000, NULL, NULL, &disp->sync);
2476         if (!ret) {
2477                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2478                 if (!ret) {
2479                         ret = nouveau_bo_map(disp->sync);
2480                         if (ret)
2481                                 nouveau_bo_unpin(disp->sync);
2482                 }
2483                 if (ret)
2484                         nouveau_bo_ref(NULL, &disp->sync);
2485         }
2486
2487         if (ret)
2488                 goto out;
2489
2490         /* allocate master evo channel */
2491         ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2492                               &disp->mast);
2493         if (ret)
2494                 goto out;
2495
2496         /* create crtc objects to represent the hw heads */
2497         if (disp->disp->oclass >= GF110_DISP)
2498                 crtcs = nvif_rd32(device, 0x022448);
2499         else
2500                 crtcs = 2;
2501
2502         for (i = 0; i < crtcs; i++) {
2503                 ret = nv50_crtc_create(dev, i);
2504                 if (ret)
2505                         goto out;
2506         }
2507
2508         /* create encoder/connector objects based on VBIOS DCB table */
2509         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2510                 connector = nouveau_connector_create(dev, dcbe->connector);
2511                 if (IS_ERR(connector))
2512                         continue;
2513
2514                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2515                         switch (dcbe->type) {
2516                         case DCB_OUTPUT_TMDS:
2517                         case DCB_OUTPUT_LVDS:
2518                         case DCB_OUTPUT_DP:
2519                                 ret = nv50_sor_create(connector, dcbe);
2520                                 break;
2521                         case DCB_OUTPUT_ANALOG:
2522                                 ret = nv50_dac_create(connector, dcbe);
2523                                 break;
2524                         default:
2525                                 ret = -ENODEV;
2526                                 break;
2527                         }
2528                 } else {
2529                         ret = nv50_pior_create(connector, dcbe);
2530                 }
2531
2532                 if (ret) {
2533                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2534                                      dcbe->location, dcbe->type,
2535                                      ffs(dcbe->or) - 1, ret);
2536                         ret = 0;
2537                 }
2538         }
2539
2540         /* cull any connectors we created that don't have an encoder */
2541         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2542                 if (connector->encoder_ids[0])
2543                         continue;
2544
2545                 NV_WARN(drm, "%s has no encoders, removing\n",
2546                         connector->name);
2547                 connector->funcs->destroy(connector);
2548         }
2549
2550 out:
2551         if (ret)
2552                 nv50_display_destroy(dev);
2553         return ret;
2554 }