drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_fb_helper.h>
  32
  33 #include <nvif/class.h>
  34
  35 #include "nouveau_drm.h"
  36 #include "nouveau_dma.h"
  37 #include "nouveau_gem.h"
  38 #include "nouveau_connector.h"
  39 #include "nouveau_encoder.h"
  40 #include "nouveau_crtc.h"
  41 #include "nouveau_fence.h"
  42 #include "nv50_display.h"
  43
  44 #define EVO_DMA_NR 9
  45
  46 #define EVO_MASTER  (0x00)
  47 #define EVO_FLIP(c) (0x01 + (c))
  48 #define EVO_OVLY(c) (0x05 + (c))
  49 #define EVO_OIMM(c) (0x09 + (c))
  50 #define EVO_CURS(c) (0x0d + (c))
  51
  52 /* offsets in shared sync bo of various structures */
  53 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  54 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  55 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  56 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  57
  58 /******************************************************************************
  59  * EVO channel
  60  *****************************************************************************/
  61
  62 struct nv50_chan {
  63         struct nvif_object user;
  64         struct nvif_device *device;
  65 };
  66
  67 static int
  68 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  69                  const s32 *oclass, u8 head, void *data, u32 size,
  70                  struct nv50_chan *chan)
  71 {
  72         struct nvif_sclass *sclass;
  73         int ret, i, n;
  74
  75         chan->device = device;
  76
  77         ret = n = nvif_object_sclass_get(disp, &sclass);
  78         if (ret < 0)
  79                 return ret;
  80
  81         while (oclass[0]) {
  82                 for (i = 0; i < n; i++) {
  83                         if (sclass[i].oclass == oclass[0]) {
  84                                 ret = nvif_object_init(disp, 0, oclass[0],
  85                                                        data, size, &chan->user);
  86                                 if (ret == 0)
  87                                         nvif_object_map(&chan->user);
  88                                 nvif_object_sclass_put(&sclass);
  89                                 return ret;
  90                         }
  91                 }
  92                 oclass++;
  93         }
  94
  95         nvif_object_sclass_put(&sclass);
  96         return -ENOSYS;
  97 }
  98
  99 static void
 100 nv50_chan_destroy(struct nv50_chan *chan)
 101 {
 102         nvif_object_fini(&chan->user);
 103 }
 104
 105 /******************************************************************************
 106  * PIO EVO channel
 107  *****************************************************************************/
 108
 109 struct nv50_pioc {
 110         struct nv50_chan base;
 111 };
 112
 113 static void
 114 nv50_pioc_destroy(struct nv50_pioc *pioc)
 115 {
 116         nv50_chan_destroy(&pioc->base);
 117 }
 118
 119 static int
 120 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 121                  const s32 *oclass, u8 head, void *data, u32 size,
 122                  struct nv50_pioc *pioc)
 123 {
 124         return nv50_chan_create(device, disp, oclass, head, data, size,
 125                                 &pioc->base);
 126 }
 127
 128 /******************************************************************************
 129  * Cursor Immediate
 130  *****************************************************************************/
 131
 132 struct nv50_curs {
 133         struct nv50_pioc base;
 134 };
 135
 136 static int
 137 nv50_curs_create(struct nvif_device *device, struct nvif_object *disp,
 138                  int head, struct nv50_curs *curs)
 139 {
 140         struct nv50_disp_cursor_v0 args = {
 141                 .head = head,
 142         };
 143         static const s32 oclass[] = {
 144                 GK104_DISP_CURSOR,
 145                 GF110_DISP_CURSOR,
 146                 GT214_DISP_CURSOR,
 147                 G82_DISP_CURSOR,
 148                 NV50_DISP_CURSOR,
 149                 0
 150         };
 151
 152         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 153                                 &curs->base);
 154 }
 155
 156 /******************************************************************************
 157  * Overlay Immediate
 158  *****************************************************************************/
 159
 160 struct nv50_oimm {
 161         struct nv50_pioc base;
 162 };
 163
 164 static int
 165 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 166                  int head, struct nv50_oimm *oimm)
 167 {
 168         struct nv50_disp_cursor_v0 args = {
 169                 .head = head,
 170         };
 171         static const s32 oclass[] = {
 172                 GK104_DISP_OVERLAY,
 173                 GF110_DISP_OVERLAY,
 174                 GT214_DISP_OVERLAY,
 175                 G82_DISP_OVERLAY,
 176                 NV50_DISP_OVERLAY,
 177                 0
 178         };
 179
 180         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 181                                 &oimm->base);
 182 }
 183
 184 /******************************************************************************
 185  * DMA EVO channel
 186  *****************************************************************************/
 187
 188 struct nv50_dmac {
 189         struct nv50_chan base;
 190         dma_addr_t handle;
 191         u32 *ptr;
 192
 193         struct nvif_object sync;
 194         struct nvif_object vram;
 195
 196         /* Protects against concurrent pushbuf access to this channel, lock is
 197          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 198          * dropped again by evo_kick. */
 199         struct mutex lock;
 200 };
 201
 202 static void
 203 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 204 {
 205         struct nvif_device *device = dmac->base.device;
 206
 207         nvif_object_fini(&dmac->vram);
 208         nvif_object_fini(&dmac->sync);
 209
 210         nv50_chan_destroy(&dmac->base);
 211
 212         if (dmac->ptr) {
 213                 struct device *dev = nvxx_device(device)->dev;
 214                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 215         }
 216 }
 217
 218 static int
 219 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 220                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 221                  struct nv50_dmac *dmac)
 222 {
 223         struct nv50_disp_core_channel_dma_v0 *args = data;
 224         struct nvif_object pushbuf;
 225         int ret;
 226
 227         mutex_init(&dmac->lock);
 228
 229         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 230                                        &dmac->handle, GFP_KERNEL);
 231         if (!dmac->ptr)
 232                 return -ENOMEM;
 233
 234         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 235                                &(struct nv_dma_v0) {
 236                                         .target = NV_DMA_V0_TARGET_PCI_US,
 237                                         .access = NV_DMA_V0_ACCESS_RD,
 238                                         .start = dmac->handle + 0x0000,
 239                                         .limit = dmac->handle + 0x0fff,
 240                                }, sizeof(struct nv_dma_v0), &pushbuf);
 241         if (ret)
 242                 return ret;
 243
 244         args->pushbuf = nvif_handle(&pushbuf);
 245
 246         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 247                                &dmac->base);
 248         nvif_object_fini(&pushbuf);
 249         if (ret)
 250                 return ret;
 251
 252         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 253                                &(struct nv_dma_v0) {
 254                                         .target = NV_DMA_V0_TARGET_VRAM,
 255                                         .access = NV_DMA_V0_ACCESS_RDWR,
 256                                         .start = syncbuf + 0x0000,
 257                                         .limit = syncbuf + 0x0fff,
 258                                }, sizeof(struct nv_dma_v0),
 259                                &dmac->sync);
 260         if (ret)
 261                 return ret;
 262
 263         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 264                                &(struct nv_dma_v0) {
 265                                         .target = NV_DMA_V0_TARGET_VRAM,
 266                                         .access = NV_DMA_V0_ACCESS_RDWR,
 267                                         .start = 0,
 268                                         .limit = device->info.ram_user - 1,
 269                                }, sizeof(struct nv_dma_v0),
 270                                &dmac->vram);
 271         if (ret)
 272                 return ret;
 273
 274         return ret;
 275 }
 276
 277 /******************************************************************************
 278  * Core
 279  *****************************************************************************/
 280
 281 struct nv50_mast {
 282         struct nv50_dmac base;
 283 };
 284
 285 static int
 286 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 287                  u64 syncbuf, struct nv50_mast *core)
 288 {
 289         struct nv50_disp_core_channel_dma_v0 args = {
 290                 .pushbuf = 0xb0007d00,
 291         };
 292         static const s32 oclass[] = {
 293                 GM204_DISP_CORE_CHANNEL_DMA,
 294                 GM107_DISP_CORE_CHANNEL_DMA,
 295                 GK110_DISP_CORE_CHANNEL_DMA,
 296                 GK104_DISP_CORE_CHANNEL_DMA,
 297                 GF110_DISP_CORE_CHANNEL_DMA,
 298                 GT214_DISP_CORE_CHANNEL_DMA,
 299                 GT206_DISP_CORE_CHANNEL_DMA,
 300                 GT200_DISP_CORE_CHANNEL_DMA,
 301                 G82_DISP_CORE_CHANNEL_DMA,
 302                 NV50_DISP_CORE_CHANNEL_DMA,
 303                 0
 304         };
 305
 306         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 307                                 syncbuf, &core->base);
 308 }
 309
 310 /******************************************************************************
 311  * Base
 312  *****************************************************************************/
 313
 314 struct nv50_sync {
 315         struct nv50_dmac base;
 316         u32 addr;
 317         u32 data;
 318 };
 319
 320 static int
 321 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 322                  int head, u64 syncbuf, struct nv50_sync *base)
 323 {
 324         struct nv50_disp_base_channel_dma_v0 args = {
 325                 .pushbuf = 0xb0007c00 | head,
 326                 .head = head,
 327         };
 328         static const s32 oclass[] = {
 329                 GK110_DISP_BASE_CHANNEL_DMA,
 330                 GK104_DISP_BASE_CHANNEL_DMA,
 331                 GF110_DISP_BASE_CHANNEL_DMA,
 332                 GT214_DISP_BASE_CHANNEL_DMA,
 333                 GT200_DISP_BASE_CHANNEL_DMA,
 334                 G82_DISP_BASE_CHANNEL_DMA,
 335                 NV50_DISP_BASE_CHANNEL_DMA,
 336                 0
 337         };
 338
 339         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 340                                 syncbuf, &base->base);
 341 }
 342
 343 /******************************************************************************
 344  * Overlay
 345  *****************************************************************************/
 346
 347 struct nv50_ovly {
 348         struct nv50_dmac base;
 349 };
 350
 351 static int
 352 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 353                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 354 {
 355         struct nv50_disp_overlay_channel_dma_v0 args = {
 356                 .pushbuf = 0xb0007e00 | head,
 357                 .head = head,
 358         };
 359         static const s32 oclass[] = {
 360                 GK104_DISP_OVERLAY_CONTROL_DMA,
 361                 GF110_DISP_OVERLAY_CONTROL_DMA,
 362                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 363                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 364                 G82_DISP_OVERLAY_CHANNEL_DMA,
 365                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 366                 0
 367         };
 368
 369         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 370                                 syncbuf, &ovly->base);
 371 }
 372
 373 struct nv50_head {
 374         struct nouveau_crtc base;
 375         struct nouveau_bo *image;
 376         struct nv50_curs curs;
 377         struct nv50_sync sync;
 378         struct nv50_ovly ovly;
 379         struct nv50_oimm oimm;
 380 };
 381
 382 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 383 #define nv50_curs(c) (&nv50_head(c)->curs)
 384 #define nv50_sync(c) (&nv50_head(c)->sync)
 385 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 386 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 387 #define nv50_chan(c) (&(c)->base.base)
 388 #define nv50_vers(c) nv50_chan(c)->user.oclass
 389
 390 struct nv50_fbdma {
 391         struct list_head head;
 392         struct nvif_object core;
 393         struct nvif_object base[4];
 394 };
 395
 396 struct nv50_disp {
 397         struct nvif_object *disp;
 398         struct nv50_mast mast;
 399
 400         struct list_head fbdma;
 401
 402         struct nouveau_bo *sync;
 403 };
 404
 405 static struct nv50_disp *
 406 nv50_disp(struct drm_device *dev)
 407 {
 408         return nouveau_display(dev)->priv;
 409 }
 410
 411 #define nv50_mast(d) (&nv50_disp(d)->mast)
 412
 413 static struct drm_crtc *
 414 nv50_display_crtc_get(struct drm_encoder *encoder)
 415 {
 416         return nouveau_encoder(encoder)->crtc;
 417 }
 418
 419 /******************************************************************************
 420  * EVO channel helpers
 421  *****************************************************************************/
 422 static u32 *
 423 evo_wait(void *evoc, int nr)
 424 {
 425         struct nv50_dmac *dmac = evoc;
 426         struct nvif_device *device = dmac->base.device;
 427         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 428
 429         mutex_lock(&dmac->lock);
 430         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 431                 dmac->ptr[put] = 0x20000000;
 432
 433                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 434                 if (nvif_msec(device, 2000,
 435                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 436                                 break;
 437                 ) < 0) {
 438                         mutex_unlock(&dmac->lock);
 439                         printk(KERN_ERR "nouveau: evo channel stalled\n");
 440                         return NULL;
 441                 }
 442
 443                 put = 0;
 444         }
 445
 446         return dmac->ptr + put;
 447 }
 448
 449 static void
 450 evo_kick(u32 *push, void *evoc)
 451 {
 452         struct nv50_dmac *dmac = evoc;
 453         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 454         mutex_unlock(&dmac->lock);
 455 }
 456
 457 #if 1
 458 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 459 #define evo_data(p,d)   *((p)++) = (d)
 460 #else
 461 #define evo_mthd(p,m,s) do {                                                   \
 462         const u32 _m = (m), _s = (s);                                          \
 463         printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__);                     \
 464         *((p)++) = ((_s << 18) | _m);                                          \
 465 } while(0)
 466 #define evo_data(p,d) do {                                                     \
 467         const u32 _d = (d);                                                    \
 468         printk(KERN_ERR "\t%08x\n", _d);                                       \
 469         *((p)++) = _d;                                                         \
 470 } while(0)
 471 #endif
 472
 473 static bool
 474 evo_sync_wait(void *data)
 475 {
 476         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 477                 return true;
 478         usleep_range(1, 2);
 479         return false;
 480 }
 481
 482 static int
 483 evo_sync(struct drm_device *dev)
 484 {
 485         struct nvif_device *device = &nouveau_drm(dev)->device;
 486         struct nv50_disp *disp = nv50_disp(dev);
 487         struct nv50_mast *mast = nv50_mast(dev);
 488         u32 *push = evo_wait(mast, 8);
 489         if (push) {
 490                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 491                 evo_mthd(push, 0x0084, 1);
 492                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 493                 evo_mthd(push, 0x0080, 2);
 494                 evo_data(push, 0x00000000);
 495                 evo_data(push, 0x00000000);
 496                 evo_kick(push, mast);
 497                 if (nvif_msec(device, 2000,
 498                         if (evo_sync_wait(disp->sync))
 499                                 break;
 500                 ) >= 0)
 501                         return 0;
 502         }
 503
 504         return -EBUSY;
 505 }
 506
 507 /******************************************************************************
 508  * Page flipping channel
 509  *****************************************************************************/
 510 struct nouveau_bo *
 511 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 512 {
 513         return nv50_disp(dev)->sync;
 514 }
 515
 516 struct nv50_display_flip {
 517         struct nv50_disp *disp;
 518         struct nv50_sync *chan;
 519 };
 520
 521 static bool
 522 nv50_display_flip_wait(void *data)
 523 {
 524         struct nv50_display_flip *flip = data;
 525         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 526                                               flip->chan->data)
 527                 return true;
 528         usleep_range(1, 2);
 529         return false;
 530 }
 531
 532 void
 533 nv50_display_flip_stop(struct drm_crtc *crtc)
 534 {
 535         struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
 536         struct nv50_display_flip flip = {
 537                 .disp = nv50_disp(crtc->dev),
 538                 .chan = nv50_sync(crtc),
 539         };
 540         u32 *push;
 541
 542         push = evo_wait(flip.chan, 8);
 543         if (push) {
 544                 evo_mthd(push, 0x0084, 1);
 545                 evo_data(push, 0x00000000);
 546                 evo_mthd(push, 0x0094, 1);
 547                 evo_data(push, 0x00000000);
 548                 evo_mthd(push, 0x00c0, 1);
 549                 evo_data(push, 0x00000000);
 550                 evo_mthd(push, 0x0080, 1);
 551                 evo_data(push, 0x00000000);
 552                 evo_kick(push, flip.chan);
 553         }
 554
 555         nvif_msec(device, 2000,
 556                 if (nv50_display_flip_wait(&flip))
 557                         break;
 558         );
 559 }
 560
 561 int
 562 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 563                        struct nouveau_channel *chan, u32 swap_interval)
 564 {
 565         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 566         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 567         struct nv50_head *head = nv50_head(crtc);
 568         struct nv50_sync *sync = nv50_sync(crtc);
 569         u32 *push;
 570         int ret;
 571
 572         if (crtc->primary->fb->width != fb->width ||
 573             crtc->primary->fb->height != fb->height)
 574                 return -EINVAL;
 575
 576         swap_interval <<= 4;
 577         if (swap_interval == 0)
 578                 swap_interval |= 0x100;
 579         if (chan == NULL)
 580                 evo_sync(crtc->dev);
 581
 582         push = evo_wait(sync, 128);
 583         if (unlikely(push == NULL))
 584                 return -EBUSY;
 585
 586         if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
 587                 ret = RING_SPACE(chan, 8);
 588                 if (ret)
 589                         return ret;
 590
 591                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 592                 OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 593                 OUT_RING  (chan, sync->addr ^ 0x10);
 594                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 595                 OUT_RING  (chan, sync->data + 1);
 596                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 597                 OUT_RING  (chan, sync->addr);
 598                 OUT_RING  (chan, sync->data);
 599         } else
 600         if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
 601                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 602                 ret = RING_SPACE(chan, 12);
 603                 if (ret)
 604                         return ret;
 605
 606                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 607                 OUT_RING  (chan, chan->vram.handle);
 608                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 609                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 610                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 611                 OUT_RING  (chan, sync->data + 1);
 612                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 613                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 614                 OUT_RING  (chan, upper_32_bits(addr));
 615                 OUT_RING  (chan, lower_32_bits(addr));
 616                 OUT_RING  (chan, sync->data);
 617                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 618         } else
 619         if (chan) {
 620                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 621                 ret = RING_SPACE(chan, 10);
 622                 if (ret)
 623                         return ret;
 624
 625                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 626                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 627                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 628                 OUT_RING  (chan, sync->data + 1);
 629                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 630                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 631                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 632                 OUT_RING  (chan, upper_32_bits(addr));
 633                 OUT_RING  (chan, lower_32_bits(addr));
 634                 OUT_RING  (chan, sync->data);
 635                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 636                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 637         }
 638
 639         if (chan) {
 640                 sync->addr ^= 0x10;
 641                 sync->data++;
 642                 FIRE_RING (chan);
 643         }
 644
 645         /* queue the flip */
 646         evo_mthd(push, 0x0100, 1);
 647         evo_data(push, 0xfffe0000);
 648         evo_mthd(push, 0x0084, 1);
 649         evo_data(push, swap_interval);
 650         if (!(swap_interval & 0x00000100)) {
 651                 evo_mthd(push, 0x00e0, 1);
 652                 evo_data(push, 0x40000000);
 653         }
 654         evo_mthd(push, 0x0088, 4);
 655         evo_data(push, sync->addr);
 656         evo_data(push, sync->data++);
 657         evo_data(push, sync->data);
 658         evo_data(push, sync->base.sync.handle);
 659         evo_mthd(push, 0x00a0, 2);
 660         evo_data(push, 0x00000000);
 661         evo_data(push, 0x00000000);
 662         evo_mthd(push, 0x00c0, 1);
 663         evo_data(push, nv_fb->r_handle);
 664         evo_mthd(push, 0x0110, 2);
 665         evo_data(push, 0x00000000);
 666         evo_data(push, 0x00000000);
 667         if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
 668                 evo_mthd(push, 0x0800, 5);
 669                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 670                 evo_data(push, 0);
 671                 evo_data(push, (fb->height << 16) | fb->width);
 672                 evo_data(push, nv_fb->r_pitch);
 673                 evo_data(push, nv_fb->r_format);
 674         } else {
 675                 evo_mthd(push, 0x0400, 5);
 676                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 677                 evo_data(push, 0);
 678                 evo_data(push, (fb->height << 16) | fb->width);
 679                 evo_data(push, nv_fb->r_pitch);
 680                 evo_data(push, nv_fb->r_format);
 681         }
 682         evo_mthd(push, 0x0080, 1);
 683         evo_data(push, 0x00000000);
 684         evo_kick(push, sync);
 685
 686         nouveau_bo_ref(nv_fb->nvbo, &head->image);
 687         return 0;
 688 }
 689
 690 /******************************************************************************
 691  * CRTC
 692  *****************************************************************************/
 693 static int
 694 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 695 {
 696         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 697         struct nouveau_connector *nv_connector;
 698         struct drm_connector *connector;
 699         u32 *push, mode = 0x00;
 700
 701         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 702         connector = &nv_connector->base;
 703         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 704                 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
 705                         mode = DITHERING_MODE_DYNAMIC2X2;
 706         } else {
 707                 mode = nv_connector->dithering_mode;
 708         }
 709
 710         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 711                 if (connector->display_info.bpc >= 8)
 712                         mode |= DITHERING_DEPTH_8BPC;
 713         } else {
 714                 mode |= nv_connector->dithering_depth;
 715         }
 716
 717         push = evo_wait(mast, 4);
 718         if (push) {
 719                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 720                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 721                         evo_data(push, mode);
 722                 } else
 723                 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
 724                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 725                         evo_data(push, mode);
 726                 } else {
 727                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 728                         evo_data(push, mode);
 729                 }
 730
 731                 if (update) {
 732                         evo_mthd(push, 0x0080, 1);
 733                         evo_data(push, 0x00000000);
 734                 }
 735                 evo_kick(push, mast);
 736         }
 737
 738         return 0;
 739 }
 740
 741 static int
 742 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 743 {
 744         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 745         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 746         struct drm_crtc *crtc = &nv_crtc->base;
 747         struct nouveau_connector *nv_connector;
 748         int mode = DRM_MODE_SCALE_NONE;
 749         u32 oX, oY, *push;
 750
 751         /* start off at the resolution we programmed the crtc for, this
 752          * effectively handles NONE/FULL scaling
 753          */
 754         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 755         if (nv_connector && nv_connector->native_mode) {
 756                 mode = nv_connector->scaling_mode;
 757                 if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */
 758                         mode = DRM_MODE_SCALE_FULLSCREEN;
 759         }
 760
 761         if (mode != DRM_MODE_SCALE_NONE)
 762                 omode = nv_connector->native_mode;
 763         else
 764                 omode = umode;
 765
 766         oX = omode->hdisplay;
 767         oY = omode->vdisplay;
 768         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 769                 oY *= 2;
 770
 771         /* add overscan compensation if necessary, will keep the aspect
 772          * ratio the same as the backend mode unless overridden by the
 773          * user setting both hborder and vborder properties.
 774          */
 775         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 776                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 777                               nv_connector->edid &&
 778                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 779                 u32 bX = nv_connector->underscan_hborder;
 780                 u32 bY = nv_connector->underscan_vborder;
 781                 u32 aspect = (oY << 19) / oX;
 782
 783                 if (bX) {
 784                         oX -= (bX * 2);
 785                         if (bY) oY -= (bY * 2);
 786                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 787                 } else {
 788                         oX -= (oX >> 4) + 32;
 789                         if (bY) oY -= (bY * 2);
 790                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 791                 }
 792         }
 793
 794         /* handle CENTER/ASPECT scaling, taking into account the areas
 795          * removed already for overscan compensation
 796          */
 797         switch (mode) {
 798         case DRM_MODE_SCALE_CENTER:
 799                 oX = min((u32)umode->hdisplay, oX);
 800                 oY = min((u32)umode->vdisplay, oY);
 801                 /* fall-through */
 802         case DRM_MODE_SCALE_ASPECT:
 803                 if (oY < oX) {
 804                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 805                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 806                 } else {
 807                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 808                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 809                 }
 810                 break;
 811         default:
 812                 break;
 813         }
 814
 815         push = evo_wait(mast, 8);
 816         if (push) {
 817                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 818                         /*XXX: SCALE_CTRL_ACTIVE??? */
 819                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 820                         evo_data(push, (oY << 16) | oX);
 821                         evo_data(push, (oY << 16) | oX);
 822                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 823                         evo_data(push, 0x00000000);
 824                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 825                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 826                 } else {
 827                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 828                         evo_data(push, (oY << 16) | oX);
 829                         evo_data(push, (oY << 16) | oX);
 830                         evo_data(push, (oY << 16) | oX);
 831                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 832                         evo_data(push, 0x00000000);
 833                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 834                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 835                 }
 836
 837                 evo_kick(push, mast);
 838
 839                 if (update) {
 840                         nv50_display_flip_stop(crtc);
 841                         nv50_display_flip_next(crtc, crtc->primary->fb,
 842                                                NULL, 1);
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static int
 850 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
 851 {
 852         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 853         u32 *push;
 854
 855         push = evo_wait(mast, 8);
 856         if (!push)
 857                 return -ENOMEM;
 858
 859         evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
 860         evo_data(push, usec);
 861         evo_kick(push, mast);
 862         return 0;
 863 }
 864
 865 static int
 866 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 867 {
 868         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 869         u32 *push, hue, vib;
 870         int adj;
 871
 872         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 873         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 874         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 875
 876         push = evo_wait(mast, 16);
 877         if (push) {
 878                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 879                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 880                         evo_data(push, (hue << 20) | (vib << 8));
 881                 } else {
 882                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 883                         evo_data(push, (hue << 20) | (vib << 8));
 884                 }
 885
 886                 if (update) {
 887                         evo_mthd(push, 0x0080, 1);
 888                         evo_data(push, 0x00000000);
 889                 }
 890                 evo_kick(push, mast);
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int
 897 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 898                     int x, int y, bool update)
 899 {
 900         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 901         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 902         u32 *push;
 903
 904         push = evo_wait(mast, 16);
 905         if (push) {
 906                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 907                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 908                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 909                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 910                         evo_data(push, (fb->height << 16) | fb->width);
 911                         evo_data(push, nvfb->r_pitch);
 912                         evo_data(push, nvfb->r_format);
 913                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 914                         evo_data(push, (y << 16) | x);
 915                         if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
 916                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 917                                 evo_data(push, nvfb->r_handle);
 918                         }
 919                 } else {
 920                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 921                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 922                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 923                         evo_data(push, (fb->height << 16) | fb->width);
 924                         evo_data(push, nvfb->r_pitch);
 925                         evo_data(push, nvfb->r_format);
 926                         evo_data(push, nvfb->r_handle);
 927                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 928                         evo_data(push, (y << 16) | x);
 929                 }
 930
 931                 if (update) {
 932                         evo_mthd(push, 0x0080, 1);
 933                         evo_data(push, 0x00000000);
 934                 }
 935                 evo_kick(push, mast);
 936         }
 937
 938         nv_crtc->fb.handle = nvfb->r_handle;
 939         return 0;
 940 }
 941
 942 static void
 943 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 944 {
 945         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 946         u32 *push = evo_wait(mast, 16);
 947         if (push) {
 948                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 949                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 950                         evo_data(push, 0x85000000);
 951                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 952                 } else
 953                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 954                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 955                         evo_data(push, 0x85000000);
 956                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 957                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 958                         evo_data(push, mast->base.vram.handle);
 959                 } else {
 960                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 961                         evo_data(push, 0x85000000);
 962                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 963                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 964                         evo_data(push, mast->base.vram.handle);
 965                 }
 966                 evo_kick(push, mast);
 967         }
 968         nv_crtc->cursor.visible = true;
 969 }
 970
 971 static void
 972 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 973 {
 974         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 975         u32 *push = evo_wait(mast, 16);
 976         if (push) {
 977                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 978                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 979                         evo_data(push, 0x05000000);
 980                 } else
 981                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 982                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 983                         evo_data(push, 0x05000000);
 984                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 985                         evo_data(push, 0x00000000);
 986                 } else {
 987                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 988                         evo_data(push, 0x05000000);
 989                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 990                         evo_data(push, 0x00000000);
 991                 }
 992                 evo_kick(push, mast);
 993         }
 994         nv_crtc->cursor.visible = false;
 995 }
 996
 997 static void
 998 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 999 {
1000         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1001
1002         if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
1003                 nv50_crtc_cursor_show(nv_crtc);
1004         else
1005                 nv50_crtc_cursor_hide(nv_crtc);
1006
1007         if (update) {
1008                 u32 *push = evo_wait(mast, 2);
1009                 if (push) {
1010                         evo_mthd(push, 0x0080, 1);
1011                         evo_data(push, 0x00000000);
1012                         evo_kick(push, mast);
1013                 }
1014         }
1015 }
1016
1017 static void
1018 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
1019 {
1020 }
1021
1022 static void
1023 nv50_crtc_prepare(struct drm_crtc *crtc)
1024 {
1025         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1026         struct nv50_mast *mast = nv50_mast(crtc->dev);
1027         u32 *push;
1028
1029         nv50_display_flip_stop(crtc);
1030
1031         push = evo_wait(mast, 6);
1032         if (push) {
1033                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1034                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1035                         evo_data(push, 0x00000000);
1036                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1037                         evo_data(push, 0x40000000);
1038                 } else
1039                 if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
1040                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1041                         evo_data(push, 0x00000000);
1042                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1043                         evo_data(push, 0x40000000);
1044                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1045                         evo_data(push, 0x00000000);
1046                 } else {
1047                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1048                         evo_data(push, 0x00000000);
1049                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1050                         evo_data(push, 0x03000000);
1051                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1052                         evo_data(push, 0x00000000);
1053                 }
1054
1055                 evo_kick(push, mast);
1056         }
1057
1058         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1059 }
1060
1061 static void
1062 nv50_crtc_commit(struct drm_crtc *crtc)
1063 {
1064         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1065         struct nv50_mast *mast = nv50_mast(crtc->dev);
1066         u32 *push;
1067
1068         push = evo_wait(mast, 32);
1069         if (push) {
1070                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1071                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1072                         evo_data(push, nv_crtc->fb.handle);
1073                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1074                         evo_data(push, 0xc0000000);
1075                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1076                 } else
1077                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1078                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1079                         evo_data(push, nv_crtc->fb.handle);
1080                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1081                         evo_data(push, 0xc0000000);
1082                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1083                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1084                         evo_data(push, mast->base.vram.handle);
1085                 } else {
1086                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1087                         evo_data(push, nv_crtc->fb.handle);
1088                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1089                         evo_data(push, 0x83000000);
1090                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1091                         evo_data(push, 0x00000000);
1092                         evo_data(push, 0x00000000);
1093                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1094                         evo_data(push, mast->base.vram.handle);
1095                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1096                         evo_data(push, 0xffffff00);
1097                 }
1098
1099                 evo_kick(push, mast);
1100         }
1101
1102         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1103         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1104 }
1105
1106 static bool
1107 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1108                      struct drm_display_mode *adjusted_mode)
1109 {
1110         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1111         return true;
1112 }
1113
1114 static int
1115 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1116 {
1117         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1118         struct nv50_head *head = nv50_head(crtc);
1119         int ret;
1120
1121         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1122         if (ret == 0) {
1123                 if (head->image)
1124                         nouveau_bo_unpin(head->image);
1125                 nouveau_bo_ref(nvfb->nvbo, &head->image);
1126         }
1127
1128         return ret;
1129 }
1130
1131 static int
1132 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1133                    struct drm_display_mode *mode, int x, int y,
1134                    struct drm_framebuffer *old_fb)
1135 {
1136         struct nv50_mast *mast = nv50_mast(crtc->dev);
1137         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1138         struct nouveau_connector *nv_connector;
1139         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1140         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1141         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1142         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1143         u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1144         u32 *push;
1145         int ret;
1146
1147         hactive = mode->htotal;
1148         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1149         hbackp  = mode->htotal - mode->hsync_end;
1150         hblanke = hsynce + hbackp;
1151         hfrontp = mode->hsync_start - mode->hdisplay;
1152         hblanks = mode->htotal - hfrontp - 1;
1153
1154         vactive = mode->vtotal * vscan / ilace;
1155         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1156         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1157         vblanke = vsynce + vbackp;
1158         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1159         vblanks = vactive - vfrontp - 1;
1160         /* XXX: Safe underestimate, even "0" works */
1161         vblankus = (vactive - mode->vdisplay - 2) * hactive;
1162         vblankus *= 1000;
1163         vblankus /= mode->clock;
1164
1165         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1166                 vblan2e = vactive + vsynce + vbackp;
1167                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1168                 vactive = (vactive * 2) + 1;
1169         }
1170
1171         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1172         if (ret)
1173                 return ret;
1174
1175         push = evo_wait(mast, 64);
1176         if (push) {
1177                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1178                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1179                         evo_data(push, 0x00800000 | mode->clock);
1180                         evo_data(push, (ilace == 2) ? 2 : 0);
1181                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1182                         evo_data(push, 0x00000000);
1183                         evo_data(push, (vactive << 16) | hactive);
1184                         evo_data(push, ( vsynce << 16) | hsynce);
1185                         evo_data(push, (vblanke << 16) | hblanke);
1186                         evo_data(push, (vblanks << 16) | hblanks);
1187                         evo_data(push, (vblan2e << 16) | vblan2s);
1188                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1189                         evo_data(push, 0x00000000);
1190                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1191                         evo_data(push, 0x00000311);
1192                         evo_data(push, 0x00000100);
1193                 } else {
1194                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1195                         evo_data(push, 0x00000000);
1196                         evo_data(push, (vactive << 16) | hactive);
1197                         evo_data(push, ( vsynce << 16) | hsynce);
1198                         evo_data(push, (vblanke << 16) | hblanke);
1199                         evo_data(push, (vblanks << 16) | hblanks);
1200                         evo_data(push, (vblan2e << 16) | vblan2s);
1201                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1202                         evo_data(push, 0x00000000); /* ??? */
1203                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1204                         evo_data(push, mode->clock * 1000);
1205                         evo_data(push, 0x00200000); /* ??? */
1206                         evo_data(push, mode->clock * 1000);
1207                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1208                         evo_data(push, 0x00000311);
1209                         evo_data(push, 0x00000100);
1210                 }
1211
1212                 evo_kick(push, mast);
1213         }
1214
1215         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1216         nv50_crtc_set_dither(nv_crtc, false);
1217         nv50_crtc_set_scale(nv_crtc, false);
1218
1219         /* G94 only accepts this after setting scale */
1220         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1221                 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1222
1223         nv50_crtc_set_color_vibrance(nv_crtc, false);
1224         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1225         return 0;
1226 }
1227
1228 static int
1229 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1230                         struct drm_framebuffer *old_fb)
1231 {
1232         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1233         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1234         int ret;
1235
1236         if (!crtc->primary->fb) {
1237                 NV_DEBUG(drm, "No FB bound\n");
1238                 return 0;
1239         }
1240
1241         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1242         if (ret)
1243                 return ret;
1244
1245         nv50_display_flip_stop(crtc);
1246         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1247         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1248         return 0;
1249 }
1250
1251 static int
1252 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1253                                struct drm_framebuffer *fb, int x, int y,
1254                                enum mode_set_atomic state)
1255 {
1256         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1257         nv50_display_flip_stop(crtc);
1258         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1259         return 0;
1260 }
1261
1262 static void
1263 nv50_crtc_lut_load(struct drm_crtc *crtc)
1264 {
1265         struct nv50_disp *disp = nv50_disp(crtc->dev);
1266         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1267         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1268         int i;
1269
1270         for (i = 0; i < 256; i++) {
1271                 u16 r = nv_crtc->lut.r[i] >> 2;
1272                 u16 g = nv_crtc->lut.g[i] >> 2;
1273                 u16 b = nv_crtc->lut.b[i] >> 2;
1274
1275                 if (disp->disp->oclass < GF110_DISP) {
1276                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1277                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1278                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1279                 } else {
1280                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1281                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1282                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1283                 }
1284         }
1285 }
1286
1287 static void
1288 nv50_crtc_disable(struct drm_crtc *crtc)
1289 {
1290         struct nv50_head *head = nv50_head(crtc);
1291         evo_sync(crtc->dev);
1292         if (head->image)
1293                 nouveau_bo_unpin(head->image);
1294         nouveau_bo_ref(NULL, &head->image);
1295 }
1296
1297 static int
1298 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1299                      uint32_t handle, uint32_t width, uint32_t height)
1300 {
1301         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1302         struct drm_device *dev = crtc->dev;
1303         struct drm_gem_object *gem = NULL;
1304         struct nouveau_bo *nvbo = NULL;
1305         int ret = 0;
1306
1307         if (handle) {
1308                 if (width != 64 || height != 64)
1309                         return -EINVAL;
1310
1311                 gem = drm_gem_object_lookup(dev, file_priv, handle);
1312                 if (unlikely(!gem))
1313                         return -ENOENT;
1314                 nvbo = nouveau_gem_object(gem);
1315
1316                 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1317         }
1318
1319         if (ret == 0) {
1320                 if (nv_crtc->cursor.nvbo)
1321                         nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1322                 nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
1323         }
1324         drm_gem_object_unreference_unlocked(gem);
1325
1326         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1327         return ret;
1328 }
1329
1330 static int
1331 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1332 {
1333         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1334         struct nv50_curs *curs = nv50_curs(crtc);
1335         struct nv50_chan *chan = nv50_chan(curs);
1336         nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1337         nvif_wr32(&chan->user, 0x0080, 0x00000000);
1338
1339         nv_crtc->cursor_saved_x = x;
1340         nv_crtc->cursor_saved_y = y;
1341         return 0;
1342 }
1343
1344 static void
1345 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1346                     uint32_t start, uint32_t size)
1347 {
1348         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1349         u32 end = min_t(u32, start + size, 256);
1350         u32 i;
1351
1352         for (i = start; i < end; i++) {
1353                 nv_crtc->lut.r[i] = r[i];
1354                 nv_crtc->lut.g[i] = g[i];
1355                 nv_crtc->lut.b[i] = b[i];
1356         }
1357
1358         nv50_crtc_lut_load(crtc);
1359 }
1360
1361 static void
1362 nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
1363 {
1364         nv50_crtc_cursor_move(&nv_crtc->base, x, y);
1365
1366         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1367 }
1368
1369 static void
1370 nv50_crtc_destroy(struct drm_crtc *crtc)
1371 {
1372         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1373         struct nv50_disp *disp = nv50_disp(crtc->dev);
1374         struct nv50_head *head = nv50_head(crtc);
1375         struct nv50_fbdma *fbdma;
1376
1377         list_for_each_entry(fbdma, &disp->fbdma, head) {
1378                 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1379         }
1380
1381         nv50_dmac_destroy(&head->ovly.base, disp->disp);
1382         nv50_pioc_destroy(&head->oimm.base);
1383         nv50_dmac_destroy(&head->sync.base, disp->disp);
1384         nv50_pioc_destroy(&head->curs.base);
1385
1386         /*XXX: this shouldn't be necessary, but the core doesn't call
1387          *     disconnect() during the cleanup paths
1388          */
1389         if (head->image)
1390                 nouveau_bo_unpin(head->image);
1391         nouveau_bo_ref(NULL, &head->image);
1392
1393         /*XXX: ditto */
1394         if (nv_crtc->cursor.nvbo)
1395                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1396         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1397
1398         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1399         if (nv_crtc->lut.nvbo)
1400                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1401         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1402
1403         drm_crtc_cleanup(crtc);
1404         kfree(crtc);
1405 }
1406
1407 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1408         .dpms = nv50_crtc_dpms,
1409         .prepare = nv50_crtc_prepare,
1410         .commit = nv50_crtc_commit,
1411         .mode_fixup = nv50_crtc_mode_fixup,
1412         .mode_set = nv50_crtc_mode_set,
1413         .mode_set_base = nv50_crtc_mode_set_base,
1414         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1415         .load_lut = nv50_crtc_lut_load,
1416         .disable = nv50_crtc_disable,
1417 };
1418
1419 static const struct drm_crtc_funcs nv50_crtc_func = {
1420         .cursor_set = nv50_crtc_cursor_set,
1421         .cursor_move = nv50_crtc_cursor_move,
1422         .gamma_set = nv50_crtc_gamma_set,
1423         .set_config = nouveau_crtc_set_config,
1424         .destroy = nv50_crtc_destroy,
1425         .page_flip = nouveau_crtc_page_flip,
1426 };
1427
1428 static int
1429 nv50_crtc_create(struct drm_device *dev, int index)
1430 {
1431         struct nouveau_drm *drm = nouveau_drm(dev);
1432         struct nvif_device *device = &drm->device;
1433         struct nv50_disp *disp = nv50_disp(dev);
1434         struct nv50_head *head;
1435         struct drm_crtc *crtc;
1436         int ret, i;
1437
1438         head = kzalloc(sizeof(*head), GFP_KERNEL);
1439         if (!head)
1440                 return -ENOMEM;
1441
1442         head->base.index = index;
1443         head->base.set_dither = nv50_crtc_set_dither;
1444         head->base.set_scale = nv50_crtc_set_scale;
1445         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1446         head->base.color_vibrance = 50;
1447         head->base.vibrant_hue = 0;
1448         head->base.cursor.set_pos = nv50_crtc_cursor_restore;
1449         for (i = 0; i < 256; i++) {
1450                 head->base.lut.r[i] = i << 8;
1451                 head->base.lut.g[i] = i << 8;
1452                 head->base.lut.b[i] = i << 8;
1453         }
1454
1455         crtc = &head->base.base;
1456         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1457         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1458         drm_mode_crtc_set_gamma_size(crtc, 256);
1459
1460         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1461                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1462         if (!ret) {
1463                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1464                 if (!ret) {
1465                         ret = nouveau_bo_map(head->base.lut.nvbo);
1466                         if (ret)
1467                                 nouveau_bo_unpin(head->base.lut.nvbo);
1468                 }
1469                 if (ret)
1470                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1471         }
1472
1473         if (ret)
1474                 goto out;
1475
1476         /* allocate cursor resources */
1477         ret = nv50_curs_create(device, disp->disp, index, &head->curs);
1478         if (ret)
1479                 goto out;
1480
1481         /* allocate page flip / sync resources */
1482         ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,
1483                                &head->sync);
1484         if (ret)
1485                 goto out;
1486
1487         head->sync.addr = EVO_FLIP_SEM0(index);
1488         head->sync.data = 0x00000000;
1489
1490         /* allocate overlay resources */
1491         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
1492         if (ret)
1493                 goto out;
1494
1495         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
1496                                &head->ovly);
1497         if (ret)
1498                 goto out;
1499
1500 out:
1501         if (ret)
1502                 nv50_crtc_destroy(crtc);
1503         return ret;
1504 }
1505
1506 /******************************************************************************
1507  * Encoder helpers
1508  *****************************************************************************/
1509 static bool
1510 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1511                         const struct drm_display_mode *mode,
1512                         struct drm_display_mode *adjusted_mode)
1513 {
1514         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1515         struct nouveau_connector *nv_connector;
1516
1517         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1518         if (nv_connector && nv_connector->native_mode) {
1519                 nv_connector->scaling_full = false;
1520                 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
1521                         switch (nv_connector->type) {
1522                         case DCB_CONNECTOR_LVDS:
1523                         case DCB_CONNECTOR_LVDS_SPWG:
1524                         case DCB_CONNECTOR_eDP:
1525                                 /* force use of scaler for non-edid modes */
1526                                 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
1527                                         return true;
1528                                 nv_connector->scaling_full = true;
1529                                 break;
1530                         default:
1531                                 return true;
1532                         }
1533                 }
1534
1535                 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1536         }
1537
1538         return true;
1539 }
1540
1541 /******************************************************************************
1542  * DAC
1543  *****************************************************************************/
1544 static void
1545 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1546 {
1547         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1548         struct nv50_disp *disp = nv50_disp(encoder->dev);
1549         struct {
1550                 struct nv50_disp_mthd_v1 base;
1551                 struct nv50_disp_dac_pwr_v0 pwr;
1552         } args = {
1553                 .base.version = 1,
1554                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1555                 .base.hasht  = nv_encoder->dcb->hasht,
1556                 .base.hashm  = nv_encoder->dcb->hashm,
1557                 .pwr.state = 1,
1558                 .pwr.data  = 1,
1559                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1560                               mode != DRM_MODE_DPMS_OFF),
1561                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1562                               mode != DRM_MODE_DPMS_OFF),
1563         };
1564
1565         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1566 }
1567
1568 static void
1569 nv50_dac_commit(struct drm_encoder *encoder)
1570 {
1571 }
1572
1573 static void
1574 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1575                   struct drm_display_mode *adjusted_mode)
1576 {
1577         struct nv50_mast *mast = nv50_mast(encoder->dev);
1578         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1579         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1580         u32 *push;
1581
1582         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1583
1584         push = evo_wait(mast, 8);
1585         if (push) {
1586                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1587                         u32 syncs = 0x00000000;
1588
1589                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1590                                 syncs |= 0x00000001;
1591                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1592                                 syncs |= 0x00000002;
1593
1594                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1595                         evo_data(push, 1 << nv_crtc->index);
1596                         evo_data(push, syncs);
1597                 } else {
1598                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1599                         u32 syncs = 0x00000001;
1600
1601                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1602                                 syncs |= 0x00000008;
1603                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1604                                 syncs |= 0x00000010;
1605
1606                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1607                                 magic |= 0x00000001;
1608
1609                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1610                         evo_data(push, syncs);
1611                         evo_data(push, magic);
1612                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1613                         evo_data(push, 1 << nv_crtc->index);
1614                 }
1615
1616                 evo_kick(push, mast);
1617         }
1618
1619         nv_encoder->crtc = encoder->crtc;
1620 }
1621
1622 static void
1623 nv50_dac_disconnect(struct drm_encoder *encoder)
1624 {
1625         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1626         struct nv50_mast *mast = nv50_mast(encoder->dev);
1627         const int or = nv_encoder->or;
1628         u32 *push;
1629
1630         if (nv_encoder->crtc) {
1631                 nv50_crtc_prepare(nv_encoder->crtc);
1632
1633                 push = evo_wait(mast, 4);
1634                 if (push) {
1635                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1636                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1637                                 evo_data(push, 0x00000000);
1638                         } else {
1639                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1640                                 evo_data(push, 0x00000000);
1641                         }
1642                         evo_kick(push, mast);
1643                 }
1644         }
1645
1646         nv_encoder->crtc = NULL;
1647 }
1648
1649 static enum drm_connector_status
1650 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1651 {
1652         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1653         struct nv50_disp *disp = nv50_disp(encoder->dev);
1654         struct {
1655                 struct nv50_disp_mthd_v1 base;
1656                 struct nv50_disp_dac_load_v0 load;
1657         } args = {
1658                 .base.version = 1,
1659                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1660                 .base.hasht  = nv_encoder->dcb->hasht,
1661                 .base.hashm  = nv_encoder->dcb->hashm,
1662         };
1663         int ret;
1664
1665         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1666         if (args.load.data == 0)
1667                 args.load.data = 340;
1668
1669         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1670         if (ret || !args.load.load)
1671                 return connector_status_disconnected;
1672
1673         return connector_status_connected;
1674 }
1675
1676 static void
1677 nv50_dac_destroy(struct drm_encoder *encoder)
1678 {
1679         drm_encoder_cleanup(encoder);
1680         kfree(encoder);
1681 }
1682
1683 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1684         .dpms = nv50_dac_dpms,
1685         .mode_fixup = nv50_encoder_mode_fixup,
1686         .prepare = nv50_dac_disconnect,
1687         .commit = nv50_dac_commit,
1688         .mode_set = nv50_dac_mode_set,
1689         .disable = nv50_dac_disconnect,
1690         .get_crtc = nv50_display_crtc_get,
1691         .detect = nv50_dac_detect
1692 };
1693
1694 static const struct drm_encoder_funcs nv50_dac_func = {
1695         .destroy = nv50_dac_destroy,
1696 };
1697
1698 static int
1699 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1700 {
1701         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1702         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
1703         struct nvkm_i2c_bus *bus;
1704         struct nouveau_encoder *nv_encoder;
1705         struct drm_encoder *encoder;
1706         int type = DRM_MODE_ENCODER_DAC;
1707
1708         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1709         if (!nv_encoder)
1710                 return -ENOMEM;
1711         nv_encoder->dcb = dcbe;
1712         nv_encoder->or = ffs(dcbe->or) - 1;
1713
1714         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1715         if (bus)
1716                 nv_encoder->i2c = &bus->i2c;
1717
1718         encoder = to_drm_encoder(nv_encoder);
1719         encoder->possible_crtcs = dcbe->heads;
1720         encoder->possible_clones = 0;
1721         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, NULL);
1722         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1723
1724         drm_mode_connector_attach_encoder(connector, encoder);
1725         return 0;
1726 }
1727
1728 /******************************************************************************
1729  * Audio
1730  *****************************************************************************/
1731 static void
1732 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1733 {
1734         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1735         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1736         struct nouveau_connector *nv_connector;
1737         struct nv50_disp *disp = nv50_disp(encoder->dev);
1738         struct __packed {
1739                 struct {
1740                         struct nv50_disp_mthd_v1 mthd;
1741                         struct nv50_disp_sor_hda_eld_v0 eld;
1742                 } base;
1743                 u8 data[sizeof(nv_connector->base.eld)];
1744         } args = {
1745                 .base.mthd.version = 1,
1746                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1747                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
1748                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1749                                      (0x0100 << nv_crtc->index),
1750         };
1751
1752         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1753         if (!drm_detect_monitor_audio(nv_connector->edid))
1754                 return;
1755
1756         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1757         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1758
1759         nvif_mthd(disp->disp, 0, &args,
1760                   sizeof(args.base) + drm_eld_size(args.data));
1761 }
1762
1763 static void
1764 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1765 {
1766         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1767         struct nv50_disp *disp = nv50_disp(encoder->dev);
1768         struct {
1769                 struct nv50_disp_mthd_v1 base;
1770                 struct nv50_disp_sor_hda_eld_v0 eld;
1771         } args = {
1772                 .base.version = 1,
1773                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1774                 .base.hasht   = nv_encoder->dcb->hasht,
1775                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1776                                 (0x0100 << nv_crtc->index),
1777         };
1778
1779         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1780 }
1781
1782 /******************************************************************************
1783  * HDMI
1784  *****************************************************************************/
1785 static void
1786 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1787 {
1788         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1789         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1790         struct nv50_disp *disp = nv50_disp(encoder->dev);
1791         struct {
1792                 struct nv50_disp_mthd_v1 base;
1793                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1794         } args = {
1795                 .base.version = 1,
1796                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1797                 .base.hasht  = nv_encoder->dcb->hasht,
1798                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1799                                (0x0100 << nv_crtc->index),
1800                 .pwr.state = 1,
1801                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1802         };
1803         struct nouveau_connector *nv_connector;
1804         u32 max_ac_packet;
1805
1806         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1807         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1808                 return;
1809
1810         max_ac_packet  = mode->htotal - mode->hdisplay;
1811         max_ac_packet -= args.pwr.rekey;
1812         max_ac_packet -= 18; /* constant from tegra */
1813         args.pwr.max_ac_packet = max_ac_packet / 32;
1814
1815         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1816         nv50_audio_mode_set(encoder, mode);
1817 }
1818
1819 static void
1820 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1821 {
1822         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1823         struct nv50_disp *disp = nv50_disp(encoder->dev);
1824         struct {
1825                 struct nv50_disp_mthd_v1 base;
1826                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1827         } args = {
1828                 .base.version = 1,
1829                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1830                 .base.hasht  = nv_encoder->dcb->hasht,
1831                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1832                                (0x0100 << nv_crtc->index),
1833         };
1834
1835         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1836 }
1837
1838 /******************************************************************************
1839  * SOR
1840  *****************************************************************************/
1841 static void
1842 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1843 {
1844         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1845         struct nv50_disp *disp = nv50_disp(encoder->dev);
1846         struct {
1847                 struct nv50_disp_mthd_v1 base;
1848                 struct nv50_disp_sor_pwr_v0 pwr;
1849         } args = {
1850                 .base.version = 1,
1851                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1852                 .base.hasht  = nv_encoder->dcb->hasht,
1853                 .base.hashm  = nv_encoder->dcb->hashm,
1854                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1855         };
1856         struct {
1857                 struct nv50_disp_mthd_v1 base;
1858                 struct nv50_disp_sor_dp_pwr_v0 pwr;
1859         } link = {
1860                 .base.version = 1,
1861                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1862                 .base.hasht  = nv_encoder->dcb->hasht,
1863                 .base.hashm  = nv_encoder->dcb->hashm,
1864                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1865         };
1866         struct drm_device *dev = encoder->dev;
1867         struct drm_encoder *partner;
1868
1869         nv_encoder->last_dpms = mode;
1870
1871         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1872                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1873
1874                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1875                         continue;
1876
1877                 if (nv_partner != nv_encoder &&
1878                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1879                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1880                                 return;
1881                         break;
1882                 }
1883         }
1884
1885         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1886                 args.pwr.state = 1;
1887                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1888                 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1889         } else {
1890                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1891         }
1892 }
1893
1894 static void
1895 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1896 {
1897         struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1898         u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1899         if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1900                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1901                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1902                         evo_data(push, (nv_encoder->ctrl = temp));
1903                 } else {
1904                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1905                         evo_data(push, (nv_encoder->ctrl = temp));
1906                 }
1907                 evo_kick(push, mast);
1908         }
1909 }
1910
1911 static void
1912 nv50_sor_disconnect(struct drm_encoder *encoder)
1913 {
1914         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1915         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1916
1917         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1918         nv_encoder->crtc = NULL;
1919
1920         if (nv_crtc) {
1921                 nv50_crtc_prepare(&nv_crtc->base);
1922                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1923                 nv50_audio_disconnect(encoder, nv_crtc);
1924                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1925         }
1926 }
1927
1928 static void
1929 nv50_sor_commit(struct drm_encoder *encoder)
1930 {
1931 }
1932
1933 static void
1934 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1935                   struct drm_display_mode *mode)
1936 {
1937         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1938         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1939         struct {
1940                 struct nv50_disp_mthd_v1 base;
1941                 struct nv50_disp_sor_lvds_script_v0 lvds;
1942         } lvds = {
1943                 .base.version = 1,
1944                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1945                 .base.hasht   = nv_encoder->dcb->hasht,
1946                 .base.hashm   = nv_encoder->dcb->hashm,
1947         };
1948         struct nv50_disp *disp = nv50_disp(encoder->dev);
1949         struct nv50_mast *mast = nv50_mast(encoder->dev);
1950         struct drm_device *dev = encoder->dev;
1951         struct nouveau_drm *drm = nouveau_drm(dev);
1952         struct nouveau_connector *nv_connector;
1953         struct nvbios *bios = &drm->vbios;
1954         u32 mask, ctrl;
1955         u8 owner = 1 << nv_crtc->index;
1956         u8 proto = 0xf;
1957         u8 depth = 0x0;
1958
1959         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1960         nv_encoder->crtc = encoder->crtc;
1961
1962         switch (nv_encoder->dcb->type) {
1963         case DCB_OUTPUT_TMDS:
1964                 if (nv_encoder->dcb->sorconf.link & 1) {
1965                         proto = 0x1;
1966                         /* Only enable dual-link if:
1967                          *  - Need to (i.e. rate > 165MHz)
1968                          *  - DCB says we can
1969                          *  - Not an HDMI monitor, since there's no dual-link
1970                          *    on HDMI.
1971                          */
1972                         if (mode->clock >= 165000 &&
1973                             nv_encoder->dcb->duallink_possible &&
1974                             !drm_detect_hdmi_monitor(nv_connector->edid))
1975                                 proto |= 0x4;
1976                 } else {
1977                         proto = 0x2;
1978                 }
1979
1980                 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1981                 break;
1982         case DCB_OUTPUT_LVDS:
1983                 proto = 0x0;
1984
1985                 if (bios->fp_no_ddc) {
1986                         if (bios->fp.dual_link)
1987                                 lvds.lvds.script |= 0x0100;
1988                         if (bios->fp.if_is_24bit)
1989                                 lvds.lvds.script |= 0x0200;
1990                 } else {
1991                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1992                                 if (((u8 *)nv_connector->edid)[121] == 2)
1993                                         lvds.lvds.script |= 0x0100;
1994                         } else
1995                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1996                                 lvds.lvds.script |= 0x0100;
1997                         }
1998
1999                         if (lvds.lvds.script & 0x0100) {
2000                                 if (bios->fp.strapless_is_24bit & 2)
2001                                         lvds.lvds.script |= 0x0200;
2002                         } else {
2003                                 if (bios->fp.strapless_is_24bit & 1)
2004                                         lvds.lvds.script |= 0x0200;
2005                         }
2006
2007                         if (nv_connector->base.display_info.bpc == 8)
2008                                 lvds.lvds.script |= 0x0200;
2009                 }
2010
2011                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
2012                 break;
2013         case DCB_OUTPUT_DP:
2014                 if (nv_connector->base.display_info.bpc == 6) {
2015                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
2016                         depth = 0x2;
2017                 } else
2018                 if (nv_connector->base.display_info.bpc == 8) {
2019                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
2020                         depth = 0x5;
2021                 } else {
2022                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
2023                         depth = 0x6;
2024                 }
2025
2026                 if (nv_encoder->dcb->sorconf.link & 1)
2027                         proto = 0x8;
2028                 else
2029                         proto = 0x9;
2030                 nv50_audio_mode_set(encoder, mode);
2031                 break;
2032         default:
2033                 BUG_ON(1);
2034                 break;
2035         }
2036
2037         nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
2038
2039         if (nv50_vers(mast) >= GF110_DISP) {
2040                 u32 *push = evo_wait(mast, 3);
2041                 if (push) {
2042                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2043                         u32 syncs = 0x00000001;
2044
2045                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2046                                 syncs |= 0x00000008;
2047                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2048                                 syncs |= 0x00000010;
2049
2050                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2051                                 magic |= 0x00000001;
2052
2053                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2054                         evo_data(push, syncs | (depth << 6));
2055                         evo_data(push, magic);
2056                         evo_kick(push, mast);
2057                 }
2058
2059                 ctrl = proto << 8;
2060                 mask = 0x00000f00;
2061         } else {
2062                 ctrl = (depth << 16) | (proto << 8);
2063                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2064                         ctrl |= 0x00001000;
2065                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2066                         ctrl |= 0x00002000;
2067                 mask = 0x000f3f00;
2068         }
2069
2070         nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2071 }
2072
2073 static void
2074 nv50_sor_destroy(struct drm_encoder *encoder)
2075 {
2076         drm_encoder_cleanup(encoder);
2077         kfree(encoder);
2078 }
2079
2080 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2081         .dpms = nv50_sor_dpms,
2082         .mode_fixup = nv50_encoder_mode_fixup,
2083         .prepare = nv50_sor_disconnect,
2084         .commit = nv50_sor_commit,
2085         .mode_set = nv50_sor_mode_set,
2086         .disable = nv50_sor_disconnect,
2087         .get_crtc = nv50_display_crtc_get,
2088 };
2089
2090 static const struct drm_encoder_funcs nv50_sor_func = {
2091         .destroy = nv50_sor_destroy,
2092 };
2093
2094 static int
2095 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2096 {
2097         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2098         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2099         struct nouveau_encoder *nv_encoder;
2100         struct drm_encoder *encoder;
2101         int type;
2102
2103         switch (dcbe->type) {
2104         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2105         case DCB_OUTPUT_TMDS:
2106         case DCB_OUTPUT_DP:
2107         default:
2108                 type = DRM_MODE_ENCODER_TMDS;
2109                 break;
2110         }
2111
2112         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2113         if (!nv_encoder)
2114                 return -ENOMEM;
2115         nv_encoder->dcb = dcbe;
2116         nv_encoder->or = ffs(dcbe->or) - 1;
2117         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2118
2119         if (dcbe->type == DCB_OUTPUT_DP) {
2120                 struct nvkm_i2c_aux *aux =
2121                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
2122                 if (aux) {
2123                         nv_encoder->i2c = &aux->i2c;
2124                         nv_encoder->aux = aux;
2125                 }
2126         } else {
2127                 struct nvkm_i2c_bus *bus =
2128                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2129                 if (bus)
2130                         nv_encoder->i2c = &bus->i2c;
2131         }
2132
2133         encoder = to_drm_encoder(nv_encoder);
2134         encoder->possible_crtcs = dcbe->heads;
2135         encoder->possible_clones = 0;
2136         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, NULL);
2137         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2138
2139         drm_mode_connector_attach_encoder(connector, encoder);
2140         return 0;
2141 }
2142
2143 /******************************************************************************
2144  * PIOR
2145  *****************************************************************************/
2146
2147 static void
2148 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2149 {
2150         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2151         struct nv50_disp *disp = nv50_disp(encoder->dev);
2152         struct {
2153                 struct nv50_disp_mthd_v1 base;
2154                 struct nv50_disp_pior_pwr_v0 pwr;
2155         } args = {
2156                 .base.version = 1,
2157                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2158                 .base.hasht  = nv_encoder->dcb->hasht,
2159                 .base.hashm  = nv_encoder->dcb->hashm,
2160                 .pwr.state = mode == DRM_MODE_DPMS_ON,
2161                 .pwr.type = nv_encoder->dcb->type,
2162         };
2163
2164         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2165 }
2166
2167 static bool
2168 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2169                      const struct drm_display_mode *mode,
2170                      struct drm_display_mode *adjusted_mode)
2171 {
2172         if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2173                 return false;
2174         adjusted_mode->clock *= 2;
2175         return true;
2176 }
2177
2178 static void
2179 nv50_pior_commit(struct drm_encoder *encoder)
2180 {
2181 }
2182
2183 static void
2184 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2185                    struct drm_display_mode *adjusted_mode)
2186 {
2187         struct nv50_mast *mast = nv50_mast(encoder->dev);
2188         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2189         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2190         struct nouveau_connector *nv_connector;
2191         u8 owner = 1 << nv_crtc->index;
2192         u8 proto, depth;
2193         u32 *push;
2194
2195         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2196         switch (nv_connector->base.display_info.bpc) {
2197         case 10: depth = 0x6; break;
2198         case  8: depth = 0x5; break;
2199         case  6: depth = 0x2; break;
2200         default: depth = 0x0; break;
2201         }
2202
2203         switch (nv_encoder->dcb->type) {
2204         case DCB_OUTPUT_TMDS:
2205         case DCB_OUTPUT_DP:
2206                 proto = 0x0;
2207                 break;
2208         default:
2209                 BUG_ON(1);
2210                 break;
2211         }
2212
2213         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2214
2215         push = evo_wait(mast, 8);
2216         if (push) {
2217                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2218                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2219                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2220                                 ctrl |= 0x00001000;
2221                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2222                                 ctrl |= 0x00002000;
2223                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2224                         evo_data(push, ctrl);
2225                 }
2226
2227                 evo_kick(push, mast);
2228         }
2229
2230         nv_encoder->crtc = encoder->crtc;
2231 }
2232
2233 static void
2234 nv50_pior_disconnect(struct drm_encoder *encoder)
2235 {
2236         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2237         struct nv50_mast *mast = nv50_mast(encoder->dev);
2238         const int or = nv_encoder->or;
2239         u32 *push;
2240
2241         if (nv_encoder->crtc) {
2242                 nv50_crtc_prepare(nv_encoder->crtc);
2243
2244                 push = evo_wait(mast, 4);
2245                 if (push) {
2246                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2247                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2248                                 evo_data(push, 0x00000000);
2249                         }
2250                         evo_kick(push, mast);
2251                 }
2252         }
2253
2254         nv_encoder->crtc = NULL;
2255 }
2256
2257 static void
2258 nv50_pior_destroy(struct drm_encoder *encoder)
2259 {
2260         drm_encoder_cleanup(encoder);
2261         kfree(encoder);
2262 }
2263
2264 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2265         .dpms = nv50_pior_dpms,
2266         .mode_fixup = nv50_pior_mode_fixup,
2267         .prepare = nv50_pior_disconnect,
2268         .commit = nv50_pior_commit,
2269         .mode_set = nv50_pior_mode_set,
2270         .disable = nv50_pior_disconnect,
2271         .get_crtc = nv50_display_crtc_get,
2272 };
2273
2274 static const struct drm_encoder_funcs nv50_pior_func = {
2275         .destroy = nv50_pior_destroy,
2276 };
2277
2278 static int
2279 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2280 {
2281         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2282         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2283         struct nvkm_i2c_bus *bus = NULL;
2284         struct nvkm_i2c_aux *aux = NULL;
2285         struct i2c_adapter *ddc;
2286         struct nouveau_encoder *nv_encoder;
2287         struct drm_encoder *encoder;
2288         int type;
2289
2290         switch (dcbe->type) {
2291         case DCB_OUTPUT_TMDS:
2292                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2293                 ddc  = bus ? &bus->i2c : NULL;
2294                 type = DRM_MODE_ENCODER_TMDS;
2295                 break;
2296         case DCB_OUTPUT_DP:
2297                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2298                 ddc  = aux ? &aux->i2c : NULL;
2299                 type = DRM_MODE_ENCODER_TMDS;
2300                 break;
2301         default:
2302                 return -ENODEV;
2303         }
2304
2305         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2306         if (!nv_encoder)
2307                 return -ENOMEM;
2308         nv_encoder->dcb = dcbe;
2309         nv_encoder->or = ffs(dcbe->or) - 1;
2310         nv_encoder->i2c = ddc;
2311         nv_encoder->aux = aux;
2312
2313         encoder = to_drm_encoder(nv_encoder);
2314         encoder->possible_crtcs = dcbe->heads;
2315         encoder->possible_clones = 0;
2316         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, NULL);
2317         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2318
2319         drm_mode_connector_attach_encoder(connector, encoder);
2320         return 0;
2321 }
2322
2323 /******************************************************************************
2324  * Framebuffer
2325  *****************************************************************************/
2326
2327 static void
2328 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2329 {
2330         int i;
2331         for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2332                 nvif_object_fini(&fbdma->base[i]);
2333         nvif_object_fini(&fbdma->core);
2334         list_del(&fbdma->head);
2335         kfree(fbdma);
2336 }
2337
2338 static int
2339 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2340 {
2341         struct nouveau_drm *drm = nouveau_drm(dev);
2342         struct nv50_disp *disp = nv50_disp(dev);
2343         struct nv50_mast *mast = nv50_mast(dev);
2344         struct __attribute__ ((packed)) {
2345                 struct nv_dma_v0 base;
2346                 union {
2347                         struct nv50_dma_v0 nv50;
2348                         struct gf100_dma_v0 gf100;
2349                         struct gf119_dma_v0 gf119;
2350                 };
2351         } args = {};
2352         struct nv50_fbdma *fbdma;
2353         struct drm_crtc *crtc;
2354         u32 size = sizeof(args.base);
2355         int ret;
2356
2357         list_for_each_entry(fbdma, &disp->fbdma, head) {
2358                 if (fbdma->core.handle == name)
2359                         return 0;
2360         }
2361
2362         fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2363         if (!fbdma)
2364                 return -ENOMEM;
2365         list_add(&fbdma->head, &disp->fbdma);
2366
2367         args.base.target = NV_DMA_V0_TARGET_VRAM;
2368         args.base.access = NV_DMA_V0_ACCESS_RDWR;
2369         args.base.start = offset;
2370         args.base.limit = offset + length - 1;
2371
2372         if (drm->device.info.chipset < 0x80) {
2373                 args.nv50.part = NV50_DMA_V0_PART_256;
2374                 size += sizeof(args.nv50);
2375         } else
2376         if (drm->device.info.chipset < 0xc0) {
2377                 args.nv50.part = NV50_DMA_V0_PART_256;
2378                 args.nv50.kind = kind;
2379                 size += sizeof(args.nv50);
2380         } else
2381         if (drm->device.info.chipset < 0xd0) {
2382                 args.gf100.kind = kind;
2383                 size += sizeof(args.gf100);
2384         } else {
2385                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2386                 args.gf119.kind = kind;
2387                 size += sizeof(args.gf119);
2388         }
2389
2390         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2391                 struct nv50_head *head = nv50_head(crtc);
2392                 int ret = nvif_object_init(&head->sync.base.base.user, name,
2393                                            NV_DMA_IN_MEMORY, &args, size,
2394                                            &fbdma->base[head->base.index]);
2395                 if (ret) {
2396                         nv50_fbdma_fini(fbdma);
2397                         return ret;
2398                 }
2399         }
2400
2401         ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY,
2402                                &args, size, &fbdma->core);
2403         if (ret) {
2404                 nv50_fbdma_fini(fbdma);
2405                 return ret;
2406         }
2407
2408         return 0;
2409 }
2410
2411 static void
2412 nv50_fb_dtor(struct drm_framebuffer *fb)
2413 {
2414 }
2415
2416 static int
2417 nv50_fb_ctor(struct drm_framebuffer *fb)
2418 {
2419         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2420         struct nouveau_drm *drm = nouveau_drm(fb->dev);
2421         struct nouveau_bo *nvbo = nv_fb->nvbo;
2422         struct nv50_disp *disp = nv50_disp(fb->dev);
2423         u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2424         u8 tile = nvbo->tile_mode;
2425
2426         if (drm->device.info.chipset >= 0xc0)
2427                 tile >>= 4; /* yep.. */
2428
2429         switch (fb->depth) {
2430         case  8: nv_fb->r_format = 0x1e00; break;
2431         case 15: nv_fb->r_format = 0xe900; break;
2432         case 16: nv_fb->r_format = 0xe800; break;
2433         case 24:
2434         case 32: nv_fb->r_format = 0xcf00; break;
2435         case 30: nv_fb->r_format = 0xd100; break;
2436         default:
2437                  NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2438                  return -EINVAL;
2439         }
2440
2441         if (disp->disp->oclass < G82_DISP) {
2442                 nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2443                                             (fb->pitches[0] | 0x00100000);
2444                 nv_fb->r_format |= kind << 16;
2445         } else
2446         if (disp->disp->oclass < GF110_DISP) {
2447                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2448                                            (fb->pitches[0] | 0x00100000);
2449         } else {
2450                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2451                                            (fb->pitches[0] | 0x01000000);
2452         }
2453         nv_fb->r_handle = 0xffff0000 | kind;
2454
2455         return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2456                                drm->device.info.ram_user, kind);
2457 }
2458
2459 /******************************************************************************
2460  * Init
2461  *****************************************************************************/
2462
2463 void
2464 nv50_display_fini(struct drm_device *dev)
2465 {
2466 }
2467
2468 int
2469 nv50_display_init(struct drm_device *dev)
2470 {
2471         struct nv50_disp *disp = nv50_disp(dev);
2472         struct drm_crtc *crtc;
2473         u32 *push;
2474
2475         push = evo_wait(nv50_mast(dev), 32);
2476         if (!push)
2477                 return -EBUSY;
2478
2479         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2480                 struct nv50_sync *sync = nv50_sync(crtc);
2481
2482                 nv50_crtc_lut_load(crtc);
2483                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2484         }
2485
2486         evo_mthd(push, 0x0088, 1);
2487         evo_data(push, nv50_mast(dev)->base.sync.handle);
2488         evo_kick(push, nv50_mast(dev));
2489         return 0;
2490 }
2491
2492 void
2493 nv50_display_destroy(struct drm_device *dev)
2494 {
2495         struct nv50_disp *disp = nv50_disp(dev);
2496         struct nv50_fbdma *fbdma, *fbtmp;
2497
2498         list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2499                 nv50_fbdma_fini(fbdma);
2500         }
2501
2502         nv50_dmac_destroy(&disp->mast.base, disp->disp);
2503
2504         nouveau_bo_unmap(disp->sync);
2505         if (disp->sync)
2506                 nouveau_bo_unpin(disp->sync);
2507         nouveau_bo_ref(NULL, &disp->sync);
2508
2509         nouveau_display(dev)->priv = NULL;
2510         kfree(disp);
2511 }
2512
2513 int
2514 nv50_display_create(struct drm_device *dev)
2515 {
2516         struct nvif_device *device = &nouveau_drm(dev)->device;
2517         struct nouveau_drm *drm = nouveau_drm(dev);
2518         struct dcb_table *dcb = &drm->vbios.dcb;
2519         struct drm_connector *connector, *tmp;
2520         struct nv50_disp *disp;
2521         struct dcb_output *dcbe;
2522         int crtcs, ret, i;
2523
2524         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2525         if (!disp)
2526                 return -ENOMEM;
2527         INIT_LIST_HEAD(&disp->fbdma);
2528
2529         nouveau_display(dev)->priv = disp;
2530         nouveau_display(dev)->dtor = nv50_display_destroy;
2531         nouveau_display(dev)->init = nv50_display_init;
2532         nouveau_display(dev)->fini = nv50_display_fini;
2533         nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2534         nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2535         disp->disp = &nouveau_display(dev)->disp;
2536
2537         /* small shared memory area we use for notifiers and semaphores */
2538         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2539                              0, 0x0000, NULL, NULL, &disp->sync);
2540         if (!ret) {
2541                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2542                 if (!ret) {
2543                         ret = nouveau_bo_map(disp->sync);
2544                         if (ret)
2545                                 nouveau_bo_unpin(disp->sync);
2546                 }
2547                 if (ret)
2548                         nouveau_bo_ref(NULL, &disp->sync);
2549         }
2550
2551         if (ret)
2552                 goto out;
2553
2554         /* allocate master evo channel */
2555         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
2556                               &disp->mast);
2557         if (ret)
2558                 goto out;
2559
2560         /* create crtc objects to represent the hw heads */
2561         if (disp->disp->oclass >= GF110_DISP)
2562                 crtcs = nvif_rd32(&device->object, 0x022448);
2563         else
2564                 crtcs = 2;
2565
2566         for (i = 0; i < crtcs; i++) {
2567                 ret = nv50_crtc_create(dev, i);
2568                 if (ret)
2569                         goto out;
2570         }
2571
2572         /* create encoder/connector objects based on VBIOS DCB table */
2573         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2574                 connector = nouveau_connector_create(dev, dcbe->connector);
2575                 if (IS_ERR(connector))
2576                         continue;
2577
2578                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2579                         switch (dcbe->type) {
2580                         case DCB_OUTPUT_TMDS:
2581                         case DCB_OUTPUT_LVDS:
2582                         case DCB_OUTPUT_DP:
2583                                 ret = nv50_sor_create(connector, dcbe);
2584                                 break;
2585                         case DCB_OUTPUT_ANALOG:
2586                                 ret = nv50_dac_create(connector, dcbe);
2587                                 break;
2588                         default:
2589                                 ret = -ENODEV;
2590                                 break;
2591                         }
2592                 } else {
2593                         ret = nv50_pior_create(connector, dcbe);
2594                 }
2595
2596                 if (ret) {
2597                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2598                                      dcbe->location, dcbe->type,
2599                                      ffs(dcbe->or) - 1, ret);
2600                         ret = 0;
2601                 }
2602         }
2603
2604         /* cull any connectors we created that don't have an encoder */
2605         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2606                 if (connector->encoder_ids[0])
2607                         continue;
2608
2609                 NV_WARN(drm, "%s has no encoders, removing\n",
2610                         connector->name);
2611                 connector->funcs->destroy(connector);
2612         }
2613
2614 out:
2615         if (ret)
2616                 nv50_display_destroy(dev);
2617         return ret;
2618 }