drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_plane_helper.h>
  30 #include <drm/drm_dp_helper.h>
  31 #include <drm/drm_fb_helper.h>
  32
  33 #include <nvif/class.h>
  34
  35 #include "nouveau_drm.h"
  36 #include "nouveau_dma.h"
  37 #include "nouveau_gem.h"
  38 #include "nouveau_connector.h"
  39 #include "nouveau_encoder.h"
  40 #include "nouveau_crtc.h"
  41 #include "nouveau_fence.h"
  42 #include "nv50_display.h"
  43
  44 #define EVO_DMA_NR 9
  45
  46 #define EVO_MASTER  (0x00)
  47 #define EVO_FLIP(c) (0x01 + (c))
  48 #define EVO_OVLY(c) (0x05 + (c))
  49 #define EVO_OIMM(c) (0x09 + (c))
  50 #define EVO_CURS(c) (0x0d + (c))
  51
  52 /* offsets in shared sync bo of various structures */
  53 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  54 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  55 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  56 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  57
  58 /******************************************************************************
  59  * EVO channel
  60  *****************************************************************************/
  61
  62 struct nv50_chan {
  63         struct nvif_object user;
  64         struct nvif_device *device;
  65 };
  66
  67 static int
  68 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
  69                  const s32 *oclass, u8 head, void *data, u32 size,
  70                  struct nv50_chan *chan)
  71 {
  72         struct nvif_sclass *sclass;
  73         int ret, i, n;
  74
  75         chan->device = device;
  76
  77         ret = n = nvif_object_sclass_get(disp, &sclass);
  78         if (ret < 0)
  79                 return ret;
  80
  81         while (oclass[0]) {
  82                 for (i = 0; i < n; i++) {
  83                         if (sclass[i].oclass == oclass[0]) {
  84                                 ret = nvif_object_init(disp, 0, oclass[0],
  85                                                        data, size, &chan->user);
  86                                 if (ret == 0)
  87                                         nvif_object_map(&chan->user);
  88                                 nvif_object_sclass_put(&sclass);
  89                                 return ret;
  90                         }
  91                 }
  92                 oclass++;
  93         }
  94
  95         nvif_object_sclass_put(&sclass);
  96         return -ENOSYS;
  97 }
  98
  99 static void
 100 nv50_chan_destroy(struct nv50_chan *chan)
 101 {
 102         nvif_object_fini(&chan->user);
 103 }
 104
 105 /******************************************************************************
 106  * PIO EVO channel
 107  *****************************************************************************/
 108
 109 struct nv50_pioc {
 110         struct nv50_chan base;
 111 };
 112
 113 static void
 114 nv50_pioc_destroy(struct nv50_pioc *pioc)
 115 {
 116         nv50_chan_destroy(&pioc->base);
 117 }
 118
 119 static int
 120 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 121                  const s32 *oclass, u8 head, void *data, u32 size,
 122                  struct nv50_pioc *pioc)
 123 {
 124         return nv50_chan_create(device, disp, oclass, head, data, size,
 125                                 &pioc->base);
 126 }
 127
 128 /******************************************************************************
 129  * Cursor Immediate
 130  *****************************************************************************/
 131
 132 struct nv50_curs {
 133         struct nv50_pioc base;
 134 };
 135
 136 static int
 137 nv50_curs_create(struct nvif_device *device, struct nvif_object *disp,
 138                  int head, struct nv50_curs *curs)
 139 {
 140         struct nv50_disp_cursor_v0 args = {
 141                 .head = head,
 142         };
 143         static const s32 oclass[] = {
 144                 GK104_DISP_CURSOR,
 145                 GF110_DISP_CURSOR,
 146                 GT214_DISP_CURSOR,
 147                 G82_DISP_CURSOR,
 148                 NV50_DISP_CURSOR,
 149                 0
 150         };
 151
 152         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 153                                 &curs->base);
 154 }
 155
 156 /******************************************************************************
 157  * Overlay Immediate
 158  *****************************************************************************/
 159
 160 struct nv50_oimm {
 161         struct nv50_pioc base;
 162 };
 163
 164 static int
 165 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 166                  int head, struct nv50_oimm *oimm)
 167 {
 168         struct nv50_disp_cursor_v0 args = {
 169                 .head = head,
 170         };
 171         static const s32 oclass[] = {
 172                 GK104_DISP_OVERLAY,
 173                 GF110_DISP_OVERLAY,
 174                 GT214_DISP_OVERLAY,
 175                 G82_DISP_OVERLAY,
 176                 NV50_DISP_OVERLAY,
 177                 0
 178         };
 179
 180         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 181                                 &oimm->base);
 182 }
 183
 184 /******************************************************************************
 185  * DMA EVO channel
 186  *****************************************************************************/
 187
 188 struct nv50_dmac {
 189         struct nv50_chan base;
 190         dma_addr_t handle;
 191         u32 *ptr;
 192
 193         struct nvif_object sync;
 194         struct nvif_object vram;
 195
 196         /* Protects against concurrent pushbuf access to this channel, lock is
 197          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 198          * dropped again by evo_kick. */
 199         struct mutex lock;
 200 };
 201
 202 static void
 203 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 204 {
 205         struct nvif_device *device = dmac->base.device;
 206
 207         nvif_object_fini(&dmac->vram);
 208         nvif_object_fini(&dmac->sync);
 209
 210         nv50_chan_destroy(&dmac->base);
 211
 212         if (dmac->ptr) {
 213                 struct device *dev = nvxx_device(device)->dev;
 214                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 215         }
 216 }
 217
 218 static int
 219 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 220                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 221                  struct nv50_dmac *dmac)
 222 {
 223         struct nv50_disp_core_channel_dma_v0 *args = data;
 224         struct nvif_object pushbuf;
 225         int ret;
 226
 227         mutex_init(&dmac->lock);
 228
 229         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 230                                        &dmac->handle, GFP_KERNEL);
 231         if (!dmac->ptr)
 232                 return -ENOMEM;
 233
 234         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 235                                &(struct nv_dma_v0) {
 236                                         .target = NV_DMA_V0_TARGET_PCI_US,
 237                                         .access = NV_DMA_V0_ACCESS_RD,
 238                                         .start = dmac->handle + 0x0000,
 239                                         .limit = dmac->handle + 0x0fff,
 240                                }, sizeof(struct nv_dma_v0), &pushbuf);
 241         if (ret)
 242                 return ret;
 243
 244         args->pushbuf = nvif_handle(&pushbuf);
 245
 246         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 247                                &dmac->base);
 248         nvif_object_fini(&pushbuf);
 249         if (ret)
 250                 return ret;
 251
 252         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 253                                &(struct nv_dma_v0) {
 254                                         .target = NV_DMA_V0_TARGET_VRAM,
 255                                         .access = NV_DMA_V0_ACCESS_RDWR,
 256                                         .start = syncbuf + 0x0000,
 257                                         .limit = syncbuf + 0x0fff,
 258                                }, sizeof(struct nv_dma_v0),
 259                                &dmac->sync);
 260         if (ret)
 261                 return ret;
 262
 263         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 264                                &(struct nv_dma_v0) {
 265                                         .target = NV_DMA_V0_TARGET_VRAM,
 266                                         .access = NV_DMA_V0_ACCESS_RDWR,
 267                                         .start = 0,
 268                                         .limit = device->info.ram_user - 1,
 269                                }, sizeof(struct nv_dma_v0),
 270                                &dmac->vram);
 271         if (ret)
 272                 return ret;
 273
 274         return ret;
 275 }
 276
 277 /******************************************************************************
 278  * Core
 279  *****************************************************************************/
 280
 281 struct nv50_mast {
 282         struct nv50_dmac base;
 283 };
 284
 285 static int
 286 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 287                  u64 syncbuf, struct nv50_mast *core)
 288 {
 289         struct nv50_disp_core_channel_dma_v0 args = {
 290                 .pushbuf = 0xb0007d00,
 291         };
 292         static const s32 oclass[] = {
 293                 GM204_DISP_CORE_CHANNEL_DMA,
 294                 GM107_DISP_CORE_CHANNEL_DMA,
 295                 GK110_DISP_CORE_CHANNEL_DMA,
 296                 GK104_DISP_CORE_CHANNEL_DMA,
 297                 GF110_DISP_CORE_CHANNEL_DMA,
 298                 GT214_DISP_CORE_CHANNEL_DMA,
 299                 GT206_DISP_CORE_CHANNEL_DMA,
 300                 GT200_DISP_CORE_CHANNEL_DMA,
 301                 G82_DISP_CORE_CHANNEL_DMA,
 302                 NV50_DISP_CORE_CHANNEL_DMA,
 303                 0
 304         };
 305
 306         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 307                                 syncbuf, &core->base);
 308 }
 309
 310 /******************************************************************************
 311  * Base
 312  *****************************************************************************/
 313
 314 struct nv50_sync {
 315         struct nv50_dmac base;
 316         u32 addr;
 317         u32 data;
 318 };
 319
 320 static int
 321 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 322                  int head, u64 syncbuf, struct nv50_sync *base)
 323 {
 324         struct nv50_disp_base_channel_dma_v0 args = {
 325                 .pushbuf = 0xb0007c00 | head,
 326                 .head = head,
 327         };
 328         static const s32 oclass[] = {
 329                 GK110_DISP_BASE_CHANNEL_DMA,
 330                 GK104_DISP_BASE_CHANNEL_DMA,
 331                 GF110_DISP_BASE_CHANNEL_DMA,
 332                 GT214_DISP_BASE_CHANNEL_DMA,
 333                 GT200_DISP_BASE_CHANNEL_DMA,
 334                 G82_DISP_BASE_CHANNEL_DMA,
 335                 NV50_DISP_BASE_CHANNEL_DMA,
 336                 0
 337         };
 338
 339         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 340                                 syncbuf, &base->base);
 341 }
 342
 343 /******************************************************************************
 344  * Overlay
 345  *****************************************************************************/
 346
 347 struct nv50_ovly {
 348         struct nv50_dmac base;
 349 };
 350
 351 static int
 352 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 353                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 354 {
 355         struct nv50_disp_overlay_channel_dma_v0 args = {
 356                 .pushbuf = 0xb0007e00 | head,
 357                 .head = head,
 358         };
 359         static const s32 oclass[] = {
 360                 GK104_DISP_OVERLAY_CONTROL_DMA,
 361                 GF110_DISP_OVERLAY_CONTROL_DMA,
 362                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 363                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 364                 G82_DISP_OVERLAY_CHANNEL_DMA,
 365                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 366                 0
 367         };
 368
 369         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 370                                 syncbuf, &ovly->base);
 371 }
 372
 373 struct nv50_head {
 374         struct nouveau_crtc base;
 375         struct nouveau_bo *image;
 376         struct nv50_curs curs;
 377         struct nv50_sync sync;
 378         struct nv50_ovly ovly;
 379         struct nv50_oimm oimm;
 380 };
 381
 382 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 383 #define nv50_curs(c) (&nv50_head(c)->curs)
 384 #define nv50_sync(c) (&nv50_head(c)->sync)
 385 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 386 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 387 #define nv50_chan(c) (&(c)->base.base)
 388 #define nv50_vers(c) nv50_chan(c)->user.oclass
 389
 390 struct nv50_fbdma {
 391         struct list_head head;
 392         struct nvif_object core;
 393         struct nvif_object base[4];
 394 };
 395
 396 struct nv50_disp {
 397         struct nvif_object *disp;
 398         struct nv50_mast mast;
 399
 400         struct list_head fbdma;
 401
 402         struct nouveau_bo *sync;
 403 };
 404
 405 static struct nv50_disp *
 406 nv50_disp(struct drm_device *dev)
 407 {
 408         return nouveau_display(dev)->priv;
 409 }
 410
 411 #define nv50_mast(d) (&nv50_disp(d)->mast)
 412
 413 static struct drm_crtc *
 414 nv50_display_crtc_get(struct drm_encoder *encoder)
 415 {
 416         return nouveau_encoder(encoder)->crtc;
 417 }
 418
 419 /******************************************************************************
 420  * EVO channel helpers
 421  *****************************************************************************/
 422 static u32 *
 423 evo_wait(void *evoc, int nr)
 424 {
 425         struct nv50_dmac *dmac = evoc;
 426         struct nvif_device *device = dmac->base.device;
 427         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 428
 429         mutex_lock(&dmac->lock);
 430         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 431                 dmac->ptr[put] = 0x20000000;
 432
 433                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 434                 if (nvif_msec(device, 2000,
 435                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 436                                 break;
 437                 ) < 0) {
 438                         mutex_unlock(&dmac->lock);
 439                         printk(KERN_ERR "nouveau: evo channel stalled\n");
 440                         return NULL;
 441                 }
 442
 443                 put = 0;
 444         }
 445
 446         return dmac->ptr + put;
 447 }
 448
 449 static void
 450 evo_kick(u32 *push, void *evoc)
 451 {
 452         struct nv50_dmac *dmac = evoc;
 453         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 454         mutex_unlock(&dmac->lock);
 455 }
 456
 457 #if 1
 458 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 459 #define evo_data(p,d)   *((p)++) = (d)
 460 #else
 461 #define evo_mthd(p,m,s) do {                                                   \
 462         const u32 _m = (m), _s = (s);                                          \
 463         printk(KERN_ERR "%04x %d %s\n", _m, _s, __func__);                     \
 464         *((p)++) = ((_s << 18) | _m);                                          \
 465 } while(0)
 466 #define evo_data(p,d) do {                                                     \
 467         const u32 _d = (d);                                                    \
 468         printk(KERN_ERR "\t%08x\n", _d);                                       \
 469         *((p)++) = _d;                                                         \
 470 } while(0)
 471 #endif
 472
 473 static bool
 474 evo_sync_wait(void *data)
 475 {
 476         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 477                 return true;
 478         usleep_range(1, 2);
 479         return false;
 480 }
 481
 482 static int
 483 evo_sync(struct drm_device *dev)
 484 {
 485         struct nvif_device *device = &nouveau_drm(dev)->device;
 486         struct nv50_disp *disp = nv50_disp(dev);
 487         struct nv50_mast *mast = nv50_mast(dev);
 488         u32 *push = evo_wait(mast, 8);
 489         if (push) {
 490                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 491                 evo_mthd(push, 0x0084, 1);
 492                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 493                 evo_mthd(push, 0x0080, 2);
 494                 evo_data(push, 0x00000000);
 495                 evo_data(push, 0x00000000);
 496                 evo_kick(push, mast);
 497                 if (nvif_msec(device, 2000,
 498                         if (evo_sync_wait(disp->sync))
 499                                 break;
 500                 ) >= 0)
 501                         return 0;
 502         }
 503
 504         return -EBUSY;
 505 }
 506
 507 /******************************************************************************
 508  * Page flipping channel
 509  *****************************************************************************/
 510 struct nouveau_bo *
 511 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 512 {
 513         return nv50_disp(dev)->sync;
 514 }
 515
 516 struct nv50_display_flip {
 517         struct nv50_disp *disp;
 518         struct nv50_sync *chan;
 519 };
 520
 521 static bool
 522 nv50_display_flip_wait(void *data)
 523 {
 524         struct nv50_display_flip *flip = data;
 525         if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
 526                                               flip->chan->data)
 527                 return true;
 528         usleep_range(1, 2);
 529         return false;
 530 }
 531
 532 void
 533 nv50_display_flip_stop(struct drm_crtc *crtc)
 534 {
 535         struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
 536         struct nv50_display_flip flip = {
 537                 .disp = nv50_disp(crtc->dev),
 538                 .chan = nv50_sync(crtc),
 539         };
 540         u32 *push;
 541
 542         push = evo_wait(flip.chan, 8);
 543         if (push) {
 544                 evo_mthd(push, 0x0084, 1);
 545                 evo_data(push, 0x00000000);
 546                 evo_mthd(push, 0x0094, 1);
 547                 evo_data(push, 0x00000000);
 548                 evo_mthd(push, 0x00c0, 1);
 549                 evo_data(push, 0x00000000);
 550                 evo_mthd(push, 0x0080, 1);
 551                 evo_data(push, 0x00000000);
 552                 evo_kick(push, flip.chan);
 553         }
 554
 555         nvif_msec(device, 2000,
 556                 if (nv50_display_flip_wait(&flip))
 557                         break;
 558         );
 559 }
 560
 561 int
 562 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 563                        struct nouveau_channel *chan, u32 swap_interval)
 564 {
 565         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 566         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 567         struct nv50_head *head = nv50_head(crtc);
 568         struct nv50_sync *sync = nv50_sync(crtc);
 569         u32 *push;
 570         int ret;
 571
 572         if (crtc->primary->fb->width != fb->width ||
 573             crtc->primary->fb->height != fb->height)
 574                 return -EINVAL;
 575
 576         swap_interval <<= 4;
 577         if (swap_interval == 0)
 578                 swap_interval |= 0x100;
 579         if (chan == NULL)
 580                 evo_sync(crtc->dev);
 581
 582         push = evo_wait(sync, 128);
 583         if (unlikely(push == NULL))
 584                 return -EBUSY;
 585
 586         if (chan && chan->user.oclass < G82_CHANNEL_GPFIFO) {
 587                 ret = RING_SPACE(chan, 8);
 588                 if (ret)
 589                         return ret;
 590
 591                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 592                 OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 593                 OUT_RING  (chan, sync->addr ^ 0x10);
 594                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 595                 OUT_RING  (chan, sync->data + 1);
 596                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 597                 OUT_RING  (chan, sync->addr);
 598                 OUT_RING  (chan, sync->data);
 599         } else
 600         if (chan && chan->user.oclass < FERMI_CHANNEL_GPFIFO) {
 601                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 602                 ret = RING_SPACE(chan, 12);
 603                 if (ret)
 604                         return ret;
 605
 606                 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 607                 OUT_RING  (chan, chan->vram.handle);
 608                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 609                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 610                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 611                 OUT_RING  (chan, sync->data + 1);
 612                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
 613                 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 614                 OUT_RING  (chan, upper_32_bits(addr));
 615                 OUT_RING  (chan, lower_32_bits(addr));
 616                 OUT_RING  (chan, sync->data);
 617                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
 618         } else
 619         if (chan) {
 620                 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
 621                 ret = RING_SPACE(chan, 10);
 622                 if (ret)
 623                         return ret;
 624
 625                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 626                 OUT_RING  (chan, upper_32_bits(addr ^ 0x10));
 627                 OUT_RING  (chan, lower_32_bits(addr ^ 0x10));
 628                 OUT_RING  (chan, sync->data + 1);
 629                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
 630                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 631                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 632                 OUT_RING  (chan, upper_32_bits(addr));
 633                 OUT_RING  (chan, lower_32_bits(addr));
 634                 OUT_RING  (chan, sync->data);
 635                 OUT_RING  (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
 636                                  NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
 637         }
 638
 639         if (chan) {
 640                 sync->addr ^= 0x10;
 641                 sync->data++;
 642                 FIRE_RING (chan);
 643         }
 644
 645         /* queue the flip */
 646         evo_mthd(push, 0x0100, 1);
 647         evo_data(push, 0xfffe0000);
 648         evo_mthd(push, 0x0084, 1);
 649         evo_data(push, swap_interval);
 650         if (!(swap_interval & 0x00000100)) {
 651                 evo_mthd(push, 0x00e0, 1);
 652                 evo_data(push, 0x40000000);
 653         }
 654         evo_mthd(push, 0x0088, 4);
 655         evo_data(push, sync->addr);
 656         evo_data(push, sync->data++);
 657         evo_data(push, sync->data);
 658         evo_data(push, sync->base.sync.handle);
 659         evo_mthd(push, 0x00a0, 2);
 660         evo_data(push, 0x00000000);
 661         evo_data(push, 0x00000000);
 662         evo_mthd(push, 0x00c0, 1);
 663         evo_data(push, nv_fb->r_handle);
 664         evo_mthd(push, 0x0110, 2);
 665         evo_data(push, 0x00000000);
 666         evo_data(push, 0x00000000);
 667         if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
 668                 evo_mthd(push, 0x0800, 5);
 669                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 670                 evo_data(push, 0);
 671                 evo_data(push, (fb->height << 16) | fb->width);
 672                 evo_data(push, nv_fb->r_pitch);
 673                 evo_data(push, nv_fb->r_format);
 674         } else {
 675                 evo_mthd(push, 0x0400, 5);
 676                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 677                 evo_data(push, 0);
 678                 evo_data(push, (fb->height << 16) | fb->width);
 679                 evo_data(push, nv_fb->r_pitch);
 680                 evo_data(push, nv_fb->r_format);
 681         }
 682         evo_mthd(push, 0x0080, 1);
 683         evo_data(push, 0x00000000);
 684         evo_kick(push, sync);
 685
 686         nouveau_bo_ref(nv_fb->nvbo, &head->image);
 687         return 0;
 688 }
 689
 690 /******************************************************************************
 691  * CRTC
 692  *****************************************************************************/
 693 static int
 694 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 695 {
 696         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 697         struct nouveau_connector *nv_connector;
 698         struct drm_connector *connector;
 699         u32 *push, mode = 0x00;
 700
 701         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 702         connector = &nv_connector->base;
 703         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 704                 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
 705                         mode = DITHERING_MODE_DYNAMIC2X2;
 706         } else {
 707                 mode = nv_connector->dithering_mode;
 708         }
 709
 710         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 711                 if (connector->display_info.bpc >= 8)
 712                         mode |= DITHERING_DEPTH_8BPC;
 713         } else {
 714                 mode |= nv_connector->dithering_depth;
 715         }
 716
 717         push = evo_wait(mast, 4);
 718         if (push) {
 719                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 720                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 721                         evo_data(push, mode);
 722                 } else
 723                 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
 724                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 725                         evo_data(push, mode);
 726                 } else {
 727                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 728                         evo_data(push, mode);
 729                 }
 730
 731                 if (update) {
 732                         evo_mthd(push, 0x0080, 1);
 733                         evo_data(push, 0x00000000);
 734                 }
 735                 evo_kick(push, mast);
 736         }
 737
 738         return 0;
 739 }
 740
 741 static int
 742 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 743 {
 744         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 745         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 746         struct drm_crtc *crtc = &nv_crtc->base;
 747         struct nouveau_connector *nv_connector;
 748         int mode = DRM_MODE_SCALE_NONE;
 749         u32 oX, oY, *push;
 750
 751         /* start off at the resolution we programmed the crtc for, this
 752          * effectively handles NONE/FULL scaling
 753          */
 754         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 755         if (nv_connector && nv_connector->native_mode) {
 756                 mode = nv_connector->scaling_mode;
 757                 if (nv_connector->scaling_full) /* non-EDID LVDS/eDP mode */
 758                         mode = DRM_MODE_SCALE_FULLSCREEN;
 759         }
 760
 761         if (mode != DRM_MODE_SCALE_NONE)
 762                 omode = nv_connector->native_mode;
 763         else
 764                 omode = umode;
 765
 766         oX = omode->hdisplay;
 767         oY = omode->vdisplay;
 768         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 769                 oY *= 2;
 770
 771         /* add overscan compensation if necessary, will keep the aspect
 772          * ratio the same as the backend mode unless overridden by the
 773          * user setting both hborder and vborder properties.
 774          */
 775         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 776                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 777                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 778                 u32 bX = nv_connector->underscan_hborder;
 779                 u32 bY = nv_connector->underscan_vborder;
 780                 u32 aspect = (oY << 19) / oX;
 781
 782                 if (bX) {
 783                         oX -= (bX * 2);
 784                         if (bY) oY -= (bY * 2);
 785                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 786                 } else {
 787                         oX -= (oX >> 4) + 32;
 788                         if (bY) oY -= (bY * 2);
 789                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 790                 }
 791         }
 792
 793         /* handle CENTER/ASPECT scaling, taking into account the areas
 794          * removed already for overscan compensation
 795          */
 796         switch (mode) {
 797         case DRM_MODE_SCALE_CENTER:
 798                 oX = min((u32)umode->hdisplay, oX);
 799                 oY = min((u32)umode->vdisplay, oY);
 800                 /* fall-through */
 801         case DRM_MODE_SCALE_ASPECT:
 802                 if (oY < oX) {
 803                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 804                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 805                 } else {
 806                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 807                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 808                 }
 809                 break;
 810         default:
 811                 break;
 812         }
 813
 814         push = evo_wait(mast, 8);
 815         if (push) {
 816                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 817                         /*XXX: SCALE_CTRL_ACTIVE??? */
 818                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 819                         evo_data(push, (oY << 16) | oX);
 820                         evo_data(push, (oY << 16) | oX);
 821                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 822                         evo_data(push, 0x00000000);
 823                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 824                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 825                 } else {
 826                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 827                         evo_data(push, (oY << 16) | oX);
 828                         evo_data(push, (oY << 16) | oX);
 829                         evo_data(push, (oY << 16) | oX);
 830                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 831                         evo_data(push, 0x00000000);
 832                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 833                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 834                 }
 835
 836                 evo_kick(push, mast);
 837
 838                 if (update) {
 839                         nv50_display_flip_stop(crtc);
 840                         nv50_display_flip_next(crtc, crtc->primary->fb,
 841                                                NULL, 1);
 842                 }
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int
 849 nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec)
 850 {
 851         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 852         u32 *push;
 853
 854         push = evo_wait(mast, 8);
 855         if (!push)
 856                 return -ENOMEM;
 857
 858         evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1);
 859         evo_data(push, usec);
 860         evo_kick(push, mast);
 861         return 0;
 862 }
 863
 864 static int
 865 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 866 {
 867         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 868         u32 *push, hue, vib;
 869         int adj;
 870
 871         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 872         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 873         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 874
 875         push = evo_wait(mast, 16);
 876         if (push) {
 877                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 878                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 879                         evo_data(push, (hue << 20) | (vib << 8));
 880                 } else {
 881                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 882                         evo_data(push, (hue << 20) | (vib << 8));
 883                 }
 884
 885                 if (update) {
 886                         evo_mthd(push, 0x0080, 1);
 887                         evo_data(push, 0x00000000);
 888                 }
 889                 evo_kick(push, mast);
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int
 896 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 897                     int x, int y, bool update)
 898 {
 899         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 900         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 901         u32 *push;
 902
 903         push = evo_wait(mast, 16);
 904         if (push) {
 905                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 906                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 907                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 908                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 909                         evo_data(push, (fb->height << 16) | fb->width);
 910                         evo_data(push, nvfb->r_pitch);
 911                         evo_data(push, nvfb->r_format);
 912                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 913                         evo_data(push, (y << 16) | x);
 914                         if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
 915                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 916                                 evo_data(push, nvfb->r_handle);
 917                         }
 918                 } else {
 919                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 920                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 921                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 922                         evo_data(push, (fb->height << 16) | fb->width);
 923                         evo_data(push, nvfb->r_pitch);
 924                         evo_data(push, nvfb->r_format);
 925                         evo_data(push, nvfb->r_handle);
 926                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 927                         evo_data(push, (y << 16) | x);
 928                 }
 929
 930                 if (update) {
 931                         evo_mthd(push, 0x0080, 1);
 932                         evo_data(push, 0x00000000);
 933                 }
 934                 evo_kick(push, mast);
 935         }
 936
 937         nv_crtc->fb.handle = nvfb->r_handle;
 938         return 0;
 939 }
 940
 941 static void
 942 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 943 {
 944         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 945         u32 *push = evo_wait(mast, 16);
 946         if (push) {
 947                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 948                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 949                         evo_data(push, 0x85000000);
 950                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 951                 } else
 952                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 953                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 954                         evo_data(push, 0x85000000);
 955                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 956                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 957                         evo_data(push, mast->base.vram.handle);
 958                 } else {
 959                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 960                         evo_data(push, 0x85000000);
 961                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 962                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 963                         evo_data(push, mast->base.vram.handle);
 964                 }
 965                 evo_kick(push, mast);
 966         }
 967         nv_crtc->cursor.visible = true;
 968 }
 969
 970 static void
 971 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 972 {
 973         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 974         u32 *push = evo_wait(mast, 16);
 975         if (push) {
 976                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
 977                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 978                         evo_data(push, 0x05000000);
 979                 } else
 980                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
 981                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 982                         evo_data(push, 0x05000000);
 983                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 984                         evo_data(push, 0x00000000);
 985                 } else {
 986                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 987                         evo_data(push, 0x05000000);
 988                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 989                         evo_data(push, 0x00000000);
 990                 }
 991                 evo_kick(push, mast);
 992         }
 993         nv_crtc->cursor.visible = false;
 994 }
 995
 996 static void
 997 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 998 {
 999         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
1000
1001         if (show && nv_crtc->cursor.nvbo && nv_crtc->base.enabled)
1002                 nv50_crtc_cursor_show(nv_crtc);
1003         else
1004                 nv50_crtc_cursor_hide(nv_crtc);
1005
1006         if (update) {
1007                 u32 *push = evo_wait(mast, 2);
1008                 if (push) {
1009                         evo_mthd(push, 0x0080, 1);
1010                         evo_data(push, 0x00000000);
1011                         evo_kick(push, mast);
1012                 }
1013         }
1014 }
1015
1016 static void
1017 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
1018 {
1019 }
1020
1021 static void
1022 nv50_crtc_prepare(struct drm_crtc *crtc)
1023 {
1024         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1025         struct nv50_mast *mast = nv50_mast(crtc->dev);
1026         u32 *push;
1027
1028         nv50_display_flip_stop(crtc);
1029
1030         push = evo_wait(mast, 6);
1031         if (push) {
1032                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1033                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1034                         evo_data(push, 0x00000000);
1035                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1036                         evo_data(push, 0x40000000);
1037                 } else
1038                 if (nv50_vers(mast) <  GF110_DISP_CORE_CHANNEL_DMA) {
1039                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1040                         evo_data(push, 0x00000000);
1041                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
1042                         evo_data(push, 0x40000000);
1043                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1044                         evo_data(push, 0x00000000);
1045                 } else {
1046                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1047                         evo_data(push, 0x00000000);
1048                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
1049                         evo_data(push, 0x03000000);
1050                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1051                         evo_data(push, 0x00000000);
1052                 }
1053
1054                 evo_kick(push, mast);
1055         }
1056
1057         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
1058 }
1059
1060 static void
1061 nv50_crtc_commit(struct drm_crtc *crtc)
1062 {
1063         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1064         struct nv50_mast *mast = nv50_mast(crtc->dev);
1065         u32 *push;
1066
1067         push = evo_wait(mast, 32);
1068         if (push) {
1069                 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1070                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1071                         evo_data(push, nv_crtc->fb.handle);
1072                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1073                         evo_data(push, 0xc0000000);
1074                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1075                 } else
1076                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1077                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1078                         evo_data(push, nv_crtc->fb.handle);
1079                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1080                         evo_data(push, 0xc0000000);
1081                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1082                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1083                         evo_data(push, mast->base.vram.handle);
1084                 } else {
1085                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1086                         evo_data(push, nv_crtc->fb.handle);
1087                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1088                         evo_data(push, 0x83000000);
1089                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1090                         evo_data(push, 0x00000000);
1091                         evo_data(push, 0x00000000);
1092                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1093                         evo_data(push, mast->base.vram.handle);
1094                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1095                         evo_data(push, 0xffffff00);
1096                 }
1097
1098                 evo_kick(push, mast);
1099         }
1100
1101         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1102         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1103 }
1104
1105 static bool
1106 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1107                      struct drm_display_mode *adjusted_mode)
1108 {
1109         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1110         return true;
1111 }
1112
1113 static int
1114 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1115 {
1116         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1117         struct nv50_head *head = nv50_head(crtc);
1118         int ret;
1119
1120         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, true);
1121         if (ret == 0) {
1122                 if (head->image)
1123                         nouveau_bo_unpin(head->image);
1124                 nouveau_bo_ref(nvfb->nvbo, &head->image);
1125         }
1126
1127         return ret;
1128 }
1129
1130 static int
1131 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1132                    struct drm_display_mode *mode, int x, int y,
1133                    struct drm_framebuffer *old_fb)
1134 {
1135         struct nv50_mast *mast = nv50_mast(crtc->dev);
1136         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1137         struct nouveau_connector *nv_connector;
1138         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1139         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1140         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1141         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1142         u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
1143         u32 *push;
1144         int ret;
1145
1146         hactive = mode->htotal;
1147         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1148         hbackp  = mode->htotal - mode->hsync_end;
1149         hblanke = hsynce + hbackp;
1150         hfrontp = mode->hsync_start - mode->hdisplay;
1151         hblanks = mode->htotal - hfrontp - 1;
1152
1153         vactive = mode->vtotal * vscan / ilace;
1154         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1155         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1156         vblanke = vsynce + vbackp;
1157         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1158         vblanks = vactive - vfrontp - 1;
1159         /* XXX: Safe underestimate, even "0" works */
1160         vblankus = (vactive - mode->vdisplay - 2) * hactive;
1161         vblankus *= 1000;
1162         vblankus /= mode->clock;
1163
1164         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1165                 vblan2e = vactive + vsynce + vbackp;
1166                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1167                 vactive = (vactive * 2) + 1;
1168         }
1169
1170         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1171         if (ret)
1172                 return ret;
1173
1174         push = evo_wait(mast, 64);
1175         if (push) {
1176                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1177                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1178                         evo_data(push, 0x00800000 | mode->clock);
1179                         evo_data(push, (ilace == 2) ? 2 : 0);
1180                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1181                         evo_data(push, 0x00000000);
1182                         evo_data(push, (vactive << 16) | hactive);
1183                         evo_data(push, ( vsynce << 16) | hsynce);
1184                         evo_data(push, (vblanke << 16) | hblanke);
1185                         evo_data(push, (vblanks << 16) | hblanks);
1186                         evo_data(push, (vblan2e << 16) | vblan2s);
1187                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1188                         evo_data(push, 0x00000000);
1189                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1190                         evo_data(push, 0x00000311);
1191                         evo_data(push, 0x00000100);
1192                 } else {
1193                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1194                         evo_data(push, 0x00000000);
1195                         evo_data(push, (vactive << 16) | hactive);
1196                         evo_data(push, ( vsynce << 16) | hsynce);
1197                         evo_data(push, (vblanke << 16) | hblanke);
1198                         evo_data(push, (vblanks << 16) | hblanks);
1199                         evo_data(push, (vblan2e << 16) | vblan2s);
1200                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1201                         evo_data(push, 0x00000000); /* ??? */
1202                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1203                         evo_data(push, mode->clock * 1000);
1204                         evo_data(push, 0x00200000); /* ??? */
1205                         evo_data(push, mode->clock * 1000);
1206                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1207                         evo_data(push, 0x00000311);
1208                         evo_data(push, 0x00000100);
1209                 }
1210
1211                 evo_kick(push, mast);
1212         }
1213
1214         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1215         nv50_crtc_set_dither(nv_crtc, false);
1216         nv50_crtc_set_scale(nv_crtc, false);
1217
1218         /* G94 only accepts this after setting scale */
1219         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA)
1220                 nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus);
1221
1222         nv50_crtc_set_color_vibrance(nv_crtc, false);
1223         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1224         return 0;
1225 }
1226
1227 static int
1228 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1229                         struct drm_framebuffer *old_fb)
1230 {
1231         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1232         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1233         int ret;
1234
1235         if (!crtc->primary->fb) {
1236                 NV_DEBUG(drm, "No FB bound\n");
1237                 return 0;
1238         }
1239
1240         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1241         if (ret)
1242                 return ret;
1243
1244         nv50_display_flip_stop(crtc);
1245         nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1246         nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1247         return 0;
1248 }
1249
1250 static int
1251 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1252                                struct drm_framebuffer *fb, int x, int y,
1253                                enum mode_set_atomic state)
1254 {
1255         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1256         nv50_display_flip_stop(crtc);
1257         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1258         return 0;
1259 }
1260
1261 static void
1262 nv50_crtc_lut_load(struct drm_crtc *crtc)
1263 {
1264         struct nv50_disp *disp = nv50_disp(crtc->dev);
1265         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1266         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1267         int i;
1268
1269         for (i = 0; i < 256; i++) {
1270                 u16 r = nv_crtc->lut.r[i] >> 2;
1271                 u16 g = nv_crtc->lut.g[i] >> 2;
1272                 u16 b = nv_crtc->lut.b[i] >> 2;
1273
1274                 if (disp->disp->oclass < GF110_DISP) {
1275                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1276                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1277                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1278                 } else {
1279                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1280                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1281                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1282                 }
1283         }
1284 }
1285
1286 static void
1287 nv50_crtc_disable(struct drm_crtc *crtc)
1288 {
1289         struct nv50_head *head = nv50_head(crtc);
1290         evo_sync(crtc->dev);
1291         if (head->image)
1292                 nouveau_bo_unpin(head->image);
1293         nouveau_bo_ref(NULL, &head->image);
1294 }
1295
1296 static int
1297 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1298                      uint32_t handle, uint32_t width, uint32_t height)
1299 {
1300         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1301         struct drm_device *dev = crtc->dev;
1302         struct drm_gem_object *gem = NULL;
1303         struct nouveau_bo *nvbo = NULL;
1304         int ret = 0;
1305
1306         if (handle) {
1307                 if (width != 64 || height != 64)
1308                         return -EINVAL;
1309
1310                 gem = drm_gem_object_lookup(dev, file_priv, handle);
1311                 if (unlikely(!gem))
1312                         return -ENOENT;
1313                 nvbo = nouveau_gem_object(gem);
1314
1315                 ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM, true);
1316         }
1317
1318         if (ret == 0) {
1319                 if (nv_crtc->cursor.nvbo)
1320                         nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1321                 nouveau_bo_ref(nvbo, &nv_crtc->cursor.nvbo);
1322         }
1323         drm_gem_object_unreference_unlocked(gem);
1324
1325         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1326         return ret;
1327 }
1328
1329 static int
1330 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1331 {
1332         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1333         struct nv50_curs *curs = nv50_curs(crtc);
1334         struct nv50_chan *chan = nv50_chan(curs);
1335         nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1336         nvif_wr32(&chan->user, 0x0080, 0x00000000);
1337
1338         nv_crtc->cursor_saved_x = x;
1339         nv_crtc->cursor_saved_y = y;
1340         return 0;
1341 }
1342
1343 static void
1344 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1345                     uint32_t start, uint32_t size)
1346 {
1347         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1348         u32 end = min_t(u32, start + size, 256);
1349         u32 i;
1350
1351         for (i = start; i < end; i++) {
1352                 nv_crtc->lut.r[i] = r[i];
1353                 nv_crtc->lut.g[i] = g[i];
1354                 nv_crtc->lut.b[i] = b[i];
1355         }
1356
1357         nv50_crtc_lut_load(crtc);
1358 }
1359
1360 static void
1361 nv50_crtc_cursor_restore(struct nouveau_crtc *nv_crtc, int x, int y)
1362 {
1363         nv50_crtc_cursor_move(&nv_crtc->base, x, y);
1364
1365         nv50_crtc_cursor_show_hide(nv_crtc, true, true);
1366 }
1367
1368 static void
1369 nv50_crtc_destroy(struct drm_crtc *crtc)
1370 {
1371         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1372         struct nv50_disp *disp = nv50_disp(crtc->dev);
1373         struct nv50_head *head = nv50_head(crtc);
1374         struct nv50_fbdma *fbdma;
1375
1376         list_for_each_entry(fbdma, &disp->fbdma, head) {
1377                 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1378         }
1379
1380         nv50_dmac_destroy(&head->ovly.base, disp->disp);
1381         nv50_pioc_destroy(&head->oimm.base);
1382         nv50_dmac_destroy(&head->sync.base, disp->disp);
1383         nv50_pioc_destroy(&head->curs.base);
1384
1385         /*XXX: this shouldn't be necessary, but the core doesn't call
1386          *     disconnect() during the cleanup paths
1387          */
1388         if (head->image)
1389                 nouveau_bo_unpin(head->image);
1390         nouveau_bo_ref(NULL, &head->image);
1391
1392         /*XXX: ditto */
1393         if (nv_crtc->cursor.nvbo)
1394                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1395         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1396
1397         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1398         if (nv_crtc->lut.nvbo)
1399                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1400         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1401
1402         drm_crtc_cleanup(crtc);
1403         kfree(crtc);
1404 }
1405
1406 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1407         .dpms = nv50_crtc_dpms,
1408         .prepare = nv50_crtc_prepare,
1409         .commit = nv50_crtc_commit,
1410         .mode_fixup = nv50_crtc_mode_fixup,
1411         .mode_set = nv50_crtc_mode_set,
1412         .mode_set_base = nv50_crtc_mode_set_base,
1413         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1414         .load_lut = nv50_crtc_lut_load,
1415         .disable = nv50_crtc_disable,
1416 };
1417
1418 static const struct drm_crtc_funcs nv50_crtc_func = {
1419         .cursor_set = nv50_crtc_cursor_set,
1420         .cursor_move = nv50_crtc_cursor_move,
1421         .gamma_set = nv50_crtc_gamma_set,
1422         .set_config = nouveau_crtc_set_config,
1423         .destroy = nv50_crtc_destroy,
1424         .page_flip = nouveau_crtc_page_flip,
1425 };
1426
1427 static int
1428 nv50_crtc_create(struct drm_device *dev, int index)
1429 {
1430         struct nouveau_drm *drm = nouveau_drm(dev);
1431         struct nvif_device *device = &drm->device;
1432         struct nv50_disp *disp = nv50_disp(dev);
1433         struct nv50_head *head;
1434         struct drm_crtc *crtc;
1435         int ret, i;
1436
1437         head = kzalloc(sizeof(*head), GFP_KERNEL);
1438         if (!head)
1439                 return -ENOMEM;
1440
1441         head->base.index = index;
1442         head->base.set_dither = nv50_crtc_set_dither;
1443         head->base.set_scale = nv50_crtc_set_scale;
1444         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1445         head->base.color_vibrance = 50;
1446         head->base.vibrant_hue = 0;
1447         head->base.cursor.set_pos = nv50_crtc_cursor_restore;
1448         for (i = 0; i < 256; i++) {
1449                 head->base.lut.r[i] = i << 8;
1450                 head->base.lut.g[i] = i << 8;
1451                 head->base.lut.b[i] = i << 8;
1452         }
1453
1454         crtc = &head->base.base;
1455         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1456         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1457         drm_mode_crtc_set_gamma_size(crtc, 256);
1458
1459         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1460                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
1461         if (!ret) {
1462                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
1463                 if (!ret) {
1464                         ret = nouveau_bo_map(head->base.lut.nvbo);
1465                         if (ret)
1466                                 nouveau_bo_unpin(head->base.lut.nvbo);
1467                 }
1468                 if (ret)
1469                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1470         }
1471
1472         if (ret)
1473                 goto out;
1474
1475         /* allocate cursor resources */
1476         ret = nv50_curs_create(device, disp->disp, index, &head->curs);
1477         if (ret)
1478                 goto out;
1479
1480         /* allocate page flip / sync resources */
1481         ret = nv50_base_create(device, disp->disp, index, disp->sync->bo.offset,
1482                                &head->sync);
1483         if (ret)
1484                 goto out;
1485
1486         head->sync.addr = EVO_FLIP_SEM0(index);
1487         head->sync.data = 0x00000000;
1488
1489         /* allocate overlay resources */
1490         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
1491         if (ret)
1492                 goto out;
1493
1494         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
1495                                &head->ovly);
1496         if (ret)
1497                 goto out;
1498
1499 out:
1500         if (ret)
1501                 nv50_crtc_destroy(crtc);
1502         return ret;
1503 }
1504
1505 /******************************************************************************
1506  * Encoder helpers
1507  *****************************************************************************/
1508 static bool
1509 nv50_encoder_mode_fixup(struct drm_encoder *encoder,
1510                         const struct drm_display_mode *mode,
1511                         struct drm_display_mode *adjusted_mode)
1512 {
1513         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1514         struct nouveau_connector *nv_connector;
1515
1516         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1517         if (nv_connector && nv_connector->native_mode) {
1518                 nv_connector->scaling_full = false;
1519                 if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) {
1520                         switch (nv_connector->type) {
1521                         case DCB_CONNECTOR_LVDS:
1522                         case DCB_CONNECTOR_LVDS_SPWG:
1523                         case DCB_CONNECTOR_eDP:
1524                                 /* force use of scaler for non-edid modes */
1525                                 if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
1526                                         return true;
1527                                 nv_connector->scaling_full = true;
1528                                 break;
1529                         default:
1530                                 return true;
1531                         }
1532                 }
1533
1534                 drm_mode_copy(adjusted_mode, nv_connector->native_mode);
1535         }
1536
1537         return true;
1538 }
1539
1540 /******************************************************************************
1541  * DAC
1542  *****************************************************************************/
1543 static void
1544 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1545 {
1546         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1547         struct nv50_disp *disp = nv50_disp(encoder->dev);
1548         struct {
1549                 struct nv50_disp_mthd_v1 base;
1550                 struct nv50_disp_dac_pwr_v0 pwr;
1551         } args = {
1552                 .base.version = 1,
1553                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1554                 .base.hasht  = nv_encoder->dcb->hasht,
1555                 .base.hashm  = nv_encoder->dcb->hashm,
1556                 .pwr.state = 1,
1557                 .pwr.data  = 1,
1558                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1559                               mode != DRM_MODE_DPMS_OFF),
1560                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1561                               mode != DRM_MODE_DPMS_OFF),
1562         };
1563
1564         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1565 }
1566
1567 static void
1568 nv50_dac_commit(struct drm_encoder *encoder)
1569 {
1570 }
1571
1572 static void
1573 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1574                   struct drm_display_mode *adjusted_mode)
1575 {
1576         struct nv50_mast *mast = nv50_mast(encoder->dev);
1577         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1578         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1579         u32 *push;
1580
1581         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1582
1583         push = evo_wait(mast, 8);
1584         if (push) {
1585                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1586                         u32 syncs = 0x00000000;
1587
1588                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1589                                 syncs |= 0x00000001;
1590                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1591                                 syncs |= 0x00000002;
1592
1593                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1594                         evo_data(push, 1 << nv_crtc->index);
1595                         evo_data(push, syncs);
1596                 } else {
1597                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1598                         u32 syncs = 0x00000001;
1599
1600                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1601                                 syncs |= 0x00000008;
1602                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1603                                 syncs |= 0x00000010;
1604
1605                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1606                                 magic |= 0x00000001;
1607
1608                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1609                         evo_data(push, syncs);
1610                         evo_data(push, magic);
1611                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1612                         evo_data(push, 1 << nv_crtc->index);
1613                 }
1614
1615                 evo_kick(push, mast);
1616         }
1617
1618         nv_encoder->crtc = encoder->crtc;
1619 }
1620
1621 static void
1622 nv50_dac_disconnect(struct drm_encoder *encoder)
1623 {
1624         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1625         struct nv50_mast *mast = nv50_mast(encoder->dev);
1626         const int or = nv_encoder->or;
1627         u32 *push;
1628
1629         if (nv_encoder->crtc) {
1630                 nv50_crtc_prepare(nv_encoder->crtc);
1631
1632                 push = evo_wait(mast, 4);
1633                 if (push) {
1634                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1635                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1636                                 evo_data(push, 0x00000000);
1637                         } else {
1638                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1639                                 evo_data(push, 0x00000000);
1640                         }
1641                         evo_kick(push, mast);
1642                 }
1643         }
1644
1645         nv_encoder->crtc = NULL;
1646 }
1647
1648 static enum drm_connector_status
1649 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1650 {
1651         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1652         struct nv50_disp *disp = nv50_disp(encoder->dev);
1653         struct {
1654                 struct nv50_disp_mthd_v1 base;
1655                 struct nv50_disp_dac_load_v0 load;
1656         } args = {
1657                 .base.version = 1,
1658                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1659                 .base.hasht  = nv_encoder->dcb->hasht,
1660                 .base.hashm  = nv_encoder->dcb->hashm,
1661         };
1662         int ret;
1663
1664         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1665         if (args.load.data == 0)
1666                 args.load.data = 340;
1667
1668         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1669         if (ret || !args.load.load)
1670                 return connector_status_disconnected;
1671
1672         return connector_status_connected;
1673 }
1674
1675 static void
1676 nv50_dac_destroy(struct drm_encoder *encoder)
1677 {
1678         drm_encoder_cleanup(encoder);
1679         kfree(encoder);
1680 }
1681
1682 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1683         .dpms = nv50_dac_dpms,
1684         .mode_fixup = nv50_encoder_mode_fixup,
1685         .prepare = nv50_dac_disconnect,
1686         .commit = nv50_dac_commit,
1687         .mode_set = nv50_dac_mode_set,
1688         .disable = nv50_dac_disconnect,
1689         .get_crtc = nv50_display_crtc_get,
1690         .detect = nv50_dac_detect
1691 };
1692
1693 static const struct drm_encoder_funcs nv50_dac_func = {
1694         .destroy = nv50_dac_destroy,
1695 };
1696
1697 static int
1698 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1699 {
1700         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1701         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
1702         struct nvkm_i2c_bus *bus;
1703         struct nouveau_encoder *nv_encoder;
1704         struct drm_encoder *encoder;
1705         int type = DRM_MODE_ENCODER_DAC;
1706
1707         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1708         if (!nv_encoder)
1709                 return -ENOMEM;
1710         nv_encoder->dcb = dcbe;
1711         nv_encoder->or = ffs(dcbe->or) - 1;
1712
1713         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
1714         if (bus)
1715                 nv_encoder->i2c = &bus->i2c;
1716
1717         encoder = to_drm_encoder(nv_encoder);
1718         encoder->possible_crtcs = dcbe->heads;
1719         encoder->possible_clones = 0;
1720         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type, NULL);
1721         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1722
1723         drm_mode_connector_attach_encoder(connector, encoder);
1724         return 0;
1725 }
1726
1727 /******************************************************************************
1728  * Audio
1729  *****************************************************************************/
1730 static void
1731 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1732 {
1733         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1734         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1735         struct nouveau_connector *nv_connector;
1736         struct nv50_disp *disp = nv50_disp(encoder->dev);
1737         struct __packed {
1738                 struct {
1739                         struct nv50_disp_mthd_v1 mthd;
1740                         struct nv50_disp_sor_hda_eld_v0 eld;
1741                 } base;
1742                 u8 data[sizeof(nv_connector->base.eld)];
1743         } args = {
1744                 .base.mthd.version = 1,
1745                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1746                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
1747                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1748                                      (0x0100 << nv_crtc->index),
1749         };
1750
1751         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1752         if (!drm_detect_monitor_audio(nv_connector->edid))
1753                 return;
1754
1755         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1756         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1757
1758         nvif_mthd(disp->disp, 0, &args,
1759                   sizeof(args.base) + drm_eld_size(args.data));
1760 }
1761
1762 static void
1763 nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1764 {
1765         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1766         struct nv50_disp *disp = nv50_disp(encoder->dev);
1767         struct {
1768                 struct nv50_disp_mthd_v1 base;
1769                 struct nv50_disp_sor_hda_eld_v0 eld;
1770         } args = {
1771                 .base.version = 1,
1772                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1773                 .base.hasht   = nv_encoder->dcb->hasht,
1774                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
1775                                 (0x0100 << nv_crtc->index),
1776         };
1777
1778         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1779 }
1780
1781 /******************************************************************************
1782  * HDMI
1783  *****************************************************************************/
1784 static void
1785 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1786 {
1787         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1788         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1789         struct nv50_disp *disp = nv50_disp(encoder->dev);
1790         struct {
1791                 struct nv50_disp_mthd_v1 base;
1792                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1793         } args = {
1794                 .base.version = 1,
1795                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1796                 .base.hasht  = nv_encoder->dcb->hasht,
1797                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1798                                (0x0100 << nv_crtc->index),
1799                 .pwr.state = 1,
1800                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1801         };
1802         struct nouveau_connector *nv_connector;
1803         u32 max_ac_packet;
1804
1805         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1806         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1807                 return;
1808
1809         max_ac_packet  = mode->htotal - mode->hdisplay;
1810         max_ac_packet -= args.pwr.rekey;
1811         max_ac_packet -= 18; /* constant from tegra */
1812         args.pwr.max_ac_packet = max_ac_packet / 32;
1813
1814         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1815         nv50_audio_mode_set(encoder, mode);
1816 }
1817
1818 static void
1819 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1820 {
1821         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1822         struct nv50_disp *disp = nv50_disp(encoder->dev);
1823         struct {
1824                 struct nv50_disp_mthd_v1 base;
1825                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1826         } args = {
1827                 .base.version = 1,
1828                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1829                 .base.hasht  = nv_encoder->dcb->hasht,
1830                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
1831                                (0x0100 << nv_crtc->index),
1832         };
1833
1834         nvif_mthd(disp->disp, 0, &args, sizeof(args));
1835 }
1836
1837 /******************************************************************************
1838  * SOR
1839  *****************************************************************************/
1840 static void
1841 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1842 {
1843         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1844         struct nv50_disp *disp = nv50_disp(encoder->dev);
1845         struct {
1846                 struct nv50_disp_mthd_v1 base;
1847                 struct nv50_disp_sor_pwr_v0 pwr;
1848         } args = {
1849                 .base.version = 1,
1850                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1851                 .base.hasht  = nv_encoder->dcb->hasht,
1852                 .base.hashm  = nv_encoder->dcb->hashm,
1853                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1854         };
1855         struct {
1856                 struct nv50_disp_mthd_v1 base;
1857                 struct nv50_disp_sor_dp_pwr_v0 pwr;
1858         } link = {
1859                 .base.version = 1,
1860                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1861                 .base.hasht  = nv_encoder->dcb->hasht,
1862                 .base.hashm  = nv_encoder->dcb->hashm,
1863                 .pwr.state = mode == DRM_MODE_DPMS_ON,
1864         };
1865         struct drm_device *dev = encoder->dev;
1866         struct drm_encoder *partner;
1867
1868         nv_encoder->last_dpms = mode;
1869
1870         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1871                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1872
1873                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1874                         continue;
1875
1876                 if (nv_partner != nv_encoder &&
1877                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1878                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1879                                 return;
1880                         break;
1881                 }
1882         }
1883
1884         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1885                 args.pwr.state = 1;
1886                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1887                 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1888         } else {
1889                 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1890         }
1891 }
1892
1893 static void
1894 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1895 {
1896         struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1897         u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1898         if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1899                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1900                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1901                         evo_data(push, (nv_encoder->ctrl = temp));
1902                 } else {
1903                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1904                         evo_data(push, (nv_encoder->ctrl = temp));
1905                 }
1906                 evo_kick(push, mast);
1907         }
1908 }
1909
1910 static void
1911 nv50_sor_disconnect(struct drm_encoder *encoder)
1912 {
1913         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1914         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1915
1916         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1917         nv_encoder->crtc = NULL;
1918
1919         if (nv_crtc) {
1920                 nv50_crtc_prepare(&nv_crtc->base);
1921                 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1922                 nv50_audio_disconnect(encoder, nv_crtc);
1923                 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1924         }
1925 }
1926
1927 static void
1928 nv50_sor_commit(struct drm_encoder *encoder)
1929 {
1930 }
1931
1932 static void
1933 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1934                   struct drm_display_mode *mode)
1935 {
1936         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1937         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1938         struct {
1939                 struct nv50_disp_mthd_v1 base;
1940                 struct nv50_disp_sor_lvds_script_v0 lvds;
1941         } lvds = {
1942                 .base.version = 1,
1943                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1944                 .base.hasht   = nv_encoder->dcb->hasht,
1945                 .base.hashm   = nv_encoder->dcb->hashm,
1946         };
1947         struct nv50_disp *disp = nv50_disp(encoder->dev);
1948         struct nv50_mast *mast = nv50_mast(encoder->dev);
1949         struct drm_device *dev = encoder->dev;
1950         struct nouveau_drm *drm = nouveau_drm(dev);
1951         struct nouveau_connector *nv_connector;
1952         struct nvbios *bios = &drm->vbios;
1953         u32 mask, ctrl;
1954         u8 owner = 1 << nv_crtc->index;
1955         u8 proto = 0xf;
1956         u8 depth = 0x0;
1957
1958         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1959         nv_encoder->crtc = encoder->crtc;
1960
1961         switch (nv_encoder->dcb->type) {
1962         case DCB_OUTPUT_TMDS:
1963                 if (nv_encoder->dcb->sorconf.link & 1) {
1964                         proto = 0x1;
1965                         /* Only enable dual-link if:
1966                          *  - Need to (i.e. rate > 165MHz)
1967                          *  - DCB says we can
1968                          *  - Not an HDMI monitor, since there's no dual-link
1969                          *    on HDMI.
1970                          */
1971                         if (mode->clock >= 165000 &&
1972                             nv_encoder->dcb->duallink_possible &&
1973                             !drm_detect_hdmi_monitor(nv_connector->edid))
1974                                 proto |= 0x4;
1975                 } else {
1976                         proto = 0x2;
1977                 }
1978
1979                 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1980                 break;
1981         case DCB_OUTPUT_LVDS:
1982                 proto = 0x0;
1983
1984                 if (bios->fp_no_ddc) {
1985                         if (bios->fp.dual_link)
1986                                 lvds.lvds.script |= 0x0100;
1987                         if (bios->fp.if_is_24bit)
1988                                 lvds.lvds.script |= 0x0200;
1989                 } else {
1990                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1991                                 if (((u8 *)nv_connector->edid)[121] == 2)
1992                                         lvds.lvds.script |= 0x0100;
1993                         } else
1994                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1995                                 lvds.lvds.script |= 0x0100;
1996                         }
1997
1998                         if (lvds.lvds.script & 0x0100) {
1999                                 if (bios->fp.strapless_is_24bit & 2)
2000                                         lvds.lvds.script |= 0x0200;
2001                         } else {
2002                                 if (bios->fp.strapless_is_24bit & 1)
2003                                         lvds.lvds.script |= 0x0200;
2004                         }
2005
2006                         if (nv_connector->base.display_info.bpc == 8)
2007                                 lvds.lvds.script |= 0x0200;
2008                 }
2009
2010                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
2011                 break;
2012         case DCB_OUTPUT_DP:
2013                 if (nv_connector->base.display_info.bpc == 6) {
2014                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
2015                         depth = 0x2;
2016                 } else
2017                 if (nv_connector->base.display_info.bpc == 8) {
2018                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
2019                         depth = 0x5;
2020                 } else {
2021                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
2022                         depth = 0x6;
2023                 }
2024
2025                 if (nv_encoder->dcb->sorconf.link & 1)
2026                         proto = 0x8;
2027                 else
2028                         proto = 0x9;
2029                 nv50_audio_mode_set(encoder, mode);
2030                 break;
2031         default:
2032                 BUG_ON(1);
2033                 break;
2034         }
2035
2036         nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
2037
2038         if (nv50_vers(mast) >= GF110_DISP) {
2039                 u32 *push = evo_wait(mast, 3);
2040                 if (push) {
2041                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2042                         u32 syncs = 0x00000001;
2043
2044                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2045                                 syncs |= 0x00000008;
2046                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2047                                 syncs |= 0x00000010;
2048
2049                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2050                                 magic |= 0x00000001;
2051
2052                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2053                         evo_data(push, syncs | (depth << 6));
2054                         evo_data(push, magic);
2055                         evo_kick(push, mast);
2056                 }
2057
2058                 ctrl = proto << 8;
2059                 mask = 0x00000f00;
2060         } else {
2061                 ctrl = (depth << 16) | (proto << 8);
2062                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2063                         ctrl |= 0x00001000;
2064                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2065                         ctrl |= 0x00002000;
2066                 mask = 0x000f3f00;
2067         }
2068
2069         nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2070 }
2071
2072 static void
2073 nv50_sor_destroy(struct drm_encoder *encoder)
2074 {
2075         drm_encoder_cleanup(encoder);
2076         kfree(encoder);
2077 }
2078
2079 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2080         .dpms = nv50_sor_dpms,
2081         .mode_fixup = nv50_encoder_mode_fixup,
2082         .prepare = nv50_sor_disconnect,
2083         .commit = nv50_sor_commit,
2084         .mode_set = nv50_sor_mode_set,
2085         .disable = nv50_sor_disconnect,
2086         .get_crtc = nv50_display_crtc_get,
2087 };
2088
2089 static const struct drm_encoder_funcs nv50_sor_func = {
2090         .destroy = nv50_sor_destroy,
2091 };
2092
2093 static int
2094 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2095 {
2096         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2097         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2098         struct nouveau_encoder *nv_encoder;
2099         struct drm_encoder *encoder;
2100         int type;
2101
2102         switch (dcbe->type) {
2103         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2104         case DCB_OUTPUT_TMDS:
2105         case DCB_OUTPUT_DP:
2106         default:
2107                 type = DRM_MODE_ENCODER_TMDS;
2108                 break;
2109         }
2110
2111         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2112         if (!nv_encoder)
2113                 return -ENOMEM;
2114         nv_encoder->dcb = dcbe;
2115         nv_encoder->or = ffs(dcbe->or) - 1;
2116         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2117
2118         if (dcbe->type == DCB_OUTPUT_DP) {
2119                 struct nvkm_i2c_aux *aux =
2120                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
2121                 if (aux) {
2122                         nv_encoder->i2c = &aux->i2c;
2123                         nv_encoder->aux = aux;
2124                 }
2125         } else {
2126                 struct nvkm_i2c_bus *bus =
2127                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2128                 if (bus)
2129                         nv_encoder->i2c = &bus->i2c;
2130         }
2131
2132         encoder = to_drm_encoder(nv_encoder);
2133         encoder->possible_crtcs = dcbe->heads;
2134         encoder->possible_clones = 0;
2135         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type, NULL);
2136         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2137
2138         drm_mode_connector_attach_encoder(connector, encoder);
2139         return 0;
2140 }
2141
2142 /******************************************************************************
2143  * PIOR
2144  *****************************************************************************/
2145
2146 static void
2147 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2148 {
2149         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2150         struct nv50_disp *disp = nv50_disp(encoder->dev);
2151         struct {
2152                 struct nv50_disp_mthd_v1 base;
2153                 struct nv50_disp_pior_pwr_v0 pwr;
2154         } args = {
2155                 .base.version = 1,
2156                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2157                 .base.hasht  = nv_encoder->dcb->hasht,
2158                 .base.hashm  = nv_encoder->dcb->hashm,
2159                 .pwr.state = mode == DRM_MODE_DPMS_ON,
2160                 .pwr.type = nv_encoder->dcb->type,
2161         };
2162
2163         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2164 }
2165
2166 static bool
2167 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2168                      const struct drm_display_mode *mode,
2169                      struct drm_display_mode *adjusted_mode)
2170 {
2171         if (!nv50_encoder_mode_fixup(encoder, mode, adjusted_mode))
2172                 return false;
2173         adjusted_mode->clock *= 2;
2174         return true;
2175 }
2176
2177 static void
2178 nv50_pior_commit(struct drm_encoder *encoder)
2179 {
2180 }
2181
2182 static void
2183 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2184                    struct drm_display_mode *adjusted_mode)
2185 {
2186         struct nv50_mast *mast = nv50_mast(encoder->dev);
2187         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2188         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2189         struct nouveau_connector *nv_connector;
2190         u8 owner = 1 << nv_crtc->index;
2191         u8 proto, depth;
2192         u32 *push;
2193
2194         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2195         switch (nv_connector->base.display_info.bpc) {
2196         case 10: depth = 0x6; break;
2197         case  8: depth = 0x5; break;
2198         case  6: depth = 0x2; break;
2199         default: depth = 0x0; break;
2200         }
2201
2202         switch (nv_encoder->dcb->type) {
2203         case DCB_OUTPUT_TMDS:
2204         case DCB_OUTPUT_DP:
2205                 proto = 0x0;
2206                 break;
2207         default:
2208                 BUG_ON(1);
2209                 break;
2210         }
2211
2212         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2213
2214         push = evo_wait(mast, 8);
2215         if (push) {
2216                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2217                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2218                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2219                                 ctrl |= 0x00001000;
2220                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2221                                 ctrl |= 0x00002000;
2222                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2223                         evo_data(push, ctrl);
2224                 }
2225
2226                 evo_kick(push, mast);
2227         }
2228
2229         nv_encoder->crtc = encoder->crtc;
2230 }
2231
2232 static void
2233 nv50_pior_disconnect(struct drm_encoder *encoder)
2234 {
2235         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2236         struct nv50_mast *mast = nv50_mast(encoder->dev);
2237         const int or = nv_encoder->or;
2238         u32 *push;
2239
2240         if (nv_encoder->crtc) {
2241                 nv50_crtc_prepare(nv_encoder->crtc);
2242
2243                 push = evo_wait(mast, 4);
2244                 if (push) {
2245                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2246                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2247                                 evo_data(push, 0x00000000);
2248                         }
2249                         evo_kick(push, mast);
2250                 }
2251         }
2252
2253         nv_encoder->crtc = NULL;
2254 }
2255
2256 static void
2257 nv50_pior_destroy(struct drm_encoder *encoder)
2258 {
2259         drm_encoder_cleanup(encoder);
2260         kfree(encoder);
2261 }
2262
2263 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2264         .dpms = nv50_pior_dpms,
2265         .mode_fixup = nv50_pior_mode_fixup,
2266         .prepare = nv50_pior_disconnect,
2267         .commit = nv50_pior_commit,
2268         .mode_set = nv50_pior_mode_set,
2269         .disable = nv50_pior_disconnect,
2270         .get_crtc = nv50_display_crtc_get,
2271 };
2272
2273 static const struct drm_encoder_funcs nv50_pior_func = {
2274         .destroy = nv50_pior_destroy,
2275 };
2276
2277 static int
2278 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2279 {
2280         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2281         struct nvkm_i2c *i2c = nvxx_i2c(&drm->device);
2282         struct nvkm_i2c_bus *bus = NULL;
2283         struct nvkm_i2c_aux *aux = NULL;
2284         struct i2c_adapter *ddc;
2285         struct nouveau_encoder *nv_encoder;
2286         struct drm_encoder *encoder;
2287         int type;
2288
2289         switch (dcbe->type) {
2290         case DCB_OUTPUT_TMDS:
2291                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
2292                 ddc  = bus ? &bus->i2c : NULL;
2293                 type = DRM_MODE_ENCODER_TMDS;
2294                 break;
2295         case DCB_OUTPUT_DP:
2296                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
2297                 ddc  = aux ? &aux->i2c : NULL;
2298                 type = DRM_MODE_ENCODER_TMDS;
2299                 break;
2300         default:
2301                 return -ENODEV;
2302         }
2303
2304         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2305         if (!nv_encoder)
2306                 return -ENOMEM;
2307         nv_encoder->dcb = dcbe;
2308         nv_encoder->or = ffs(dcbe->or) - 1;
2309         nv_encoder->i2c = ddc;
2310         nv_encoder->aux = aux;
2311
2312         encoder = to_drm_encoder(nv_encoder);
2313         encoder->possible_crtcs = dcbe->heads;
2314         encoder->possible_clones = 0;
2315         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type, NULL);
2316         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2317
2318         drm_mode_connector_attach_encoder(connector, encoder);
2319         return 0;
2320 }
2321
2322 /******************************************************************************
2323  * Framebuffer
2324  *****************************************************************************/
2325
2326 static void
2327 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2328 {
2329         int i;
2330         for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2331                 nvif_object_fini(&fbdma->base[i]);
2332         nvif_object_fini(&fbdma->core);
2333         list_del(&fbdma->head);
2334         kfree(fbdma);
2335 }
2336
2337 static int
2338 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2339 {
2340         struct nouveau_drm *drm = nouveau_drm(dev);
2341         struct nv50_disp *disp = nv50_disp(dev);
2342         struct nv50_mast *mast = nv50_mast(dev);
2343         struct __attribute__ ((packed)) {
2344                 struct nv_dma_v0 base;
2345                 union {
2346                         struct nv50_dma_v0 nv50;
2347                         struct gf100_dma_v0 gf100;
2348                         struct gf119_dma_v0 gf119;
2349                 };
2350         } args = {};
2351         struct nv50_fbdma *fbdma;
2352         struct drm_crtc *crtc;
2353         u32 size = sizeof(args.base);
2354         int ret;
2355
2356         list_for_each_entry(fbdma, &disp->fbdma, head) {
2357                 if (fbdma->core.handle == name)
2358                         return 0;
2359         }
2360
2361         fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2362         if (!fbdma)
2363                 return -ENOMEM;
2364         list_add(&fbdma->head, &disp->fbdma);
2365
2366         args.base.target = NV_DMA_V0_TARGET_VRAM;
2367         args.base.access = NV_DMA_V0_ACCESS_RDWR;
2368         args.base.start = offset;
2369         args.base.limit = offset + length - 1;
2370
2371         if (drm->device.info.chipset < 0x80) {
2372                 args.nv50.part = NV50_DMA_V0_PART_256;
2373                 size += sizeof(args.nv50);
2374         } else
2375         if (drm->device.info.chipset < 0xc0) {
2376                 args.nv50.part = NV50_DMA_V0_PART_256;
2377                 args.nv50.kind = kind;
2378                 size += sizeof(args.nv50);
2379         } else
2380         if (drm->device.info.chipset < 0xd0) {
2381                 args.gf100.kind = kind;
2382                 size += sizeof(args.gf100);
2383         } else {
2384                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
2385                 args.gf119.kind = kind;
2386                 size += sizeof(args.gf119);
2387         }
2388
2389         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2390                 struct nv50_head *head = nv50_head(crtc);
2391                 int ret = nvif_object_init(&head->sync.base.base.user, name,
2392                                            NV_DMA_IN_MEMORY, &args, size,
2393                                            &fbdma->base[head->base.index]);
2394                 if (ret) {
2395                         nv50_fbdma_fini(fbdma);
2396                         return ret;
2397                 }
2398         }
2399
2400         ret = nvif_object_init(&mast->base.base.user, name, NV_DMA_IN_MEMORY,
2401                                &args, size, &fbdma->core);
2402         if (ret) {
2403                 nv50_fbdma_fini(fbdma);
2404                 return ret;
2405         }
2406
2407         return 0;
2408 }
2409
2410 static void
2411 nv50_fb_dtor(struct drm_framebuffer *fb)
2412 {
2413 }
2414
2415 static int
2416 nv50_fb_ctor(struct drm_framebuffer *fb)
2417 {
2418         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2419         struct nouveau_drm *drm = nouveau_drm(fb->dev);
2420         struct nouveau_bo *nvbo = nv_fb->nvbo;
2421         struct nv50_disp *disp = nv50_disp(fb->dev);
2422         u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2423         u8 tile = nvbo->tile_mode;
2424
2425         if (drm->device.info.chipset >= 0xc0)
2426                 tile >>= 4; /* yep.. */
2427
2428         switch (fb->depth) {
2429         case  8: nv_fb->r_format = 0x1e00; break;
2430         case 15: nv_fb->r_format = 0xe900; break;
2431         case 16: nv_fb->r_format = 0xe800; break;
2432         case 24:
2433         case 32: nv_fb->r_format = 0xcf00; break;
2434         case 30: nv_fb->r_format = 0xd100; break;
2435         default:
2436                  NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2437                  return -EINVAL;
2438         }
2439
2440         if (disp->disp->oclass < G82_DISP) {
2441                 nv_fb->r_pitch   = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2442                                             (fb->pitches[0] | 0x00100000);
2443                 nv_fb->r_format |= kind << 16;
2444         } else
2445         if (disp->disp->oclass < GF110_DISP) {
2446                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2447                                            (fb->pitches[0] | 0x00100000);
2448         } else {
2449                 nv_fb->r_pitch  = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2450                                            (fb->pitches[0] | 0x01000000);
2451         }
2452         nv_fb->r_handle = 0xffff0000 | kind;
2453
2454         return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2455                                drm->device.info.ram_user, kind);
2456 }
2457
2458 /******************************************************************************
2459  * Init
2460  *****************************************************************************/
2461
2462 void
2463 nv50_display_fini(struct drm_device *dev)
2464 {
2465 }
2466
2467 int
2468 nv50_display_init(struct drm_device *dev)
2469 {
2470         struct nv50_disp *disp = nv50_disp(dev);
2471         struct drm_crtc *crtc;
2472         u32 *push;
2473
2474         push = evo_wait(nv50_mast(dev), 32);
2475         if (!push)
2476                 return -EBUSY;
2477
2478         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2479                 struct nv50_sync *sync = nv50_sync(crtc);
2480
2481                 nv50_crtc_lut_load(crtc);
2482                 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2483         }
2484
2485         evo_mthd(push, 0x0088, 1);
2486         evo_data(push, nv50_mast(dev)->base.sync.handle);
2487         evo_kick(push, nv50_mast(dev));
2488         return 0;
2489 }
2490
2491 void
2492 nv50_display_destroy(struct drm_device *dev)
2493 {
2494         struct nv50_disp *disp = nv50_disp(dev);
2495         struct nv50_fbdma *fbdma, *fbtmp;
2496
2497         list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2498                 nv50_fbdma_fini(fbdma);
2499         }
2500
2501         nv50_dmac_destroy(&disp->mast.base, disp->disp);
2502
2503         nouveau_bo_unmap(disp->sync);
2504         if (disp->sync)
2505                 nouveau_bo_unpin(disp->sync);
2506         nouveau_bo_ref(NULL, &disp->sync);
2507
2508         nouveau_display(dev)->priv = NULL;
2509         kfree(disp);
2510 }
2511
2512 int
2513 nv50_display_create(struct drm_device *dev)
2514 {
2515         struct nvif_device *device = &nouveau_drm(dev)->device;
2516         struct nouveau_drm *drm = nouveau_drm(dev);
2517         struct dcb_table *dcb = &drm->vbios.dcb;
2518         struct drm_connector *connector, *tmp;
2519         struct nv50_disp *disp;
2520         struct dcb_output *dcbe;
2521         int crtcs, ret, i;
2522
2523         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2524         if (!disp)
2525                 return -ENOMEM;
2526         INIT_LIST_HEAD(&disp->fbdma);
2527
2528         nouveau_display(dev)->priv = disp;
2529         nouveau_display(dev)->dtor = nv50_display_destroy;
2530         nouveau_display(dev)->init = nv50_display_init;
2531         nouveau_display(dev)->fini = nv50_display_fini;
2532         nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2533         nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2534         disp->disp = &nouveau_display(dev)->disp;
2535
2536         /* small shared memory area we use for notifiers and semaphores */
2537         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2538                              0, 0x0000, NULL, NULL, &disp->sync);
2539         if (!ret) {
2540                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
2541                 if (!ret) {
2542                         ret = nouveau_bo_map(disp->sync);
2543                         if (ret)
2544                                 nouveau_bo_unpin(disp->sync);
2545                 }
2546                 if (ret)
2547                         nouveau_bo_ref(NULL, &disp->sync);
2548         }
2549
2550         if (ret)
2551                 goto out;
2552
2553         /* allocate master evo channel */
2554         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
2555                               &disp->mast);
2556         if (ret)
2557                 goto out;
2558
2559         /* create crtc objects to represent the hw heads */
2560         if (disp->disp->oclass >= GF110_DISP)
2561                 crtcs = nvif_rd32(&device->object, 0x022448);
2562         else
2563                 crtcs = 2;
2564
2565         for (i = 0; i < crtcs; i++) {
2566                 ret = nv50_crtc_create(dev, i);
2567                 if (ret)
2568                         goto out;
2569         }
2570
2571         /* create encoder/connector objects based on VBIOS DCB table */
2572         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2573                 connector = nouveau_connector_create(dev, dcbe->connector);
2574                 if (IS_ERR(connector))
2575                         continue;
2576
2577                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2578                         switch (dcbe->type) {
2579                         case DCB_OUTPUT_TMDS:
2580                         case DCB_OUTPUT_LVDS:
2581                         case DCB_OUTPUT_DP:
2582                                 ret = nv50_sor_create(connector, dcbe);
2583                                 break;
2584                         case DCB_OUTPUT_ANALOG:
2585                                 ret = nv50_dac_create(connector, dcbe);
2586                                 break;
2587                         default:
2588                                 ret = -ENODEV;
2589                                 break;
2590                         }
2591                 } else {
2592                         ret = nv50_pior_create(connector, dcbe);
2593                 }
2594
2595                 if (ret) {
2596                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2597                                      dcbe->location, dcbe->type,
2598                                      ffs(dcbe->or) - 1, ret);
2599                         ret = 0;
2600                 }
2601         }
2602
2603         /* cull any connectors we created that don't have an encoder */
2604         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2605                 if (connector->encoder_ids[0])
2606                         continue;
2607
2608                 NV_WARN(drm, "%s has no encoders, removing\n",
2609                         connector->name);
2610                 connector->funcs->destroy(connector);
2611         }
2612
2613 out:
2614         if (ret)
2615                 nv50_display_destroy(dev);
2616         return ret;
2617 }