drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "gk104.h"
  25 #include "changk104.h"
  26
  27 #include <core/client.h>
  28 #include <core/enum.h>
  29 #include <core/gpuobj.h>
  30 #include <subdev/bar.h>
  31 #include <engine/sw.h>
  32
  33 #include <nvif/class.h>
  34
  35 void
  36 gk104_fifo_uevent_fini(struct nvkm_fifo *fifo)
  37 {
  38         struct nvkm_device *device = fifo->engine.subdev.device;
  39         nvkm_mask(device, 0x002140, 0x80000000, 0x00000000);
  40 }
  41
  42 void
  43 gk104_fifo_uevent_init(struct nvkm_fifo *fifo)
  44 {
  45         struct nvkm_device *device = fifo->engine.subdev.device;
  46         nvkm_mask(device, 0x002140, 0x80000000, 0x80000000);
  47 }
  48
  49 void
  50 gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
  51 {
  52         struct gk104_fifo_chan *chan;
  53         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
  54         struct nvkm_device *device = subdev->device;
  55         struct nvkm_memory *mem;
  56         int nr = 0;
  57         int target;
  58
  59         mutex_lock(&subdev->mutex);
  60         mem = fifo->runlist[runl].mem[fifo->runlist[runl].next];
  61         fifo->runlist[runl].next = !fifo->runlist[runl].next;
  62
  63         nvkm_kmap(mem);
  64         list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
  65                 nvkm_wo32(mem, (nr * 8) + 0, chan->base.chid);
  66                 nvkm_wo32(mem, (nr * 8) + 4, 0x00000000);
  67                 nr++;
  68         }
  69         nvkm_done(mem);
  70
  71         if (nvkm_memory_target(mem) == NVKM_MEM_TARGET_VRAM)
  72                 target = 0;
  73         else
  74                 target = 3;
  75
  76         nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) |
  77                                     (target << 28));
  78         nvkm_wr32(device, 0x002274, (runl << 20) | nr);
  79
  80         if (wait_event_timeout(fifo->runlist[runl].wait,
  81                                !(nvkm_rd32(device, 0x002284 + (runl * 0x08))
  82                                        & 0x00100000),
  83                                msecs_to_jiffies(2000)) == 0)
  84                 nvkm_error(subdev, "runlist %d update timeout\n", runl);
  85         mutex_unlock(&subdev->mutex);
  86 }
  87
  88 void
  89 gk104_fifo_runlist_remove(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
  90 {
  91         mutex_lock(&fifo->base.engine.subdev.mutex);
  92         list_del_init(&chan->head);
  93         mutex_unlock(&fifo->base.engine.subdev.mutex);
  94 }
  95
  96 void
  97 gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
  98 {
  99         mutex_lock(&fifo->base.engine.subdev.mutex);
 100         list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan);
 101         mutex_unlock(&fifo->base.engine.subdev.mutex);
 102 }
 103
 104 static inline struct nvkm_engine *
 105 gk104_fifo_engine(struct gk104_fifo *fifo, u32 engn)
 106 {
 107         struct nvkm_device *device = fifo->base.engine.subdev.device;
 108         u64 subdevs = gk104_fifo_engine_subdev(engn);
 109         if (subdevs)
 110                 return nvkm_device_engine(device, __ffs(subdevs));
 111         return NULL;
 112 }
 113
 114 static void
 115 gk104_fifo_recover_work(struct work_struct *w)
 116 {
 117         struct gk104_fifo *fifo = container_of(w, typeof(*fifo), recover.work);
 118         struct nvkm_device *device = fifo->base.engine.subdev.device;
 119         struct nvkm_engine *engine;
 120         unsigned long flags;
 121         u32 engn, engm = 0;
 122         u64 mask, todo;
 123
 124         spin_lock_irqsave(&fifo->base.lock, flags);
 125         mask = fifo->recover.mask;
 126         fifo->recover.mask = 0ULL;
 127         spin_unlock_irqrestore(&fifo->base.lock, flags);
 128
 129         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn))
 130                 engm |= 1 << gk104_fifo_subdev_engine(engn);
 131         nvkm_mask(device, 0x002630, engm, engm);
 132
 133         for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) {
 134                 if ((engine = nvkm_device_engine(device, engn))) {
 135                         nvkm_subdev_fini(&engine->subdev, false);
 136                         WARN_ON(nvkm_subdev_init(&engine->subdev));
 137                 }
 138                 gk104_fifo_runlist_commit(fifo, gk104_fifo_subdev_engine(engn));
 139         }
 140
 141         nvkm_wr32(device, 0x00262c, engm);
 142         nvkm_mask(device, 0x002630, engm, 0x00000000);
 143 }
 144
 145 static void
 146 gk104_fifo_recover(struct gk104_fifo *fifo, struct nvkm_engine *engine,
 147                   struct gk104_fifo_chan *chan)
 148 {
 149         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 150         struct nvkm_device *device = subdev->device;
 151         u32 chid = chan->base.chid;
 152
 153         nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n",
 154                    nvkm_subdev_name[engine->subdev.index], chid);
 155         assert_spin_locked(&fifo->base.lock);
 156
 157         nvkm_mask(device, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800);
 158         list_del_init(&chan->head);
 159         chan->killed = true;
 160
 161         fifo->recover.mask |= 1ULL << engine->subdev.index;
 162         schedule_work(&fifo->recover.work);
 163 }
 164
 165 static const struct nvkm_enum
 166 gk104_fifo_bind_reason[] = {
 167         { 0x01, "BIND_NOT_UNBOUND" },
 168         { 0x02, "SNOOP_WITHOUT_BAR1" },
 169         { 0x03, "UNBIND_WHILE_RUNNING" },
 170         { 0x05, "INVALID_RUNLIST" },
 171         { 0x06, "INVALID_CTX_TGT" },
 172         { 0x0b, "UNBIND_WHILE_PARKED" },
 173         {}
 174 };
 175
 176 static void
 177 gk104_fifo_intr_bind(struct gk104_fifo *fifo)
 178 {
 179         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 180         struct nvkm_device *device = subdev->device;
 181         u32 intr = nvkm_rd32(device, 0x00252c);
 182         u32 code = intr & 0x000000ff;
 183         const struct nvkm_enum *en =
 184                 nvkm_enum_find(gk104_fifo_bind_reason, code);
 185
 186         nvkm_error(subdev, "BIND_ERROR %02x [%s]\n", code, en ? en->name : "");
 187 }
 188
 189 static const struct nvkm_enum
 190 gk104_fifo_sched_reason[] = {
 191         { 0x0a, "CTXSW_TIMEOUT" },
 192         {}
 193 };
 194
 195 static void
 196 gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
 197 {
 198         struct nvkm_device *device = fifo->base.engine.subdev.device;
 199         struct nvkm_engine *engine;
 200         struct gk104_fifo_chan *chan;
 201         unsigned long flags;
 202         u32 engn;
 203
 204         spin_lock_irqsave(&fifo->base.lock, flags);
 205         for (engn = 0; engn < fifo->engine_nr; engn++) {
 206                 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
 207                 u32 busy = (stat & 0x80000000);
 208                 u32 next = (stat & 0x0fff0000) >> 16;
 209                 u32 chsw = (stat & 0x00008000);
 210                 u32 save = (stat & 0x00004000);
 211                 u32 load = (stat & 0x00002000);
 212                 u32 prev = (stat & 0x00000fff);
 213                 u32 chid = load ? next : prev;
 214                 (void)save;
 215
 216                 if (busy && chsw) {
 217                         list_for_each_entry(chan, &fifo->runlist[engn].chan, head) {
 218                                 if (chan->base.chid == chid) {
 219                                         engine = gk104_fifo_engine(fifo, engn);
 220                                         if (!engine)
 221                                                 break;
 222                                         gk104_fifo_recover(fifo, engine, chan);
 223                                         break;
 224                                 }
 225                         }
 226                 }
 227         }
 228         spin_unlock_irqrestore(&fifo->base.lock, flags);
 229 }
 230
 231 static void
 232 gk104_fifo_intr_sched(struct gk104_fifo *fifo)
 233 {
 234         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 235         struct nvkm_device *device = subdev->device;
 236         u32 intr = nvkm_rd32(device, 0x00254c);
 237         u32 code = intr & 0x000000ff;
 238         const struct nvkm_enum *en =
 239                 nvkm_enum_find(gk104_fifo_sched_reason, code);
 240
 241         nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : "");
 242
 243         switch (code) {
 244         case 0x0a:
 245                 gk104_fifo_intr_sched_ctxsw(fifo);
 246                 break;
 247         default:
 248                 break;
 249         }
 250 }
 251
 252 static void
 253 gk104_fifo_intr_chsw(struct gk104_fifo *fifo)
 254 {
 255         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 256         struct nvkm_device *device = subdev->device;
 257         u32 stat = nvkm_rd32(device, 0x00256c);
 258         nvkm_error(subdev, "CHSW_ERROR %08x\n", stat);
 259         nvkm_wr32(device, 0x00256c, stat);
 260 }
 261
 262 static void
 263 gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo)
 264 {
 265         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 266         struct nvkm_device *device = subdev->device;
 267         u32 stat = nvkm_rd32(device, 0x00259c);
 268         nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat);
 269 }
 270
 271 static const struct nvkm_enum
 272 gk104_fifo_fault_engine[] = {
 273         { 0x00, "GR", NULL, NVKM_ENGINE_GR },
 274         { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
 275         { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
 276         { 0x05, "BAR3", NULL, NVKM_SUBDEV_INSTMEM },
 277         { 0x07, "PBDMA0", NULL, NVKM_ENGINE_FIFO },
 278         { 0x08, "PBDMA1", NULL, NVKM_ENGINE_FIFO },
 279         { 0x09, "PBDMA2", NULL, NVKM_ENGINE_FIFO },
 280         { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
 281         { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },
 282         { 0x13, "PERF" },
 283         { 0x14, "MSPDEC", NULL, NVKM_ENGINE_MSPDEC },
 284         { 0x15, "CE0", NULL, NVKM_ENGINE_CE0 },
 285         { 0x16, "CE1", NULL, NVKM_ENGINE_CE1 },
 286         { 0x17, "PMU" },
 287         { 0x19, "MSENC", NULL, NVKM_ENGINE_MSENC },
 288         { 0x1b, "CE2", NULL, NVKM_ENGINE_CE2 },
 289         {}
 290 };
 291
 292 static const struct nvkm_enum
 293 gk104_fifo_fault_reason[] = {
 294         { 0x00, "PDE" },
 295         { 0x01, "PDE_SIZE" },
 296         { 0x02, "PTE" },
 297         { 0x03, "VA_LIMIT_VIOLATION" },
 298         { 0x04, "UNBOUND_INST_BLOCK" },
 299         { 0x05, "PRIV_VIOLATION" },
 300         { 0x06, "RO_VIOLATION" },
 301         { 0x07, "WO_VIOLATION" },
 302         { 0x08, "PITCH_MASK_VIOLATION" },
 303         { 0x09, "WORK_CREATION" },
 304         { 0x0a, "UNSUPPORTED_APERTURE" },
 305         { 0x0b, "COMPRESSION_FAILURE" },
 306         { 0x0c, "UNSUPPORTED_KIND" },
 307         { 0x0d, "REGION_VIOLATION" },
 308         { 0x0e, "BOTH_PTES_VALID" },
 309         { 0x0f, "INFO_TYPE_POISONED" },
 310         {}
 311 };
 312
 313 static const struct nvkm_enum
 314 gk104_fifo_fault_hubclient[] = {
 315         { 0x00, "VIP" },
 316         { 0x01, "CE0" },
 317         { 0x02, "CE1" },
 318         { 0x03, "DNISO" },
 319         { 0x04, "FE" },
 320         { 0x05, "FECS" },
 321         { 0x06, "HOST" },
 322         { 0x07, "HOST_CPU" },
 323         { 0x08, "HOST_CPU_NB" },
 324         { 0x09, "ISO" },
 325         { 0x0a, "MMU" },
 326         { 0x0b, "MSPDEC" },
 327         { 0x0c, "MSPPP" },
 328         { 0x0d, "MSVLD" },
 329         { 0x0e, "NISO" },
 330         { 0x0f, "P2P" },
 331         { 0x10, "PD" },
 332         { 0x11, "PERF" },
 333         { 0x12, "PMU" },
 334         { 0x13, "RASTERTWOD" },
 335         { 0x14, "SCC" },
 336         { 0x15, "SCC_NB" },
 337         { 0x16, "SEC" },
 338         { 0x17, "SSYNC" },
 339         { 0x18, "GR_CE" },
 340         { 0x19, "CE2" },
 341         { 0x1a, "XV" },
 342         { 0x1b, "MMU_NB" },
 343         { 0x1c, "MSENC" },
 344         { 0x1d, "DFALCON" },
 345         { 0x1e, "SKED" },
 346         { 0x1f, "AFALCON" },
 347         {}
 348 };
 349
 350 static const struct nvkm_enum
 351 gk104_fifo_fault_gpcclient[] = {
 352         { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" },
 353         { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" },
 354         { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" },
 355         { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" },
 356         { 0x0c, "RAST" },
 357         { 0x0d, "GCC" },
 358         { 0x0e, "GPCCS" },
 359         { 0x0f, "PROP_0" },
 360         { 0x10, "PROP_1" },
 361         { 0x11, "PROP_2" },
 362         { 0x12, "PROP_3" },
 363         { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" },
 364         { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" },
 365         { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" },
 366         { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" },
 367         { 0x1f, "GPM" },
 368         { 0x20, "LTP_UTLB_0" },
 369         { 0x21, "LTP_UTLB_1" },
 370         { 0x22, "LTP_UTLB_2" },
 371         { 0x23, "LTP_UTLB_3" },
 372         { 0x24, "GPC_RGG_UTLB" },
 373         {}
 374 };
 375
 376 static void
 377 gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit)
 378 {
 379         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 380         struct nvkm_device *device = subdev->device;
 381         u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10));
 382         u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10));
 383         u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10));
 384         u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10));
 385         u32 gpc    = (stat & 0x1f000000) >> 24;
 386         u32 client = (stat & 0x00001f00) >> 8;
 387         u32 write  = (stat & 0x00000080);
 388         u32 hub    = (stat & 0x00000040);
 389         u32 reason = (stat & 0x0000000f);
 390         const struct nvkm_enum *er, *eu, *ec;
 391         struct nvkm_engine *engine = NULL;
 392         struct nvkm_fifo_chan *chan;
 393         unsigned long flags;
 394         char gpcid[8] = "";
 395
 396         er = nvkm_enum_find(gk104_fifo_fault_reason, reason);
 397         eu = nvkm_enum_find(gk104_fifo_fault_engine, unit);
 398         if (hub) {
 399                 ec = nvkm_enum_find(gk104_fifo_fault_hubclient, client);
 400         } else {
 401                 ec = nvkm_enum_find(gk104_fifo_fault_gpcclient, client);
 402                 snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc);
 403         }
 404
 405         if (eu && eu->data2) {
 406                 switch (eu->data2) {
 407                 case NVKM_SUBDEV_BAR:
 408                         nvkm_mask(device, 0x001704, 0x00000000, 0x00000000);
 409                         break;
 410                 case NVKM_SUBDEV_INSTMEM:
 411                         nvkm_mask(device, 0x001714, 0x00000000, 0x00000000);
 412                         break;
 413                 case NVKM_ENGINE_IFB:
 414                         nvkm_mask(device, 0x001718, 0x00000000, 0x00000000);
 415                         break;
 416                 default:
 417                         engine = nvkm_device_engine(device, eu->data2);
 418                         break;
 419                 }
 420         }
 421
 422         chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags);
 423
 424         nvkm_error(subdev,
 425                    "%s fault at %010llx engine %02x [%s] client %02x [%s%s] "
 426                    "reason %02x [%s] on channel %d [%010llx %s]\n",
 427                    write ? "write" : "read", (u64)vahi << 32 | valo,
 428                    unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "",
 429                    reason, er ? er->name : "", chan ? chan->chid : -1,
 430                    (u64)inst << 12,
 431                    chan ? chan->object.client->name : "unknown");
 432
 433         if (engine && chan)
 434                 gk104_fifo_recover(fifo, engine, (void *)chan);
 435         nvkm_fifo_chan_put(&fifo->base, flags, &chan);
 436 }
 437
 438 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = {
 439         { 0x00000001, "MEMREQ" },
 440         { 0x00000002, "MEMACK_TIMEOUT" },
 441         { 0x00000004, "MEMACK_EXTRA" },
 442         { 0x00000008, "MEMDAT_TIMEOUT" },
 443         { 0x00000010, "MEMDAT_EXTRA" },
 444         { 0x00000020, "MEMFLUSH" },
 445         { 0x00000040, "MEMOP" },
 446         { 0x00000080, "LBCONNECT" },
 447         { 0x00000100, "LBREQ" },
 448         { 0x00000200, "LBACK_TIMEOUT" },
 449         { 0x00000400, "LBACK_EXTRA" },
 450         { 0x00000800, "LBDAT_TIMEOUT" },
 451         { 0x00001000, "LBDAT_EXTRA" },
 452         { 0x00002000, "GPFIFO" },
 453         { 0x00004000, "GPPTR" },
 454         { 0x00008000, "GPENTRY" },
 455         { 0x00010000, "GPCRC" },
 456         { 0x00020000, "PBPTR" },
 457         { 0x00040000, "PBENTRY" },
 458         { 0x00080000, "PBCRC" },
 459         { 0x00100000, "XBARCONNECT" },
 460         { 0x00200000, "METHOD" },
 461         { 0x00400000, "METHODCRC" },
 462         { 0x00800000, "DEVICE" },
 463         { 0x02000000, "SEMAPHORE" },
 464         { 0x04000000, "ACQUIRE" },
 465         { 0x08000000, "PRI" },
 466         { 0x20000000, "NO_CTXSW_SEG" },
 467         { 0x40000000, "PBSEG" },
 468         { 0x80000000, "SIGNATURE" },
 469         {}
 470 };
 471
 472 static void
 473 gk104_fifo_intr_pbdma_0(struct gk104_fifo *fifo, int unit)
 474 {
 475         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 476         struct nvkm_device *device = subdev->device;
 477         u32 mask = nvkm_rd32(device, 0x04010c + (unit * 0x2000));
 478         u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)) & mask;
 479         u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000));
 480         u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000));
 481         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff;
 482         u32 subc = (addr & 0x00070000) >> 16;
 483         u32 mthd = (addr & 0x00003ffc);
 484         u32 show = stat;
 485         struct nvkm_fifo_chan *chan;
 486         unsigned long flags;
 487         char msg[128];
 488
 489         if (stat & 0x00800000) {
 490                 if (device->sw) {
 491                         if (nvkm_sw_mthd(device->sw, chid, subc, mthd, data))
 492                                 show &= ~0x00800000;
 493                 }
 494                 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008);
 495         }
 496
 497         if (show) {
 498                 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_0, show);
 499                 chan = nvkm_fifo_chan_chid(&fifo->base, chid, &flags);
 500                 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%010llx %s] "
 501                                    "subc %d mthd %04x data %08x\n",
 502                            unit, show, msg, chid, chan ? chan->inst->addr : 0,
 503                            chan ? chan->object.client->name : "unknown",
 504                            subc, mthd, data);
 505                 nvkm_fifo_chan_put(&fifo->base, flags, &chan);
 506         }
 507
 508         nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat);
 509 }
 510
 511 static const struct nvkm_bitfield gk104_fifo_pbdma_intr_1[] = {
 512         { 0x00000001, "HCE_RE_ILLEGAL_OP" },
 513         { 0x00000002, "HCE_RE_ALIGNB" },
 514         { 0x00000004, "HCE_PRIV" },
 515         { 0x00000008, "HCE_ILLEGAL_MTHD" },
 516         { 0x00000010, "HCE_ILLEGAL_CLASS" },
 517         {}
 518 };
 519
 520 static void
 521 gk104_fifo_intr_pbdma_1(struct gk104_fifo *fifo, int unit)
 522 {
 523         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 524         struct nvkm_device *device = subdev->device;
 525         u32 mask = nvkm_rd32(device, 0x04014c + (unit * 0x2000));
 526         u32 stat = nvkm_rd32(device, 0x040148 + (unit * 0x2000)) & mask;
 527         u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0xfff;
 528         char msg[128];
 529
 530         if (stat) {
 531                 nvkm_snprintbf(msg, sizeof(msg), gk104_fifo_pbdma_intr_1, stat);
 532                 nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d %08x %08x\n",
 533                            unit, stat, msg, chid,
 534                            nvkm_rd32(device, 0x040150 + (unit * 0x2000)),
 535                            nvkm_rd32(device, 0x040154 + (unit * 0x2000)));
 536         }
 537
 538         nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat);
 539 }
 540
 541 static void
 542 gk104_fifo_intr_runlist(struct gk104_fifo *fifo)
 543 {
 544         struct nvkm_device *device = fifo->base.engine.subdev.device;
 545         u32 mask = nvkm_rd32(device, 0x002a00);
 546         while (mask) {
 547                 int runl = __ffs(mask);
 548                 wake_up(&fifo->runlist[runl].wait);
 549                 nvkm_wr32(device, 0x002a00, 1 << runl);
 550                 mask &= ~(1 << runl);
 551         }
 552 }
 553
 554 static void
 555 gk104_fifo_intr_engine(struct gk104_fifo *fifo)
 556 {
 557         nvkm_fifo_uevent(&fifo->base);
 558 }
 559
 560 void
 561 gk104_fifo_intr(struct nvkm_fifo *base)
 562 {
 563         struct gk104_fifo *fifo = gk104_fifo(base);
 564         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 565         struct nvkm_device *device = subdev->device;
 566         u32 mask = nvkm_rd32(device, 0x002140);
 567         u32 stat = nvkm_rd32(device, 0x002100) & mask;
 568
 569         if (stat & 0x00000001) {
 570                 gk104_fifo_intr_bind(fifo);
 571                 nvkm_wr32(device, 0x002100, 0x00000001);
 572                 stat &= ~0x00000001;
 573         }
 574
 575         if (stat & 0x00000010) {
 576                 nvkm_error(subdev, "PIO_ERROR\n");
 577                 nvkm_wr32(device, 0x002100, 0x00000010);
 578                 stat &= ~0x00000010;
 579         }
 580
 581         if (stat & 0x00000100) {
 582                 gk104_fifo_intr_sched(fifo);
 583                 nvkm_wr32(device, 0x002100, 0x00000100);
 584                 stat &= ~0x00000100;
 585         }
 586
 587         if (stat & 0x00010000) {
 588                 gk104_fifo_intr_chsw(fifo);
 589                 nvkm_wr32(device, 0x002100, 0x00010000);
 590                 stat &= ~0x00010000;
 591         }
 592
 593         if (stat & 0x00800000) {
 594                 nvkm_error(subdev, "FB_FLUSH_TIMEOUT\n");
 595                 nvkm_wr32(device, 0x002100, 0x00800000);
 596                 stat &= ~0x00800000;
 597         }
 598
 599         if (stat & 0x01000000) {
 600                 nvkm_error(subdev, "LB_ERROR\n");
 601                 nvkm_wr32(device, 0x002100, 0x01000000);
 602                 stat &= ~0x01000000;
 603         }
 604
 605         if (stat & 0x08000000) {
 606                 gk104_fifo_intr_dropped_fault(fifo);
 607                 nvkm_wr32(device, 0x002100, 0x08000000);
 608                 stat &= ~0x08000000;
 609         }
 610
 611         if (stat & 0x10000000) {
 612                 u32 mask = nvkm_rd32(device, 0x00259c);
 613                 while (mask) {
 614                         u32 unit = __ffs(mask);
 615                         gk104_fifo_intr_fault(fifo, unit);
 616                         nvkm_wr32(device, 0x00259c, (1 << unit));
 617                         mask &= ~(1 << unit);
 618                 }
 619                 stat &= ~0x10000000;
 620         }
 621
 622         if (stat & 0x20000000) {
 623                 u32 mask = nvkm_rd32(device, 0x0025a0);
 624                 while (mask) {
 625                         u32 unit = __ffs(mask);
 626                         gk104_fifo_intr_pbdma_0(fifo, unit);
 627                         gk104_fifo_intr_pbdma_1(fifo, unit);
 628                         nvkm_wr32(device, 0x0025a0, (1 << unit));
 629                         mask &= ~(1 << unit);
 630                 }
 631                 stat &= ~0x20000000;
 632         }
 633
 634         if (stat & 0x40000000) {
 635                 gk104_fifo_intr_runlist(fifo);
 636                 stat &= ~0x40000000;
 637         }
 638
 639         if (stat & 0x80000000) {
 640                 nvkm_wr32(device, 0x002100, 0x80000000);
 641                 gk104_fifo_intr_engine(fifo);
 642                 stat &= ~0x80000000;
 643         }
 644
 645         if (stat) {
 646                 nvkm_error(subdev, "INTR %08x\n", stat);
 647                 nvkm_mask(device, 0x002140, stat, 0x00000000);
 648                 nvkm_wr32(device, 0x002100, stat);
 649         }
 650 }
 651
 652 void
 653 gk104_fifo_fini(struct nvkm_fifo *base)
 654 {
 655         struct gk104_fifo *fifo = gk104_fifo(base);
 656         struct nvkm_device *device = fifo->base.engine.subdev.device;
 657         flush_work(&fifo->recover.work);
 658         /* allow mmu fault interrupts, even when we're not using fifo */
 659         nvkm_mask(device, 0x002140, 0x10000000, 0x10000000);
 660 }
 661
 662 int
 663 gk104_fifo_oneinit(struct nvkm_fifo *base)
 664 {
 665         struct gk104_fifo *fifo = gk104_fifo(base);
 666         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
 667         struct nvkm_device *device = subdev->device;
 668         int ret, i;
 669         u32 *map;
 670
 671         /* Determine number of PBDMAs by checking valid enable bits. */
 672         nvkm_wr32(device, 0x000204, 0xffffffff);
 673         fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204));
 674         nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
 675
 676         /* Read PBDMA->runlist(s) mapping from HW. */
 677         if (!(map = kzalloc(sizeof(*map) * fifo->pbdma_nr, GFP_KERNEL)))
 678                 return -ENOMEM;
 679
 680         for (i = 0; i < fifo->pbdma_nr; i++)
 681                 map[i] = nvkm_rd32(device, 0x002390 + (i * 0x04));
 682
 683         /* Read device topology from HW. */
 684         for (i = 0; i < 64; i++) {
 685                 int type = -1, pbid = -1, engidx = -1;
 686                 int engn = -1, runl = -1, intr = -1, mcen = -1;
 687                 int fault = -1, j;
 688                 u32 data, addr = 0;
 689
 690                 do {
 691                         data = nvkm_rd32(device, 0x022700 + (i * 0x04));
 692                         nvkm_trace(subdev, "%02x: %08x\n", i, data);
 693                         switch (data & 0x00000003) {
 694                         case 0x00000000: /* NOT_VALID */
 695                                 continue;
 696                         case 0x00000001: /* DATA */
 697                                 addr  = (data & 0x00fff000);
 698                                 fault = (data & 0x000000f8) >> 3;
 699                                 break;
 700                         case 0x00000002: /* ENUM */
 701                                 if (data & 0x00000020)
 702                                         engn = (data & 0x3c000000) >> 26;
 703                                 if (data & 0x00000010)
 704                                         runl = (data & 0x01e00000) >> 21;
 705                                 if (data & 0x00000008)
 706                                         intr = (data & 0x000f8000) >> 15;
 707                                 if (data & 0x00000004)
 708                                         mcen = (data & 0x00003e00) >> 9;
 709                                 break;
 710                         case 0x00000003: /* ENGINE_TYPE */
 711                                 type = (data & 0x7ffffffc) >> 2;
 712                                 break;
 713                         }
 714                 } while ((data & 0x80000000) && ++i < 64);
 715
 716                 if (!data)
 717                         continue;
 718
 719                 /* Determine which PBDMA handles requests for this engine. */
 720                 for (j = 0; runl >= 0 && j < fifo->pbdma_nr; j++) {
 721                         if (map[j] & (1 << runl)) {
 722                                 pbid = j;
 723                                 break;
 724                         }
 725                 }
 726
 727                 /* Translate engine type to NVKM engine identifier. */
 728                 switch (type) {
 729                 case 0x00000000: engidx = NVKM_ENGINE_GR; break;
 730                 case 0x00000001: engidx = NVKM_ENGINE_CE0; break;
 731                 case 0x00000002: engidx = NVKM_ENGINE_CE1; break;
 732                 case 0x00000003: engidx = NVKM_ENGINE_CE2; break;
 733                 case 0x00000008: engidx = NVKM_ENGINE_MSPDEC; break;
 734                 case 0x00000009: engidx = NVKM_ENGINE_MSPPP; break;
 735                 case 0x0000000a: engidx = NVKM_ENGINE_MSVLD; break;
 736                 case 0x0000000b: engidx = NVKM_ENGINE_MSENC; break;
 737                 case 0x0000000c: engidx = NVKM_ENGINE_VIC; break;
 738                 case 0x0000000d: engidx = NVKM_ENGINE_SEC; break;
 739                         break;
 740                 default:
 741                         break;
 742                 }
 743
 744                 nvkm_debug(subdev, "%02x (%8s): engine %2d runlist %2d "
 745                                    "pbdma %2d intr %2d reset %2d "
 746                                    "fault %2d addr %06x\n", type,
 747                            engidx < 0 ? NULL : nvkm_subdev_name[engidx],
 748                            engn, runl, pbid, intr, mcen, fault, addr);
 749
 750                 /* Mark the engine as supported if everything checks out. */
 751                 if (engn >= 0 && runl >= 0) {
 752                         fifo->engine[engn].engine = engidx < 0 ? NULL :
 753                                 nvkm_device_engine(device, engidx);
 754                         fifo->engine[engn].runl = runl;
 755                         fifo->engine[engn].pbid = pbid;
 756                         fifo->engine_nr = max(fifo->engine_nr, engn + 1);
 757                         fifo->runlist[runl].engm |= 1 << engn;
 758                         fifo->runlist_nr = max(fifo->runlist_nr, runl + 1);
 759                 }
 760         }
 761
 762         kfree(map);
 763
 764         for (i = 0; i < fifo->runlist_nr; i++) {
 765                 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 766                                       0x8000, 0x1000, false,
 767                                       &fifo->runlist[i].mem[0]);
 768                 if (ret)
 769                         return ret;
 770
 771                 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 772                                       0x8000, 0x1000, false,
 773                                       &fifo->runlist[i].mem[1]);
 774                 if (ret)
 775                         return ret;
 776
 777                 init_waitqueue_head(&fifo->runlist[i].wait);
 778                 INIT_LIST_HEAD(&fifo->runlist[i].chan);
 779         }
 780
 781         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
 782                               fifo->base.nr * 0x200, 0x1000, true,
 783                               &fifo->user.mem);
 784         if (ret)
 785                 return ret;
 786
 787         ret = nvkm_bar_umap(device->bar, fifo->base.nr * 0x200, 12,
 788                             &fifo->user.bar);
 789         if (ret)
 790                 return ret;
 791
 792         nvkm_memory_map(fifo->user.mem, &fifo->user.bar, 0);
 793         return 0;
 794 }
 795
 796 void
 797 gk104_fifo_init(struct nvkm_fifo *base)
 798 {
 799         struct gk104_fifo *fifo = gk104_fifo(base);
 800         struct nvkm_device *device = fifo->base.engine.subdev.device;
 801         int i;
 802
 803         /* Enable PBDMAs. */
 804         nvkm_wr32(device, 0x000204, (1 << fifo->pbdma_nr) - 1);
 805
 806         /* PBDMA[n] */
 807         for (i = 0; i < fifo->pbdma_nr; i++) {
 808                 nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 809                 nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 810                 nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 811         }
 812
 813         /* PBDMA[n].HCE */
 814         for (i = 0; i < fifo->pbdma_nr; i++) {
 815                 nvkm_wr32(device, 0x040148 + (i * 0x2000), 0xffffffff); /* INTR */
 816                 nvkm_wr32(device, 0x04014c + (i * 0x2000), 0xffffffff); /* INTREN */
 817         }
 818
 819         nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12);
 820
 821         nvkm_wr32(device, 0x002100, 0xffffffff);
 822         nvkm_wr32(device, 0x002140, 0x7fffffff);
 823 }
 824
 825 void *
 826 gk104_fifo_dtor(struct nvkm_fifo *base)
 827 {
 828         struct gk104_fifo *fifo = gk104_fifo(base);
 829         int i;
 830
 831         nvkm_vm_put(&fifo->user.bar);
 832         nvkm_memory_del(&fifo->user.mem);
 833
 834         for (i = 0; i < fifo->runlist_nr; i++) {
 835                 nvkm_memory_del(&fifo->runlist[i].mem[1]);
 836                 nvkm_memory_del(&fifo->runlist[i].mem[0]);
 837         }
 838
 839         return fifo;
 840 }
 841
 842 int
 843 gk104_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device,
 844                 int index, int nr, struct nvkm_fifo **pfifo)
 845 {
 846         struct gk104_fifo *fifo;
 847
 848         if (!(fifo = kzalloc(sizeof(*fifo), GFP_KERNEL)))
 849                 return -ENOMEM;
 850         INIT_WORK(&fifo->recover.work, gk104_fifo_recover_work);
 851         *pfifo = &fifo->base;
 852
 853         return nvkm_fifo_ctor(func, device, index, nr, &fifo->base);
 854 }
 855
 856 static const struct nvkm_fifo_func
 857 gk104_fifo = {
 858         .dtor = gk104_fifo_dtor,
 859         .oneinit = gk104_fifo_oneinit,
 860         .init = gk104_fifo_init,
 861         .fini = gk104_fifo_fini,
 862         .intr = gk104_fifo_intr,
 863         .uevent_init = gk104_fifo_uevent_init,
 864         .uevent_fini = gk104_fifo_uevent_fini,
 865         .chan = {
 866                 &gk104_fifo_gpfifo_oclass,
 867                 NULL
 868         },
 869 };
 870
 871 int
 872 gk104_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
 873 {
 874         return gk104_fifo_new_(&gk104_fifo, device, index, 4096, pfifo);
 875 }