4 #include <engine/fifo.h>
6 /*******************************************************************************
7 * Graphics object classes
8 ******************************************************************************/
10 static struct nvkm_oclass
12 { 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
13 { 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
14 { 0x0030, &nv04_gr_ofuncs, NULL }, /* null */
15 { 0x0039, &nv04_gr_ofuncs, NULL }, /* m2mf */
16 { 0x0043, &nv04_gr_ofuncs, NULL }, /* rop */
17 { 0x0044, &nv04_gr_ofuncs, NULL }, /* patt */
18 { 0x004a, &nv04_gr_ofuncs, NULL }, /* gdi */
19 { 0x0062, &nv04_gr_ofuncs, NULL }, /* surf2d */
20 { 0x0072, &nv04_gr_ofuncs, NULL }, /* beta4 */
21 { 0x0089, &nv04_gr_ofuncs, NULL }, /* sifm */
22 { 0x008a, &nv04_gr_ofuncs, NULL }, /* ifc */
23 { 0x009f, &nv04_gr_ofuncs, NULL }, /* imageblit */
24 { 0x0362, &nv04_gr_ofuncs, NULL }, /* surf2d (nv30) */
25 { 0x0389, &nv04_gr_ofuncs, NULL }, /* sifm (nv30) */
26 { 0x038a, &nv04_gr_ofuncs, NULL }, /* ifc (nv30) */
27 { 0x039e, &nv04_gr_ofuncs, NULL }, /* swzsurf (nv30) */
28 { 0x0697, &nv04_gr_ofuncs, NULL }, /* rankine */
32 /*******************************************************************************
34 ******************************************************************************/
37 nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
38 struct nvkm_oclass *oclass, void *data, u32 size,
39 struct nvkm_object **pobject)
41 struct nv20_gr_chan *chan;
42 struct nvkm_gpuobj *image;
45 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
46 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
47 *pobject = nv_object(chan);
51 chan->chid = nvkm_fifo_chan(parent)->chid;
52 image = &chan->base.base.gpuobj;
55 nvkm_wo32(image, 0x0028, 0x00000001 | (chan->chid << 24));
56 nvkm_wo32(image, 0x040c, 0x01000101);
57 nvkm_wo32(image, 0x0420, 0x00000111);
58 nvkm_wo32(image, 0x0424, 0x00000060);
59 nvkm_wo32(image, 0x0440, 0x00000080);
60 nvkm_wo32(image, 0x0444, 0xffff0000);
61 nvkm_wo32(image, 0x0448, 0x00000001);
62 nvkm_wo32(image, 0x045c, 0x44400000);
63 nvkm_wo32(image, 0x0480, 0xffff0000);
64 for (i = 0x04d4; i < 0x04dc; i += 4)
65 nvkm_wo32(image, i, 0x0fff0000);
66 nvkm_wo32(image, 0x04e0, 0x00011100);
67 for (i = 0x04fc; i < 0x053c; i += 4)
68 nvkm_wo32(image, i, 0x07ff0000);
69 nvkm_wo32(image, 0x0544, 0x4b7fffff);
70 nvkm_wo32(image, 0x057c, 0x00000080);
71 nvkm_wo32(image, 0x0580, 0x30201000);
72 nvkm_wo32(image, 0x0584, 0x70605040);
73 nvkm_wo32(image, 0x0588, 0xb8a89888);
74 nvkm_wo32(image, 0x058c, 0xf8e8d8c8);
75 nvkm_wo32(image, 0x05a0, 0xb0000000);
76 for (i = 0x05f0; i < 0x0630; i += 4)
77 nvkm_wo32(image, i, 0x00010588);
78 for (i = 0x0630; i < 0x0670; i += 4)
79 nvkm_wo32(image, i, 0x00030303);
80 for (i = 0x06b0; i < 0x06f0; i += 4)
81 nvkm_wo32(image, i, 0x0008aae4);
82 for (i = 0x06f0; i < 0x0730; i += 4)
83 nvkm_wo32(image, i, 0x01012000);
84 for (i = 0x0730; i < 0x0770; i += 4)
85 nvkm_wo32(image, i, 0x00080008);
86 nvkm_wo32(image, 0x0850, 0x00040000);
87 nvkm_wo32(image, 0x0854, 0x00010000);
88 for (i = 0x0858; i < 0x0868; i += 4)
89 nvkm_wo32(image, i, 0x00040004);
90 for (i = 0x15ac; i <= 0x271c ; i += 16) {
91 nvkm_wo32(image, i + 0, 0x10700ff9);
92 nvkm_wo32(image, i + 1, 0x0436086c);
93 nvkm_wo32(image, i + 2, 0x000c001b);
95 for (i = 0x274c; i < 0x275c; i += 4)
96 nvkm_wo32(image, i, 0x0000ffff);
97 nvkm_wo32(image, 0x2ae0, 0x3f800000);
98 nvkm_wo32(image, 0x2e9c, 0x3f800000);
99 nvkm_wo32(image, 0x2eb0, 0x3f800000);
100 nvkm_wo32(image, 0x2edc, 0x40000000);
101 nvkm_wo32(image, 0x2ee0, 0x3f800000);
102 nvkm_wo32(image, 0x2ee4, 0x3f000000);
103 nvkm_wo32(image, 0x2eec, 0x40000000);
104 nvkm_wo32(image, 0x2ef0, 0x3f800000);
105 nvkm_wo32(image, 0x2ef8, 0xbf800000);
106 nvkm_wo32(image, 0x2f00, 0xbf800000);
111 static struct nvkm_oclass
113 .handle = NV_ENGCTX(GR, 0x34),
114 .ofuncs = &(struct nvkm_ofuncs) {
115 .ctor = nv34_gr_context_ctor,
116 .dtor = _nvkm_gr_context_dtor,
117 .init = nv20_gr_context_init,
118 .fini = nv20_gr_context_fini,
119 .rd32 = _nvkm_gr_context_rd32,
120 .wr32 = _nvkm_gr_context_wr32,
124 /*******************************************************************************
125 * PGRAPH engine/subdev functions
126 ******************************************************************************/
129 nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
130 struct nvkm_oclass *oclass, void *data, u32 size,
131 struct nvkm_object **pobject)
136 ret = nvkm_gr_create(parent, engine, oclass, true, &gr);
137 *pobject = nv_object(gr);
141 ret = nvkm_gpuobj_new(nv_object(gr), NULL, 32 * 4, 16,
142 NVOBJ_FLAG_ZERO_ALLOC, &gr->ctxtab);
146 nv_subdev(gr)->unit = 0x00001000;
147 nv_subdev(gr)->intr = nv20_gr_intr;
148 nv_engine(gr)->cclass = &nv34_gr_cclass;
149 nv_engine(gr)->sclass = nv34_gr_sclass;
150 nv_engine(gr)->tile_prog = nv20_gr_tile_prog;
156 .handle = NV_ENGINE(GR, 0x34),
157 .ofuncs = &(struct nvkm_ofuncs) {
158 .ctor = nv34_gr_ctor,
159 .dtor = nv20_gr_dtor,
160 .init = nv30_gr_init,
161 .fini = _nvkm_gr_fini,