2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/bmp.h>
27 #include <subdev/bios/conn.h>
28 #include <subdev/bios/dcb.h>
29 #include <subdev/bios/dp.h>
30 #include <subdev/bios/gpio.h>
31 #include <subdev/bios/init.h>
32 #include <subdev/bios/ramcfg.h>
34 #include <core/device.h>
35 #include <subdev/devinit.h>
36 #include <subdev/gpio.h>
37 #include <subdev/i2c.h>
38 #include <subdev/vga.h>
40 #define bioslog(lvl, fmt, args...) do { \
41 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
42 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
44 #define cont(fmt, args...) do { \
45 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
46 printk(fmt, ##args); \
48 #define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
49 #define warn(fmt, args...) bioslog(WARN, fmt, ##args)
50 #define error(fmt, args...) bioslog(ERROR, fmt, ##args)
52 /******************************************************************************
53 * init parser control flow helpers
54 *****************************************************************************/
57 init_exec(struct nvbios_init *init)
59 return (init->execute == 1) || ((init->execute & 5) == 5);
63 init_exec_set(struct nvbios_init *init, bool exec)
65 if (exec) init->execute &= 0xfd;
66 else init->execute |= 0x02;
70 init_exec_inv(struct nvbios_init *init)
72 init->execute ^= 0x02;
76 init_exec_force(struct nvbios_init *init, bool exec)
78 if (exec) init->execute |= 0x04;
79 else init->execute &= 0xfb;
82 /******************************************************************************
83 * init parser wrappers for normal register/i2c/whatever accessors
84 *****************************************************************************/
87 init_or(struct nvbios_init *init)
89 if (init_exec(init)) {
91 return ffs(init->outp->or) - 1;
92 error("script needs OR!!\n");
98 init_link(struct nvbios_init *init)
100 if (init_exec(init)) {
102 return !(init->outp->sorconf.link & 1);
103 error("script needs OR link\n");
109 init_crtc(struct nvbios_init *init)
111 if (init_exec(init)) {
114 error("script needs crtc\n");
120 init_conn(struct nvbios_init *init)
122 struct nvkm_bios *bios = init->bios;
123 struct nvbios_connE connE;
127 if (init_exec(init)) {
129 conn = init->outp->connector;
130 conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE);
135 error("script needs connector type\n");
142 init_nvreg(struct nvbios_init *init, u32 reg)
144 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
146 /* C51 (at least) sometimes has the lower bits set which the VBIOS
147 * interprets to mean that access needs to go through certain IO
148 * ports instead. The NVIDIA binary driver has been seen to access
149 * these through the NV register address, so lets assume we can
154 /* GF8+ display scripts need register addresses mangled a bit to
155 * select a specific CRTC/OR
157 if (nv_device(init->bios)->card_type >= NV_50) {
158 if (reg & 0x80000000) {
159 reg += init_crtc(init) * 0x800;
163 if (reg & 0x40000000) {
164 reg += init_or(init) * 0x800;
166 if (reg & 0x20000000) {
167 reg += init_link(init) * 0x80;
173 if (reg & ~0x00fffffc)
174 warn("unknown bits in register 0x%08x\n", reg);
177 reg = devinit->mmio(devinit, reg);
182 init_rd32(struct nvbios_init *init, u32 reg)
184 reg = init_nvreg(init, reg);
185 if (reg != ~0 && init_exec(init))
186 return nv_rd32(init->subdev, reg);
191 init_wr32(struct nvbios_init *init, u32 reg, u32 val)
193 reg = init_nvreg(init, reg);
194 if (reg != ~0 && init_exec(init))
195 nv_wr32(init->subdev, reg, val);
199 init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
201 reg = init_nvreg(init, reg);
202 if (reg != ~0 && init_exec(init)) {
203 u32 tmp = nv_rd32(init->subdev, reg);
204 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
211 init_rdport(struct nvbios_init *init, u16 port)
214 return nv_rdport(init->subdev, init->crtc, port);
219 init_wrport(struct nvbios_init *init, u16 port, u8 value)
222 nv_wrport(init->subdev, init->crtc, port, value);
226 init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
228 struct nvkm_subdev *subdev = init->subdev;
229 if (init_exec(init)) {
230 int head = init->crtc < 0 ? 0 : init->crtc;
231 return nv_rdvgai(subdev, head, port, index);
237 init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
239 /* force head 0 for updates to cr44, it only exists on first head */
240 if (nv_device(init->subdev)->card_type < NV_50) {
241 if (port == 0x03d4 && index == 0x44)
245 if (init_exec(init)) {
246 int head = init->crtc < 0 ? 0 : init->crtc;
247 nv_wrvgai(init->subdev, head, port, index, value);
250 /* select head 1 if cr44 write selected it */
251 if (nv_device(init->subdev)->card_type < NV_50) {
252 if (port == 0x03d4 && index == 0x44 && value == 3)
257 static struct nvkm_i2c_port *
258 init_i2c(struct nvbios_init *init, int index)
260 struct nvkm_i2c *i2c = nvkm_i2c(init->bios);
263 index = NV_I2C_DEFAULT(0);
264 if (init->outp && init->outp->i2c_upper_default)
265 index = NV_I2C_DEFAULT(1);
270 error("script needs output for i2c\n");
274 if (index == -2 && init->outp->location) {
275 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
276 return i2c->find_type(i2c, index);
279 index = init->outp->i2c_index;
280 if (init->outp->type == DCB_OUTPUT_DP)
281 index += NV_I2C_AUX(0);
284 return i2c->find(i2c, index);
288 init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
290 struct nvkm_i2c_port *port = init_i2c(init, index);
291 if (port && init_exec(init))
292 return nv_rdi2cr(port, addr, reg);
297 init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
299 struct nvkm_i2c_port *port = init_i2c(init, index);
300 if (port && init_exec(init))
301 return nv_wri2cr(port, addr, reg, val);
306 init_rdauxr(struct nvbios_init *init, u32 addr)
308 struct nvkm_i2c_port *port = init_i2c(init, -2);
311 if (port && init_exec(init)) {
312 int ret = nv_rdaux(port, addr, &data, 1);
315 trace("auxch read failed with %d\n", ret);
322 init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
324 struct nvkm_i2c_port *port = init_i2c(init, -2);
325 if (port && init_exec(init)) {
326 int ret = nv_wraux(port, addr, &data, 1);
328 trace("auxch write failed with %d\n", ret);
335 init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
337 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
338 if (devinit->pll_set && init_exec(init)) {
339 int ret = devinit->pll_set(devinit, id, freq);
341 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
345 /******************************************************************************
346 * parsing of bios structures that are required to execute init tables
347 *****************************************************************************/
350 init_table(struct nvkm_bios *bios, u16 *len)
352 struct bit_entry bit_I;
354 if (!bit_entry(bios, 'I', &bit_I)) {
359 if (bmp_version(bios) >= 0x0510) {
361 return bios->bmp_offset + 75;
368 init_table_(struct nvbios_init *init, u16 offset, const char *name)
370 struct nvkm_bios *bios = init->bios;
371 u16 len, data = init_table(bios, &len);
373 if (len >= offset + 2) {
374 data = nv_ro16(bios, data + offset);
378 warn("%s pointer invalid\n", name);
382 warn("init data too short for %s pointer", name);
386 warn("init data not found\n");
390 #define init_script_table(b) init_table_((b), 0x00, "script table")
391 #define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
392 #define init_macro_table(b) init_table_((b), 0x04, "macro table")
393 #define init_condition_table(b) init_table_((b), 0x06, "condition table")
394 #define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
395 #define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
396 #define init_function_table(b) init_table_((b), 0x0c, "function table")
397 #define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
400 init_script(struct nvkm_bios *bios, int index)
402 struct nvbios_init init = { .bios = bios };
403 u16 bmp_ver = bmp_version(bios), data;
405 if (bmp_ver && bmp_ver < 0x0510) {
406 if (index > 1 || bmp_ver < 0x0100)
409 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
410 return nv_ro16(bios, data + (index * 2));
413 data = init_script_table(&init);
415 return nv_ro16(bios, data + (index * 2));
421 init_unknown_script(struct nvkm_bios *bios)
423 u16 len, data = init_table(bios, &len);
424 if (data && len >= 16)
425 return nv_ro16(bios, data + 14);
430 init_ram_restrict_group_count(struct nvbios_init *init)
432 return nvbios_ramcfg_count(init->bios);
436 init_ram_restrict(struct nvbios_init *init)
438 /* This appears to be the behaviour of the VBIOS parser, and *is*
439 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
440 * avoid fucking up the memory controller (somehow) by reading it
441 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
443 * Preserving the non-caching behaviour on earlier chipsets just
444 * in case *not* re-reading the strap causes similar breakage.
446 if (!init->ramcfg || init->bios->version.major < 0x70)
447 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
448 return (init->ramcfg & 0x7fffffff);
452 init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
454 struct nvkm_bios *bios = init->bios;
455 u16 table = init_xlat_table(init);
457 u16 data = nv_ro16(bios, table + (index * 2));
459 return nv_ro08(bios, data + offset);
460 warn("xlat table pointer %d invalid\n", index);
465 /******************************************************************************
466 * utility functions used by various init opcode handlers
467 *****************************************************************************/
470 init_condition_met(struct nvbios_init *init, u8 cond)
472 struct nvkm_bios *bios = init->bios;
473 u16 table = init_condition_table(init);
475 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
476 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
477 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
478 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
479 cond, reg, msk, val);
480 return (init_rd32(init, reg) & msk) == val;
486 init_io_condition_met(struct nvbios_init *init, u8 cond)
488 struct nvkm_bios *bios = init->bios;
489 u16 table = init_io_condition_table(init);
491 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
492 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
493 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
494 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
495 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
496 cond, port, index, mask, value);
497 return (init_rdvgai(init, port, index) & mask) == value;
503 init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
505 struct nvkm_bios *bios = init->bios;
506 u16 table = init_io_flag_condition_table(init);
508 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
509 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
510 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
511 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
512 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
513 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
514 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
515 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
516 return (nv_ro08(bios, data + ioval) & dmask) == value;
522 init_shift(u32 data, u8 shift)
525 return data >> shift;
526 return data << (0x100 - shift);
530 init_tmds_reg(struct nvbios_init *init, u8 tmds)
532 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
533 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
534 * CR58 for CR57 = 0 to index a table of offsets to the basic
536 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
537 * CR58 for CR57 = 0 to index a table of offsets to the basic
538 * 0x6808b0 address, and then flip the offset by 8.
540 const int pramdac_offset[13] = {
541 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
542 const u32 pramdac_table[4] = {
543 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
547 u32 dacoffset = pramdac_offset[init->outp->or];
550 return 0x6808b0 + dacoffset;
554 error("tmds opcodes need dcb\n");
556 if (tmds < ARRAY_SIZE(pramdac_table))
557 return pramdac_table[tmds];
559 error("tmds selector 0x%02x unknown\n", tmds);
565 /******************************************************************************
566 * init opcode handlers
567 *****************************************************************************/
570 * init_reserved - stub for various unknown/unused single-byte opcodes
574 init_reserved(struct nvbios_init *init)
576 u8 opcode = nv_ro08(init->bios, init->offset);
588 trace("RESERVED 0x%02x\t", opcode);
589 for (i = 1; i < length; i++)
590 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
592 init->offset += length;
596 * INIT_DONE - opcode 0x71
600 init_done(struct nvbios_init *init)
603 init->offset = 0x0000;
607 * INIT_IO_RESTRICT_PROG - opcode 0x32
611 init_io_restrict_prog(struct nvbios_init *init)
613 struct nvkm_bios *bios = init->bios;
614 u16 port = nv_ro16(bios, init->offset + 1);
615 u8 index = nv_ro08(bios, init->offset + 3);
616 u8 mask = nv_ro08(bios, init->offset + 4);
617 u8 shift = nv_ro08(bios, init->offset + 5);
618 u8 count = nv_ro08(bios, init->offset + 6);
619 u32 reg = nv_ro32(bios, init->offset + 7);
622 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
623 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
624 reg, port, index, mask, shift);
627 conf = (init_rdvgai(init, port, index) & mask) >> shift;
628 for (i = 0; i < count; i++) {
629 u32 data = nv_ro32(bios, init->offset);
632 trace("\t0x%08x *\n", data);
633 init_wr32(init, reg, data);
635 trace("\t0x%08x\n", data);
644 * INIT_REPEAT - opcode 0x33
648 init_repeat(struct nvbios_init *init)
650 struct nvkm_bios *bios = init->bios;
651 u8 count = nv_ro08(bios, init->offset + 1);
652 u16 repeat = init->repeat;
654 trace("REPEAT\t0x%02x\n", count);
657 init->repeat = init->offset;
658 init->repend = init->offset;
660 init->offset = init->repeat;
663 trace("REPEAT\t0x%02x\n", count);
665 init->offset = init->repend;
666 init->repeat = repeat;
670 * INIT_IO_RESTRICT_PLL - opcode 0x34
674 init_io_restrict_pll(struct nvbios_init *init)
676 struct nvkm_bios *bios = init->bios;
677 u16 port = nv_ro16(bios, init->offset + 1);
678 u8 index = nv_ro08(bios, init->offset + 3);
679 u8 mask = nv_ro08(bios, init->offset + 4);
680 u8 shift = nv_ro08(bios, init->offset + 5);
681 s8 iofc = nv_ro08(bios, init->offset + 6);
682 u8 count = nv_ro08(bios, init->offset + 7);
683 u32 reg = nv_ro32(bios, init->offset + 8);
686 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
687 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
688 reg, port, index, mask, shift, iofc);
691 conf = (init_rdvgai(init, port, index) & mask) >> shift;
692 for (i = 0; i < count; i++) {
693 u32 freq = nv_ro16(bios, init->offset) * 10;
696 trace("\t%dkHz *\n", freq);
697 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
699 init_prog_pll(init, reg, freq);
701 trace("\t%dkHz\n", freq);
710 * INIT_END_REPEAT - opcode 0x36
714 init_end_repeat(struct nvbios_init *init)
716 trace("END_REPEAT\n");
720 init->repend = init->offset;
726 * INIT_COPY - opcode 0x37
730 init_copy(struct nvbios_init *init)
732 struct nvkm_bios *bios = init->bios;
733 u32 reg = nv_ro32(bios, init->offset + 1);
734 u8 shift = nv_ro08(bios, init->offset + 5);
735 u8 smask = nv_ro08(bios, init->offset + 6);
736 u16 port = nv_ro16(bios, init->offset + 7);
737 u8 index = nv_ro08(bios, init->offset + 9);
738 u8 mask = nv_ro08(bios, init->offset + 10);
741 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
742 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
743 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
744 (shift & 0x80) ? (0x100 - shift) : shift, smask);
747 data = init_rdvgai(init, port, index) & mask;
748 data |= init_shift(init_rd32(init, reg), shift) & smask;
749 init_wrvgai(init, port, index, data);
753 * INIT_NOT - opcode 0x38
757 init_not(struct nvbios_init *init)
765 * INIT_IO_FLAG_CONDITION - opcode 0x39
769 init_io_flag_condition(struct nvbios_init *init)
771 struct nvkm_bios *bios = init->bios;
772 u8 cond = nv_ro08(bios, init->offset + 1);
774 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
777 if (!init_io_flag_condition_met(init, cond))
778 init_exec_set(init, false);
782 * INIT_DP_CONDITION - opcode 0x3a
786 init_dp_condition(struct nvbios_init *init)
788 struct nvkm_bios *bios = init->bios;
789 struct nvbios_dpout info;
790 u8 cond = nv_ro08(bios, init->offset + 1);
791 u8 unkn = nv_ro08(bios, init->offset + 2);
792 u8 ver, hdr, cnt, len;
795 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
800 if (init_conn(init) != DCB_CONNECTOR_eDP)
801 init_exec_set(init, false);
806 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
807 (init->outp->or << 0) |
808 (init->outp->sorconf.link << 6),
809 &ver, &hdr, &cnt, &len, &info)))
811 if (!(info.flags & cond))
812 init_exec_set(init, false);
817 warn("script needs dp output table data\n");
820 if (!(init_rdauxr(init, 0x0d) & 1))
821 init_exec_set(init, false);
824 warn("unknown dp condition 0x%02x\n", cond);
830 * INIT_IO_MASK_OR - opcode 0x3b
834 init_io_mask_or(struct nvbios_init *init)
836 struct nvkm_bios *bios = init->bios;
837 u8 index = nv_ro08(bios, init->offset + 1);
838 u8 or = init_or(init);
841 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
844 data = init_rdvgai(init, 0x03d4, index);
845 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
849 * INIT_IO_OR - opcode 0x3c
853 init_io_or(struct nvbios_init *init)
855 struct nvkm_bios *bios = init->bios;
856 u8 index = nv_ro08(bios, init->offset + 1);
857 u8 or = init_or(init);
860 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
863 data = init_rdvgai(init, 0x03d4, index);
864 init_wrvgai(init, 0x03d4, index, data | (1 << or));
868 * INIT_ANDN_REG - opcode 0x47
872 init_andn_reg(struct nvbios_init *init)
874 struct nvkm_bios *bios = init->bios;
875 u32 reg = nv_ro32(bios, init->offset + 1);
876 u32 mask = nv_ro32(bios, init->offset + 5);
878 trace("ANDN_REG\tR[0x%06x] &= ~0x%08x\n", reg, mask);
881 init_mask(init, reg, mask, 0);
885 * INIT_OR_REG - opcode 0x48
889 init_or_reg(struct nvbios_init *init)
891 struct nvkm_bios *bios = init->bios;
892 u32 reg = nv_ro32(bios, init->offset + 1);
893 u32 mask = nv_ro32(bios, init->offset + 5);
895 trace("OR_REG\tR[0x%06x] |= 0x%08x\n", reg, mask);
898 init_mask(init, reg, 0, mask);
902 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
906 init_idx_addr_latched(struct nvbios_init *init)
908 struct nvkm_bios *bios = init->bios;
909 u32 creg = nv_ro32(bios, init->offset + 1);
910 u32 dreg = nv_ro32(bios, init->offset + 5);
911 u32 mask = nv_ro32(bios, init->offset + 9);
912 u32 data = nv_ro32(bios, init->offset + 13);
913 u8 count = nv_ro08(bios, init->offset + 17);
915 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
916 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
920 u8 iaddr = nv_ro08(bios, init->offset + 0);
921 u8 idata = nv_ro08(bios, init->offset + 1);
923 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
926 init_wr32(init, dreg, idata);
927 init_mask(init, creg, ~mask, data | iaddr);
932 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
936 init_io_restrict_pll2(struct nvbios_init *init)
938 struct nvkm_bios *bios = init->bios;
939 u16 port = nv_ro16(bios, init->offset + 1);
940 u8 index = nv_ro08(bios, init->offset + 3);
941 u8 mask = nv_ro08(bios, init->offset + 4);
942 u8 shift = nv_ro08(bios, init->offset + 5);
943 u8 count = nv_ro08(bios, init->offset + 6);
944 u32 reg = nv_ro32(bios, init->offset + 7);
947 trace("IO_RESTRICT_PLL2\t"
948 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
949 reg, port, index, mask, shift);
952 conf = (init_rdvgai(init, port, index) & mask) >> shift;
953 for (i = 0; i < count; i++) {
954 u32 freq = nv_ro32(bios, init->offset);
956 trace("\t%dkHz *\n", freq);
957 init_prog_pll(init, reg, freq);
959 trace("\t%dkHz\n", freq);
967 * INIT_PLL2 - opcode 0x4b
971 init_pll2(struct nvbios_init *init)
973 struct nvkm_bios *bios = init->bios;
974 u32 reg = nv_ro32(bios, init->offset + 1);
975 u32 freq = nv_ro32(bios, init->offset + 5);
977 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
980 init_prog_pll(init, reg, freq);
984 * INIT_I2C_BYTE - opcode 0x4c
988 init_i2c_byte(struct nvbios_init *init)
990 struct nvkm_bios *bios = init->bios;
991 u8 index = nv_ro08(bios, init->offset + 1);
992 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
993 u8 count = nv_ro08(bios, init->offset + 3);
995 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
999 u8 reg = nv_ro08(bios, init->offset + 0);
1000 u8 mask = nv_ro08(bios, init->offset + 1);
1001 u8 data = nv_ro08(bios, init->offset + 2);
1004 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
1007 val = init_rdi2cr(init, index, addr, reg);
1010 init_wri2cr(init, index, addr, reg, (val & mask) | data);
1015 * INIT_ZM_I2C_BYTE - opcode 0x4d
1019 init_zm_i2c_byte(struct nvbios_init *init)
1021 struct nvkm_bios *bios = init->bios;
1022 u8 index = nv_ro08(bios, init->offset + 1);
1023 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1024 u8 count = nv_ro08(bios, init->offset + 3);
1026 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
1030 u8 reg = nv_ro08(bios, init->offset + 0);
1031 u8 data = nv_ro08(bios, init->offset + 1);
1033 trace("\t[0x%02x] = 0x%02x\n", reg, data);
1036 init_wri2cr(init, index, addr, reg, data);
1041 * INIT_ZM_I2C - opcode 0x4e
1045 init_zm_i2c(struct nvbios_init *init)
1047 struct nvkm_bios *bios = init->bios;
1048 u8 index = nv_ro08(bios, init->offset + 1);
1049 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1050 u8 count = nv_ro08(bios, init->offset + 3);
1053 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1056 for (i = 0; i < count; i++) {
1057 data[i] = nv_ro08(bios, init->offset);
1058 trace("\t0x%02x\n", data[i]);
1062 if (init_exec(init)) {
1063 struct nvkm_i2c_port *port = init_i2c(init, index);
1064 struct i2c_msg msg = {
1065 .addr = addr, .flags = 0, .len = count, .buf = data,
1069 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1070 warn("i2c wr failed, %d\n", ret);
1075 * INIT_TMDS - opcode 0x4f
1079 init_tmds(struct nvbios_init *init)
1081 struct nvkm_bios *bios = init->bios;
1082 u8 tmds = nv_ro08(bios, init->offset + 1);
1083 u8 addr = nv_ro08(bios, init->offset + 2);
1084 u8 mask = nv_ro08(bios, init->offset + 3);
1085 u8 data = nv_ro08(bios, init->offset + 4);
1086 u32 reg = init_tmds_reg(init, tmds);
1088 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1089 tmds, addr, mask, data);
1095 init_wr32(init, reg + 0, addr | 0x00010000);
1096 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1097 init_wr32(init, reg + 0, addr);
1101 * INIT_ZM_TMDS_GROUP - opcode 0x50
1105 init_zm_tmds_group(struct nvbios_init *init)
1107 struct nvkm_bios *bios = init->bios;
1108 u8 tmds = nv_ro08(bios, init->offset + 1);
1109 u8 count = nv_ro08(bios, init->offset + 2);
1110 u32 reg = init_tmds_reg(init, tmds);
1112 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1116 u8 addr = nv_ro08(bios, init->offset + 0);
1117 u8 data = nv_ro08(bios, init->offset + 1);
1119 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1122 init_wr32(init, reg + 4, data);
1123 init_wr32(init, reg + 0, addr);
1128 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1132 init_cr_idx_adr_latch(struct nvbios_init *init)
1134 struct nvkm_bios *bios = init->bios;
1135 u8 addr0 = nv_ro08(bios, init->offset + 1);
1136 u8 addr1 = nv_ro08(bios, init->offset + 2);
1137 u8 base = nv_ro08(bios, init->offset + 3);
1138 u8 count = nv_ro08(bios, init->offset + 4);
1141 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1144 save0 = init_rdvgai(init, 0x03d4, addr0);
1146 u8 data = nv_ro08(bios, init->offset);
1148 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1151 init_wrvgai(init, 0x03d4, addr0, base++);
1152 init_wrvgai(init, 0x03d4, addr1, data);
1154 init_wrvgai(init, 0x03d4, addr0, save0);
1158 * INIT_CR - opcode 0x52
1162 init_cr(struct nvbios_init *init)
1164 struct nvkm_bios *bios = init->bios;
1165 u8 addr = nv_ro08(bios, init->offset + 1);
1166 u8 mask = nv_ro08(bios, init->offset + 2);
1167 u8 data = nv_ro08(bios, init->offset + 3);
1170 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1173 val = init_rdvgai(init, 0x03d4, addr) & mask;
1174 init_wrvgai(init, 0x03d4, addr, val | data);
1178 * INIT_ZM_CR - opcode 0x53
1182 init_zm_cr(struct nvbios_init *init)
1184 struct nvkm_bios *bios = init->bios;
1185 u8 addr = nv_ro08(bios, init->offset + 1);
1186 u8 data = nv_ro08(bios, init->offset + 2);
1188 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1191 init_wrvgai(init, 0x03d4, addr, data);
1195 * INIT_ZM_CR_GROUP - opcode 0x54
1199 init_zm_cr_group(struct nvbios_init *init)
1201 struct nvkm_bios *bios = init->bios;
1202 u8 count = nv_ro08(bios, init->offset + 1);
1204 trace("ZM_CR_GROUP\n");
1208 u8 addr = nv_ro08(bios, init->offset + 0);
1209 u8 data = nv_ro08(bios, init->offset + 1);
1211 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1214 init_wrvgai(init, 0x03d4, addr, data);
1219 * INIT_CONDITION_TIME - opcode 0x56
1223 init_condition_time(struct nvbios_init *init)
1225 struct nvkm_bios *bios = init->bios;
1226 u8 cond = nv_ro08(bios, init->offset + 1);
1227 u8 retry = nv_ro08(bios, init->offset + 2);
1228 u8 wait = min((u16)retry * 50, 100);
1230 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1233 if (!init_exec(init))
1237 if (init_condition_met(init, cond))
1242 init_exec_set(init, false);
1246 * INIT_LTIME - opcode 0x57
1250 init_ltime(struct nvbios_init *init)
1252 struct nvkm_bios *bios = init->bios;
1253 u16 msec = nv_ro16(bios, init->offset + 1);
1255 trace("LTIME\t0x%04x\n", msec);
1258 if (init_exec(init))
1263 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1267 init_zm_reg_sequence(struct nvbios_init *init)
1269 struct nvkm_bios *bios = init->bios;
1270 u32 base = nv_ro32(bios, init->offset + 1);
1271 u8 count = nv_ro08(bios, init->offset + 5);
1273 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1277 u32 data = nv_ro32(bios, init->offset);
1279 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1282 init_wr32(init, base, data);
1288 * INIT_PLL_INDIRECT - opcode 0x59
1292 init_pll_indirect(struct nvbios_init *init)
1294 struct nvkm_bios *bios = init->bios;
1295 u32 reg = nv_ro32(bios, init->offset + 1);
1296 u16 addr = nv_ro16(bios, init->offset + 5);
1297 u32 freq = (u32)nv_ro16(bios, addr) * 1000;
1299 trace("PLL_INDIRECT\tR[0x%06x] =PLL= VBIOS[%04x] = %dkHz\n",
1303 init_prog_pll(init, reg, freq);
1307 * INIT_ZM_REG_INDIRECT - opcode 0x5a
1311 init_zm_reg_indirect(struct nvbios_init *init)
1313 struct nvkm_bios *bios = init->bios;
1314 u32 reg = nv_ro32(bios, init->offset + 1);
1315 u16 addr = nv_ro16(bios, init->offset + 5);
1316 u32 data = nv_ro32(bios, addr);
1318 trace("ZM_REG_INDIRECT\tR[0x%06x] = VBIOS[0x%04x] = 0x%08x\n",
1322 init_wr32(init, addr, data);
1326 * INIT_SUB_DIRECT - opcode 0x5b
1330 init_sub_direct(struct nvbios_init *init)
1332 struct nvkm_bios *bios = init->bios;
1333 u16 addr = nv_ro16(bios, init->offset + 1);
1336 trace("SUB_DIRECT\t0x%04x\n", addr);
1338 if (init_exec(init)) {
1339 save = init->offset;
1340 init->offset = addr;
1341 if (nvbios_exec(init)) {
1342 error("error parsing sub-table\n");
1345 init->offset = save;
1352 * INIT_JUMP - opcode 0x5c
1356 init_jump(struct nvbios_init *init)
1358 struct nvkm_bios *bios = init->bios;
1359 u16 offset = nv_ro16(bios, init->offset + 1);
1361 trace("JUMP\t0x%04x\n", offset);
1363 if (init_exec(init))
1364 init->offset = offset;
1370 * INIT_I2C_IF - opcode 0x5e
1374 init_i2c_if(struct nvbios_init *init)
1376 struct nvkm_bios *bios = init->bios;
1377 u8 index = nv_ro08(bios, init->offset + 1);
1378 u8 addr = nv_ro08(bios, init->offset + 2);
1379 u8 reg = nv_ro08(bios, init->offset + 3);
1380 u8 mask = nv_ro08(bios, init->offset + 4);
1381 u8 data = nv_ro08(bios, init->offset + 5);
1384 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1385 index, addr, reg, mask, data);
1387 init_exec_force(init, true);
1389 value = init_rdi2cr(init, index, addr, reg);
1390 if ((value & mask) != data)
1391 init_exec_set(init, false);
1393 init_exec_force(init, false);
1397 * INIT_COPY_NV_REG - opcode 0x5f
1401 init_copy_nv_reg(struct nvbios_init *init)
1403 struct nvkm_bios *bios = init->bios;
1404 u32 sreg = nv_ro32(bios, init->offset + 1);
1405 u8 shift = nv_ro08(bios, init->offset + 5);
1406 u32 smask = nv_ro32(bios, init->offset + 6);
1407 u32 sxor = nv_ro32(bios, init->offset + 10);
1408 u32 dreg = nv_ro32(bios, init->offset + 14);
1409 u32 dmask = nv_ro32(bios, init->offset + 18);
1412 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1413 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1414 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1415 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1418 data = init_shift(init_rd32(init, sreg), shift);
1419 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1423 * INIT_ZM_INDEX_IO - opcode 0x62
1427 init_zm_index_io(struct nvbios_init *init)
1429 struct nvkm_bios *bios = init->bios;
1430 u16 port = nv_ro16(bios, init->offset + 1);
1431 u8 index = nv_ro08(bios, init->offset + 3);
1432 u8 data = nv_ro08(bios, init->offset + 4);
1434 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1437 init_wrvgai(init, port, index, data);
1441 * INIT_COMPUTE_MEM - opcode 0x63
1445 init_compute_mem(struct nvbios_init *init)
1447 struct nvkm_devinit *devinit = nvkm_devinit(init->bios);
1449 trace("COMPUTE_MEM\n");
1452 init_exec_force(init, true);
1453 if (init_exec(init) && devinit->meminit)
1454 devinit->meminit(devinit);
1455 init_exec_force(init, false);
1459 * INIT_RESET - opcode 0x65
1463 init_reset(struct nvbios_init *init)
1465 struct nvkm_bios *bios = init->bios;
1466 u32 reg = nv_ro32(bios, init->offset + 1);
1467 u32 data1 = nv_ro32(bios, init->offset + 5);
1468 u32 data2 = nv_ro32(bios, init->offset + 9);
1471 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1473 init_exec_force(init, true);
1475 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1476 init_wr32(init, reg, data1);
1478 init_wr32(init, reg, data2);
1479 init_wr32(init, 0x00184c, savepci19);
1480 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1482 init_exec_force(init, false);
1486 * INIT_CONFIGURE_MEM - opcode 0x66
1490 init_configure_mem_clk(struct nvbios_init *init)
1492 u16 mdata = bmp_mem_init_table(init->bios);
1494 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1499 init_configure_mem(struct nvbios_init *init)
1501 struct nvkm_bios *bios = init->bios;
1505 trace("CONFIGURE_MEM\n");
1508 if (bios->version.major > 2) {
1512 init_exec_force(init, true);
1514 mdata = init_configure_mem_clk(init);
1515 sdata = bmp_sdr_seq_table(bios);
1516 if (nv_ro08(bios, mdata) & 0x01)
1517 sdata = bmp_ddr_seq_table(bios);
1518 mdata += 6; /* skip to data */
1520 data = init_rdvgai(init, 0x03c4, 0x01);
1521 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1523 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
1525 case 0x10021c: /* CKE_NORMAL */
1526 case 0x1002d0: /* CMD_REFRESH */
1527 case 0x1002d4: /* CMD_PRECHARGE */
1531 data = nv_ro32(bios, mdata);
1533 if (data == 0xffffffff)
1538 init_wr32(init, addr, data);
1541 init_exec_force(init, false);
1545 * INIT_CONFIGURE_CLK - opcode 0x67
1549 init_configure_clk(struct nvbios_init *init)
1551 struct nvkm_bios *bios = init->bios;
1554 trace("CONFIGURE_CLK\n");
1557 if (bios->version.major > 2) {
1561 init_exec_force(init, true);
1563 mdata = init_configure_mem_clk(init);
1566 clock = nv_ro16(bios, mdata + 4) * 10;
1567 init_prog_pll(init, 0x680500, clock);
1570 clock = nv_ro16(bios, mdata + 2) * 10;
1571 if (nv_ro08(bios, mdata) & 0x01)
1573 init_prog_pll(init, 0x680504, clock);
1575 init_exec_force(init, false);
1579 * INIT_CONFIGURE_PREINIT - opcode 0x68
1583 init_configure_preinit(struct nvbios_init *init)
1585 struct nvkm_bios *bios = init->bios;
1588 trace("CONFIGURE_PREINIT\n");
1591 if (bios->version.major > 2) {
1595 init_exec_force(init, true);
1597 strap = init_rd32(init, 0x101000);
1598 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1599 init_wrvgai(init, 0x03d4, 0x3c, strap);
1601 init_exec_force(init, false);
1605 * INIT_IO - opcode 0x69
1609 init_io(struct nvbios_init *init)
1611 struct nvkm_bios *bios = init->bios;
1612 u16 port = nv_ro16(bios, init->offset + 1);
1613 u8 mask = nv_ro16(bios, init->offset + 3);
1614 u8 data = nv_ro16(bios, init->offset + 4);
1617 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1620 /* ummm.. yes.. should really figure out wtf this is and why it's
1621 * needed some day.. it's almost certainly wrong, but, it also
1622 * somehow makes things work...
1624 if (nv_device(init->bios)->card_type >= NV_50 &&
1625 port == 0x03c3 && data == 0x01) {
1626 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1627 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1628 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1629 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1631 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1632 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1633 init_wr32(init, 0x614100, 0x00800018);
1634 init_wr32(init, 0x614900, 0x00800018);
1636 init_wr32(init, 0x614100, 0x10000018);
1637 init_wr32(init, 0x614900, 0x10000018);
1640 value = init_rdport(init, port) & mask;
1641 init_wrport(init, port, data | value);
1645 * INIT_SUB - opcode 0x6b
1649 init_sub(struct nvbios_init *init)
1651 struct nvkm_bios *bios = init->bios;
1652 u8 index = nv_ro08(bios, init->offset + 1);
1655 trace("SUB\t0x%02x\n", index);
1657 addr = init_script(bios, index);
1658 if (addr && init_exec(init)) {
1659 save = init->offset;
1660 init->offset = addr;
1661 if (nvbios_exec(init)) {
1662 error("error parsing sub-table\n");
1665 init->offset = save;
1672 * INIT_RAM_CONDITION - opcode 0x6d
1676 init_ram_condition(struct nvbios_init *init)
1678 struct nvkm_bios *bios = init->bios;
1679 u8 mask = nv_ro08(bios, init->offset + 1);
1680 u8 value = nv_ro08(bios, init->offset + 2);
1682 trace("RAM_CONDITION\t"
1683 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1686 if ((init_rd32(init, 0x100000) & mask) != value)
1687 init_exec_set(init, false);
1691 * INIT_NV_REG - opcode 0x6e
1695 init_nv_reg(struct nvbios_init *init)
1697 struct nvkm_bios *bios = init->bios;
1698 u32 reg = nv_ro32(bios, init->offset + 1);
1699 u32 mask = nv_ro32(bios, init->offset + 5);
1700 u32 data = nv_ro32(bios, init->offset + 9);
1702 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1705 init_mask(init, reg, ~mask, data);
1709 * INIT_MACRO - opcode 0x6f
1713 init_macro(struct nvbios_init *init)
1715 struct nvkm_bios *bios = init->bios;
1716 u8 macro = nv_ro08(bios, init->offset + 1);
1719 trace("MACRO\t0x%02x\n", macro);
1721 table = init_macro_table(init);
1723 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1724 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1725 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1726 init_wr32(init, addr, data);
1733 * INIT_RESUME - opcode 0x72
1737 init_resume(struct nvbios_init *init)
1741 init_exec_set(init, true);
1745 * INIT_TIME - opcode 0x74
1749 init_time(struct nvbios_init *init)
1751 struct nvkm_bios *bios = init->bios;
1752 u16 usec = nv_ro16(bios, init->offset + 1);
1754 trace("TIME\t0x%04x\n", usec);
1757 if (init_exec(init)) {
1761 mdelay((usec + 900) / 1000);
1766 * INIT_CONDITION - opcode 0x75
1770 init_condition(struct nvbios_init *init)
1772 struct nvkm_bios *bios = init->bios;
1773 u8 cond = nv_ro08(bios, init->offset + 1);
1775 trace("CONDITION\t0x%02x\n", cond);
1778 if (!init_condition_met(init, cond))
1779 init_exec_set(init, false);
1783 * INIT_IO_CONDITION - opcode 0x76
1787 init_io_condition(struct nvbios_init *init)
1789 struct nvkm_bios *bios = init->bios;
1790 u8 cond = nv_ro08(bios, init->offset + 1);
1792 trace("IO_CONDITION\t0x%02x\n", cond);
1795 if (!init_io_condition_met(init, cond))
1796 init_exec_set(init, false);
1800 * INIT_INDEX_IO - opcode 0x78
1804 init_index_io(struct nvbios_init *init)
1806 struct nvkm_bios *bios = init->bios;
1807 u16 port = nv_ro16(bios, init->offset + 1);
1808 u8 index = nv_ro16(bios, init->offset + 3);
1809 u8 mask = nv_ro08(bios, init->offset + 4);
1810 u8 data = nv_ro08(bios, init->offset + 5);
1813 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1814 port, index, mask, data);
1817 value = init_rdvgai(init, port, index) & mask;
1818 init_wrvgai(init, port, index, data | value);
1822 * INIT_PLL - opcode 0x79
1826 init_pll(struct nvbios_init *init)
1828 struct nvkm_bios *bios = init->bios;
1829 u32 reg = nv_ro32(bios, init->offset + 1);
1830 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1832 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1835 init_prog_pll(init, reg, freq);
1839 * INIT_ZM_REG - opcode 0x7a
1843 init_zm_reg(struct nvbios_init *init)
1845 struct nvkm_bios *bios = init->bios;
1846 u32 addr = nv_ro32(bios, init->offset + 1);
1847 u32 data = nv_ro32(bios, init->offset + 5);
1849 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1852 if (addr == 0x000200)
1855 init_wr32(init, addr, data);
1859 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1863 init_ram_restrict_pll(struct nvbios_init *init)
1865 struct nvkm_bios *bios = init->bios;
1866 u8 type = nv_ro08(bios, init->offset + 1);
1867 u8 count = init_ram_restrict_group_count(init);
1868 u8 strap = init_ram_restrict(init);
1871 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1874 for (cconf = 0; cconf < count; cconf++) {
1875 u32 freq = nv_ro32(bios, init->offset);
1877 if (cconf == strap) {
1878 trace("%dkHz *\n", freq);
1879 init_prog_pll(init, type, freq);
1881 trace("%dkHz\n", freq);
1889 * INIT_GPIO - opcode 0x8e
1893 init_gpio(struct nvbios_init *init)
1895 struct nvkm_gpio *gpio = nvkm_gpio(init->bios);
1900 if (init_exec(init) && gpio && gpio->reset)
1901 gpio->reset(gpio, DCB_GPIO_UNUSED);
1905 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1909 init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1911 struct nvkm_bios *bios = init->bios;
1912 u32 addr = nv_ro32(bios, init->offset + 1);
1913 u8 incr = nv_ro08(bios, init->offset + 5);
1914 u8 num = nv_ro08(bios, init->offset + 6);
1915 u8 count = init_ram_restrict_group_count(init);
1916 u8 index = init_ram_restrict(init);
1919 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1920 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
1923 for (i = 0; i < num; i++) {
1924 trace("\tR[0x%06x] = {\n", addr);
1925 for (j = 0; j < count; j++) {
1926 u32 data = nv_ro32(bios, init->offset);
1929 trace("\t\t0x%08x *\n", data);
1930 init_wr32(init, addr, data);
1932 trace("\t\t0x%08x\n", data);
1943 * INIT_COPY_ZM_REG - opcode 0x90
1947 init_copy_zm_reg(struct nvbios_init *init)
1949 struct nvkm_bios *bios = init->bios;
1950 u32 sreg = nv_ro32(bios, init->offset + 1);
1951 u32 dreg = nv_ro32(bios, init->offset + 5);
1953 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
1956 init_wr32(init, dreg, init_rd32(init, sreg));
1960 * INIT_ZM_REG_GROUP - opcode 0x91
1964 init_zm_reg_group(struct nvbios_init *init)
1966 struct nvkm_bios *bios = init->bios;
1967 u32 addr = nv_ro32(bios, init->offset + 1);
1968 u8 count = nv_ro08(bios, init->offset + 5);
1970 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
1974 u32 data = nv_ro32(bios, init->offset);
1975 trace("\t0x%08x\n", data);
1976 init_wr32(init, addr, data);
1982 * INIT_XLAT - opcode 0x96
1986 init_xlat(struct nvbios_init *init)
1988 struct nvkm_bios *bios = init->bios;
1989 u32 saddr = nv_ro32(bios, init->offset + 1);
1990 u8 sshift = nv_ro08(bios, init->offset + 5);
1991 u8 smask = nv_ro08(bios, init->offset + 6);
1992 u8 index = nv_ro08(bios, init->offset + 7);
1993 u32 daddr = nv_ro32(bios, init->offset + 8);
1994 u32 dmask = nv_ro32(bios, init->offset + 12);
1995 u8 shift = nv_ro08(bios, init->offset + 16);
1998 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1999 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
2000 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
2001 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
2004 data = init_shift(init_rd32(init, saddr), sshift) & smask;
2005 data = init_xlat_(init, index, data) << shift;
2006 init_mask(init, daddr, ~dmask, data);
2010 * INIT_ZM_MASK_ADD - opcode 0x97
2014 init_zm_mask_add(struct nvbios_init *init)
2016 struct nvkm_bios *bios = init->bios;
2017 u32 addr = nv_ro32(bios, init->offset + 1);
2018 u32 mask = nv_ro32(bios, init->offset + 5);
2019 u32 add = nv_ro32(bios, init->offset + 9);
2022 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
2025 data = init_rd32(init, addr);
2026 data = (data & mask) | ((data + add) & ~mask);
2027 init_wr32(init, addr, data);
2031 * INIT_AUXCH - opcode 0x98
2035 init_auxch(struct nvbios_init *init)
2037 struct nvkm_bios *bios = init->bios;
2038 u32 addr = nv_ro32(bios, init->offset + 1);
2039 u8 count = nv_ro08(bios, init->offset + 5);
2041 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2045 u8 mask = nv_ro08(bios, init->offset + 0);
2046 u8 data = nv_ro08(bios, init->offset + 1);
2047 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
2048 mask = init_rdauxr(init, addr) & mask;
2049 init_wrauxr(init, addr, mask | data);
2055 * INIT_AUXCH - opcode 0x99
2059 init_zm_auxch(struct nvbios_init *init)
2061 struct nvkm_bios *bios = init->bios;
2062 u32 addr = nv_ro32(bios, init->offset + 1);
2063 u8 count = nv_ro08(bios, init->offset + 5);
2065 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
2069 u8 data = nv_ro08(bios, init->offset + 0);
2070 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
2071 init_wrauxr(init, addr, data);
2077 * INIT_I2C_LONG_IF - opcode 0x9a
2081 init_i2c_long_if(struct nvbios_init *init)
2083 struct nvkm_bios *bios = init->bios;
2084 u8 index = nv_ro08(bios, init->offset + 1);
2085 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2086 u8 reglo = nv_ro08(bios, init->offset + 3);
2087 u8 reghi = nv_ro08(bios, init->offset + 4);
2088 u8 mask = nv_ro08(bios, init->offset + 5);
2089 u8 data = nv_ro08(bios, init->offset + 6);
2090 struct nvkm_i2c_port *port;
2092 trace("I2C_LONG_IF\t"
2093 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2094 index, addr, reglo, reghi, mask, data);
2097 port = init_i2c(init, index);
2099 u8 i[2] = { reghi, reglo };
2101 struct i2c_msg msg[] = {
2102 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2103 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2107 ret = i2c_transfer(&port->adapter, msg, 2);
2108 if (ret == 2 && ((o[0] & mask) == data))
2112 init_exec_set(init, false);
2116 * INIT_GPIO_NE - opcode 0xa9
2120 init_gpio_ne(struct nvbios_init *init)
2122 struct nvkm_bios *bios = init->bios;
2123 struct nvkm_gpio *gpio = nvkm_gpio(bios);
2124 struct dcb_gpio_func func;
2125 u8 count = nv_ro08(bios, init->offset + 1);
2126 u8 idx = 0, ver, len;
2132 for (i = init->offset; i < init->offset + count; i++)
2133 cont("0x%02x ", nv_ro08(bios, i));
2136 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2137 if (func.func != DCB_GPIO_UNUSED) {
2138 for (i = init->offset; i < init->offset + count; i++) {
2139 if (func.func == nv_ro08(bios, i))
2143 trace("\tFUNC[0x%02x]", func.func);
2144 if (i == (init->offset + count)) {
2146 if (init_exec(init) && gpio && gpio->reset)
2147 gpio->reset(gpio, func.func);
2153 init->offset += count;
2156 static struct nvbios_init_opcode {
2157 void (*exec)(struct nvbios_init *);
2159 [0x32] = { init_io_restrict_prog },
2160 [0x33] = { init_repeat },
2161 [0x34] = { init_io_restrict_pll },
2162 [0x36] = { init_end_repeat },
2163 [0x37] = { init_copy },
2164 [0x38] = { init_not },
2165 [0x39] = { init_io_flag_condition },
2166 [0x3a] = { init_dp_condition },
2167 [0x3b] = { init_io_mask_or },
2168 [0x3c] = { init_io_or },
2169 [0x47] = { init_andn_reg },
2170 [0x48] = { init_or_reg },
2171 [0x49] = { init_idx_addr_latched },
2172 [0x4a] = { init_io_restrict_pll2 },
2173 [0x4b] = { init_pll2 },
2174 [0x4c] = { init_i2c_byte },
2175 [0x4d] = { init_zm_i2c_byte },
2176 [0x4e] = { init_zm_i2c },
2177 [0x4f] = { init_tmds },
2178 [0x50] = { init_zm_tmds_group },
2179 [0x51] = { init_cr_idx_adr_latch },
2180 [0x52] = { init_cr },
2181 [0x53] = { init_zm_cr },
2182 [0x54] = { init_zm_cr_group },
2183 [0x56] = { init_condition_time },
2184 [0x57] = { init_ltime },
2185 [0x58] = { init_zm_reg_sequence },
2186 [0x59] = { init_pll_indirect },
2187 [0x5a] = { init_zm_reg_indirect },
2188 [0x5b] = { init_sub_direct },
2189 [0x5c] = { init_jump },
2190 [0x5e] = { init_i2c_if },
2191 [0x5f] = { init_copy_nv_reg },
2192 [0x62] = { init_zm_index_io },
2193 [0x63] = { init_compute_mem },
2194 [0x65] = { init_reset },
2195 [0x66] = { init_configure_mem },
2196 [0x67] = { init_configure_clk },
2197 [0x68] = { init_configure_preinit },
2198 [0x69] = { init_io },
2199 [0x6b] = { init_sub },
2200 [0x6d] = { init_ram_condition },
2201 [0x6e] = { init_nv_reg },
2202 [0x6f] = { init_macro },
2203 [0x71] = { init_done },
2204 [0x72] = { init_resume },
2205 [0x74] = { init_time },
2206 [0x75] = { init_condition },
2207 [0x76] = { init_io_condition },
2208 [0x78] = { init_index_io },
2209 [0x79] = { init_pll },
2210 [0x7a] = { init_zm_reg },
2211 [0x87] = { init_ram_restrict_pll },
2212 [0x8c] = { init_reserved },
2213 [0x8d] = { init_reserved },
2214 [0x8e] = { init_gpio },
2215 [0x8f] = { init_ram_restrict_zm_reg_group },
2216 [0x90] = { init_copy_zm_reg },
2217 [0x91] = { init_zm_reg_group },
2218 [0x92] = { init_reserved },
2219 [0x96] = { init_xlat },
2220 [0x97] = { init_zm_mask_add },
2221 [0x98] = { init_auxch },
2222 [0x99] = { init_zm_auxch },
2223 [0x9a] = { init_i2c_long_if },
2224 [0xa9] = { init_gpio_ne },
2225 [0xaa] = { init_reserved },
2228 #define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2231 nvbios_exec(struct nvbios_init *init)
2234 while (init->offset) {
2235 u8 opcode = nv_ro08(init->bios, init->offset);
2236 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2237 error("unknown opcode 0x%02x\n", opcode);
2241 init_opcode[opcode].exec(init);
2248 nvbios_init(struct nvkm_subdev *subdev, bool execute)
2250 struct nvkm_bios *bios = nvkm_bios(subdev);
2256 nv_info(bios, "running init tables\n");
2257 while (!ret && (data = (init_script(bios, ++i)))) {
2258 struct nvbios_init init = {
2264 .execute = execute ? 1 : 0,
2267 ret = nvbios_exec(&init);
2270 /* the vbios parser will run this right after the normal init
2271 * tables, whereas the binary driver appears to run it later.
2273 if (!ret && (data = init_unknown_script(bios))) {
2274 struct nvbios_init init = {
2280 .execute = execute ? 1 : 0,
2283 ret = nvbios_exec(&init);