2 * Copyright 2013 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
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15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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24 #include <subdev/bios.h>
25 #include <subdev/bios/bit.h>
26 #include <subdev/bios/timing.h>
29 nvbios_timingTe(struct nvkm_bios *bios,
30 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
32 struct bit_entry bit_P;
35 if (!bit_entry(bios, 'P', &bit_P)) {
36 if (bit_P.version == 1)
37 timing = nv_ro16(bios, bit_P.offset + 4);
39 if (bit_P.version == 2)
40 timing = nv_ro16(bios, bit_P.offset + 8);
43 *ver = nv_ro08(bios, timing + 0);
46 *hdr = nv_ro08(bios, timing + 1);
47 *cnt = nv_ro08(bios, timing + 2);
48 *len = nv_ro08(bios, timing + 3);
53 *hdr = nv_ro08(bios, timing + 1);
54 *cnt = nv_ro08(bios, timing + 5);
55 *len = nv_ro08(bios, timing + 2);
56 *snr = nv_ro08(bios, timing + 4);
57 *ssz = nv_ro08(bios, timing + 3);
69 nvbios_timingEe(struct nvkm_bios *bios, int idx,
70 u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
73 u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz);
74 if (timing && idx < *cnt) {
75 timing += *hdr + idx * (*len + (snr * ssz));
85 nvbios_timingEp(struct nvkm_bios *bios, int idx,
86 u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_ramcfg *p)
88 u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp;
91 switch (!!data * *ver) {
93 p->timing_10_WR = nv_ro08(bios, data + 0x00);
94 p->timing_10_WTR = nv_ro08(bios, data + 0x01);
95 p->timing_10_CL = nv_ro08(bios, data + 0x02);
96 p->timing_10_RC = nv_ro08(bios, data + 0x03);
97 p->timing_10_RFC = nv_ro08(bios, data + 0x05);
98 p->timing_10_RAS = nv_ro08(bios, data + 0x07);
99 p->timing_10_RP = nv_ro08(bios, data + 0x09);
100 p->timing_10_RCDRD = nv_ro08(bios, data + 0x0a);
101 p->timing_10_RCDWR = nv_ro08(bios, data + 0x0b);
102 p->timing_10_RRD = nv_ro08(bios, data + 0x0c);
103 p->timing_10_13 = nv_ro08(bios, data + 0x0d);
104 p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
106 p->timing_10_24 = 0xff;
109 p->timing_10_CWL = 0;
113 switch (min_t(u8, *hdr, 25)) {
115 p->timing_10_24 = nv_ro08(bios, data + 0x18);
119 p->timing_10_21 = nv_ro08(bios, data + 0x15);
121 p->timing_10_20 = nv_ro08(bios, data + 0x14);
123 p->timing_10_CWL = nv_ro08(bios, data + 0x13);
125 p->timing_10_18 = nv_ro08(bios, data + 0x12);
128 p->timing_10_16 = nv_ro08(bios, data + 0x10);
133 p->timing[0] = nv_ro32(bios, data + 0x00);
134 p->timing[1] = nv_ro32(bios, data + 0x04);
135 p->timing[2] = nv_ro32(bios, data + 0x08);
136 p->timing[3] = nv_ro32(bios, data + 0x0c);
137 p->timing[4] = nv_ro32(bios, data + 0x10);
138 p->timing[5] = nv_ro32(bios, data + 0x14);
139 p->timing[6] = nv_ro32(bios, data + 0x18);
140 p->timing[7] = nv_ro32(bios, data + 0x1c);
141 p->timing[8] = nv_ro32(bios, data + 0x20);
142 p->timing[9] = nv_ro32(bios, data + 0x24);
143 p->timing[10] = nv_ro32(bios, data + 0x28);
144 p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0;
145 p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4;
146 p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6;
147 p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0;
148 temp = nv_ro16(bios, data + 0x2c);
149 p->timing_20_2c_003f = (temp & 0x003f) >> 0;
150 p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6;
151 p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0;
152 p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3;
153 temp = nv_ro16(bios, data + 0x31);
154 p->timing_20_31_0007 = (temp & 0x0007) >> 0;
155 p->timing_20_31_0078 = (temp & 0x0078) >> 3;
156 p->timing_20_31_0780 = (temp & 0x0780) >> 7;
157 p->timing_20_31_0800 = (temp & 0x0800) >> 11;
158 p->timing_20_31_7000 = (temp & 0x7000) >> 12;
159 p->timing_20_31_8000 = (temp & 0x8000) >> 15;