2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <subdev/clk.h>
27 #include <core/device.h>
28 #include <subdev/bios.h>
29 #include <subdev/bios/pll.h>
30 #include <subdev/timer.h>
32 struct gf100_clk_info {
41 struct gf100_clk_priv {
43 struct gf100_clk_info eng[16];
46 static u32 read_div(struct gf100_clk_priv *, int, u32, u32);
49 read_vco(struct gf100_clk_priv *priv, u32 dsrc)
51 struct nvkm_clk *clk = &priv->base;
52 u32 ssrc = nv_rd32(priv, dsrc);
53 if (!(ssrc & 0x00000100))
54 return clk->read(clk, nv_clk_src_sppll0);
55 return clk->read(clk, nv_clk_src_sppll1);
59 read_pll(struct gf100_clk_priv *priv, u32 pll)
61 struct nvkm_clk *clk = &priv->base;
62 u32 ctrl = nv_rd32(priv, pll + 0x00);
63 u32 coef = nv_rd32(priv, pll + 0x04);
64 u32 P = (coef & 0x003f0000) >> 16;
65 u32 N = (coef & 0x0000ff00) >> 8;
66 u32 M = (coef & 0x000000ff) >> 0;
69 if (!(ctrl & 0x00000001))
75 sclk = nv_device(priv)->crystal;
79 sclk = clk->read(clk, nv_clk_src_mpllsrc);
82 sclk = clk->read(clk, nv_clk_src_mpllsrcref);
88 sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140);
94 return sclk * N / M / P;
98 read_div(struct gf100_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
100 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
101 u32 sctl = nv_rd32(priv, dctl + (doff * 4));
103 switch (ssrc & 0x00000003) {
105 if ((ssrc & 0x00030000) != 0x00030000)
106 return nv_device(priv)->crystal;
111 if (sctl & 0x80000000) {
112 u32 sclk = read_vco(priv, dsrc + (doff * 4));
113 u32 sdiv = (sctl & 0x0000003f) + 2;
114 return (sclk * 2) / sdiv;
117 return read_vco(priv, dsrc + (doff * 4));
124 read_clk(struct gf100_clk_priv *priv, int clk)
126 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
127 u32 ssel = nv_rd32(priv, 0x137100);
130 if (ssel & (1 << clk)) {
132 sclk = read_pll(priv, 0x137000 + (clk * 0x20));
134 sclk = read_pll(priv, 0x1370e0);
135 sdiv = ((sctl & 0x00003f00) >> 8) + 2;
137 sclk = read_div(priv, clk, 0x137160, 0x1371d0);
138 sdiv = ((sctl & 0x0000003f) >> 0) + 2;
141 if (sctl & 0x80000000)
142 return (sclk * 2) / sdiv;
148 gf100_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
150 struct nvkm_device *device = nv_device(clk);
151 struct gf100_clk_priv *priv = (void *)clk;
154 case nv_clk_src_crystal:
155 return device->crystal;
156 case nv_clk_src_href:
158 case nv_clk_src_sppll0:
159 return read_pll(priv, 0x00e800);
160 case nv_clk_src_sppll1:
161 return read_pll(priv, 0x00e820);
163 case nv_clk_src_mpllsrcref:
164 return read_div(priv, 0, 0x137320, 0x137330);
165 case nv_clk_src_mpllsrc:
166 return read_pll(priv, 0x132020);
167 case nv_clk_src_mpll:
168 return read_pll(priv, 0x132000);
169 case nv_clk_src_mdiv:
170 return read_div(priv, 0, 0x137300, 0x137310);
172 if (nv_rd32(priv, 0x1373f0) & 0x00000002)
173 return clk->read(clk, nv_clk_src_mpll);
174 return clk->read(clk, nv_clk_src_mdiv);
177 return read_clk(priv, 0x00);
179 return read_clk(priv, 0x01);
180 case nv_clk_src_hubk07:
181 return read_clk(priv, 0x02);
182 case nv_clk_src_hubk06:
183 return read_clk(priv, 0x07);
184 case nv_clk_src_hubk01:
185 return read_clk(priv, 0x08);
186 case nv_clk_src_copy:
187 return read_clk(priv, 0x09);
188 case nv_clk_src_daemon:
189 return read_clk(priv, 0x0c);
190 case nv_clk_src_vdec:
191 return read_clk(priv, 0x0e);
193 nv_error(clk, "invalid clock source %d\n", src);
199 calc_div(struct gf100_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
201 u32 div = min((ref * 2) / freq, (u32)65);
206 return (ref * 2) / div;
210 calc_src(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
214 /* use one of the fixed frequencies if possible */
231 /* otherwise, calculate the closest divider */
232 sclk = read_vco(priv, 0x137160 + (clk * 4));
234 sclk = calc_div(priv, clk, sclk, freq, ddiv);
239 calc_pll(struct gf100_clk_priv *priv, int clk, u32 freq, u32 *coef)
241 struct nvkm_bios *bios = nvkm_bios(priv);
242 struct nvbios_pll limits;
245 ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits);
249 limits.refclk = read_div(priv, clk, 0x137120, 0x137140);
253 ret = gt215_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P);
257 *coef = (P << 16) | (N << 8) | M;
262 calc_clk(struct gf100_clk_priv *priv,
263 struct nvkm_cstate *cstate, int clk, int dom)
265 struct gf100_clk_info *info = &priv->eng[clk];
266 u32 freq = cstate->domain[dom];
267 u32 src0, div0, div1D, div1P = 0;
270 /* invalid clock domain */
274 /* first possible path, using only dividers */
275 clk0 = calc_src(priv, clk, freq, &src0, &div0);
276 clk0 = calc_div(priv, clk, clk0, freq, &div1D);
278 /* see if we can get any closer using PLLs */
279 if (clk0 != freq && (0x00004387 & (1 << clk))) {
281 clk1 = calc_pll(priv, clk, freq, &info->coef);
283 clk1 = cstate->domain[nv_clk_src_hubk06];
284 clk1 = calc_div(priv, clk, clk1, freq, &div1P);
287 /* select the method which gets closest to target freq */
288 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) {
291 info->ddiv |= 0x80000000;
292 info->ddiv |= div0 << 8;
296 info->mdiv |= 0x80000000;
299 info->ssel = info->coef = 0;
303 info->mdiv |= 0x80000000;
304 info->mdiv |= div1P << 8;
306 info->ssel = (1 << clk);
314 gf100_clk_calc(struct nvkm_clk *clk, struct nvkm_cstate *cstate)
316 struct gf100_clk_priv *priv = (void *)clk;
319 if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
320 (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) ||
321 (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) ||
322 (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) ||
323 (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) ||
324 (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) ||
325 (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) ||
326 (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec)))
333 gf100_clk_prog_0(struct gf100_clk_priv *priv, int clk)
335 struct gf100_clk_info *info = &priv->eng[clk];
336 if (clk < 7 && !info->ssel) {
337 nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
338 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
343 gf100_clk_prog_1(struct gf100_clk_priv *priv, int clk)
345 nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
346 nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
350 gf100_clk_prog_2(struct gf100_clk_priv *priv, int clk)
352 struct gf100_clk_info *info = &priv->eng[clk];
353 const u32 addr = 0x137000 + (clk * 0x20);
355 nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
356 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
358 nv_wr32(priv, addr + 0x04, info->coef);
359 nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001);
360 nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000);
361 nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004);
367 gf100_clk_prog_3(struct gf100_clk_priv *priv, int clk)
369 struct gf100_clk_info *info = &priv->eng[clk];
371 nv_mask(priv, 0x137100, (1 << clk), info->ssel);
372 nv_wait(priv, 0x137100, (1 << clk), info->ssel);
377 gf100_clk_prog_4(struct gf100_clk_priv *priv, int clk)
379 struct gf100_clk_info *info = &priv->eng[clk];
380 nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
384 gf100_clk_prog(struct nvkm_clk *clk)
386 struct gf100_clk_priv *priv = (void *)clk;
388 void (*exec)(struct gf100_clk_priv *, int);
390 { gf100_clk_prog_0 }, /* div programming */
391 { gf100_clk_prog_1 }, /* select div mode */
392 { gf100_clk_prog_2 }, /* (maybe) program pll */
393 { gf100_clk_prog_3 }, /* (maybe) select pll mode */
394 { gf100_clk_prog_4 }, /* final divider */
398 for (i = 0; i < ARRAY_SIZE(stage); i++) {
399 for (j = 0; j < ARRAY_SIZE(priv->eng); j++) {
400 if (!priv->eng[j].freq)
402 stage[i].exec(priv, j);
410 gf100_clk_tidy(struct nvkm_clk *clk)
412 struct gf100_clk_priv *priv = (void *)clk;
413 memset(priv->eng, 0x00, sizeof(priv->eng));
416 static struct nvkm_domain
418 { nv_clk_src_crystal, 0xff },
419 { nv_clk_src_href , 0xff },
420 { nv_clk_src_hubk06 , 0x00 },
421 { nv_clk_src_hubk01 , 0x01 },
422 { nv_clk_src_copy , 0x02 },
423 { nv_clk_src_gpc , 0x03, 0, "core", 2000 },
424 { nv_clk_src_rop , 0x04 },
425 { nv_clk_src_mem , 0x05, 0, "memory", 1000 },
426 { nv_clk_src_vdec , 0x06 },
427 { nv_clk_src_daemon , 0x0a },
428 { nv_clk_src_hubk07 , 0x0b },
433 gf100_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
434 struct nvkm_oclass *oclass, void *data, u32 size,
435 struct nvkm_object **pobject)
437 struct gf100_clk_priv *priv;
440 ret = nvkm_clk_create(parent, engine, oclass, gf100_domain,
441 NULL, 0, false, &priv);
442 *pobject = nv_object(priv);
446 priv->base.read = gf100_clk_read;
447 priv->base.calc = gf100_clk_calc;
448 priv->base.prog = gf100_clk_prog;
449 priv->base.tidy = gf100_clk_tidy;
455 .handle = NV_SUBDEV(CLK, 0xc0),
456 .ofuncs = &(struct nvkm_ofuncs) {
457 .ctor = gf100_clk_ctor,
458 .dtor = _nvkm_clk_dtor,
459 .init = _nvkm_clk_init,
460 .fini = _nvkm_clk_fini,