2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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24 #ifndef __NVKM_CLK_GK20A_H__
25 #define __NVKM_CLK_GK20A_H__
27 #define GK20A_CLK_GPC_MDIV 1000
29 #define SYS_GPCPLL_CFG_BASE 0x00137000
31 /* All frequencies in Khz */
32 struct gk20a_clk_pllg_params {
48 const struct gk20a_clk_pllg_params *params;
52 u32 (*div_to_pl)(u32);
53 u32 (*pl_to_div)(u32);
55 #define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
57 int _gk20a_clk_ctor(struct nvkm_device *, int, const struct nvkm_clk_func *,
58 const struct gk20a_clk_pllg_params *, struct gk20a_clk *);
59 void gk20a_clk_fini(struct nvkm_clk *);
60 int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);
61 int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);
62 int gk20a_clk_prog(struct nvkm_clk *);
63 void gk20a_clk_tidy(struct nvkm_clk *);