drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  52                 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
  53                 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  54                 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  62                         args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
  63                 } else if (a2 > a1) {
  64                         args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  65                         args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = radeon_crtc->h_border;
  71                 args.usOverscanLeft = radeon_crtc->h_border;
  72                 args.usOverscanBottom = radeon_crtc->v_border;
  73                 args.usOverscanTop = radeon_crtc->v_border;
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86
  87         /* fixme - fill in enc_priv for atom dac */
  88         enum radeon_tv_std tv_std = TV_STD_NTSC;
  89         bool is_tv = false, is_cv = false;
  90         struct drm_encoder *encoder;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  96                 /* find tv std */
  97                 if (encoder->crtc == crtc) {
  98                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  99                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 100                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 101                                 tv_std = tv_dac->tv_std;
 102                                 is_tv = true;
 103                         }
 104                 }
 105         }
 106
 107         memset(&args, 0, sizeof(args));
 108
 109         args.ucScaler = radeon_crtc->crtc_id;
 110
 111         if (is_tv) {
 112                 switch (tv_std) {
 113                 case TV_STD_NTSC:
 114                 default:
 115                         args.ucTVStandard = ATOM_TV_NTSC;
 116                         break;
 117                 case TV_STD_PAL:
 118                         args.ucTVStandard = ATOM_TV_PAL;
 119                         break;
 120                 case TV_STD_PAL_M:
 121                         args.ucTVStandard = ATOM_TV_PALM;
 122                         break;
 123                 case TV_STD_PAL_60:
 124                         args.ucTVStandard = ATOM_TV_PAL60;
 125                         break;
 126                 case TV_STD_NTSC_J:
 127                         args.ucTVStandard = ATOM_TV_NTSCJ;
 128                         break;
 129                 case TV_STD_SCART_PAL:
 130                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 131                         break;
 132                 case TV_STD_SECAM:
 133                         args.ucTVStandard = ATOM_TV_SECAM;
 134                         break;
 135                 case TV_STD_PAL_CN:
 136                         args.ucTVStandard = ATOM_TV_PALCN;
 137                         break;
 138                 }
 139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 140         } else if (is_cv) {
 141                 args.ucTVStandard = ATOM_TV_CV;
 142                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 143         } else {
 144                 switch (radeon_crtc->rmx_type) {
 145                 case RMX_FULL:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 case RMX_CENTER:
 149                         args.ucEnable = ATOM_SCALER_CENTER;
 150                         break;
 151                 case RMX_ASPECT:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 default:
 155                         if (ASIC_IS_AVIVO(rdev))
 156                                 args.ucEnable = ATOM_SCALER_DISABLE;
 157                         else
 158                                 args.ucEnable = ATOM_SCALER_CENTER;
 159                         break;
 160                 }
 161         }
 162         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 163         if ((is_tv || is_cv)
 164             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 165                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 166         }
 167 }
 168
 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 170 {
 171         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 172         struct drm_device *dev = crtc->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         int index =
 175             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 176         ENABLE_CRTC_PS_ALLOCATION args;
 177
 178         memset(&args, 0, sizeof(args));
 179
 180         args.ucCRTC = radeon_crtc->crtc_id;
 181         args.ucEnable = lock;
 182
 183         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 184 }
 185
 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189         struct drm_device *dev = crtc->dev;
 190         struct radeon_device *rdev = dev->dev_private;
 191         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 192         ENABLE_CRTC_PS_ALLOCATION args;
 193
 194         memset(&args, 0, sizeof(args));
 195
 196         args.ucCRTC = radeon_crtc->crtc_id;
 197         args.ucEnable = state;
 198
 199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 200 }
 201
 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 203 {
 204         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 205         struct drm_device *dev = crtc->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 208         ENABLE_CRTC_PS_ALLOCATION args;
 209
 210         memset(&args, 0, sizeof(args));
 211
 212         args.ucCRTC = radeon_crtc->crtc_id;
 213         args.ucEnable = state;
 214
 215         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 216 }
 217
 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 219 {
 220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221         struct drm_device *dev = crtc->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 224         BLANK_CRTC_PS_ALLOCATION args;
 225
 226         memset(&args, 0, sizeof(args));
 227
 228         args.ucCRTC = radeon_crtc->crtc_id;
 229         args.ucBlanking = state;
 230
 231         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 232 }
 233
 234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 235 {
 236         struct drm_device *dev = crtc->dev;
 237         struct radeon_device *rdev = dev->dev_private;
 238         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 239
 240         switch (mode) {
 241         case DRM_MODE_DPMS_ON:
 242                 radeon_crtc->enabled = true;
 243                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 244                 radeon_pm_compute_clocks(rdev);
 245                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 246                 if (ASIC_IS_DCE3(rdev))
 247                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 248                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 249                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 250                 radeon_crtc_load_lut(crtc);
 251                 break;
 252         case DRM_MODE_DPMS_STANDBY:
 253         case DRM_MODE_DPMS_SUSPEND:
 254         case DRM_MODE_DPMS_OFF:
 255                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 256                 if (radeon_crtc->enabled)
 257                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 258                 if (ASIC_IS_DCE3(rdev))
 259                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 260                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 261                 radeon_crtc->enabled = false;
 262                 /* adjust pm to dpms changes AFTER disabling crtcs */
 263                 radeon_pm_compute_clocks(rdev);
 264                 break;
 265         }
 266 }
 267
 268 static void
 269 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 270                              struct drm_display_mode *mode)
 271 {
 272         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 273         struct drm_device *dev = crtc->dev;
 274         struct radeon_device *rdev = dev->dev_private;
 275         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 276         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 277         u16 misc = 0;
 278
 279         memset(&args, 0, sizeof(args));
 280         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 281         args.usH_Blanking_Time =
 282                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 283         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 284         args.usV_Blanking_Time =
 285                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 286         args.usH_SyncOffset =
 287                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 288         args.usH_SyncWidth =
 289                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 290         args.usV_SyncOffset =
 291                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 292         args.usV_SyncWidth =
 293                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 294         args.ucH_Border = radeon_crtc->h_border;
 295         args.ucV_Border = radeon_crtc->v_border;
 296
 297         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 298                 misc |= ATOM_VSYNC_POLARITY;
 299         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 300                 misc |= ATOM_HSYNC_POLARITY;
 301         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 302                 misc |= ATOM_COMPOSITESYNC;
 303         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 304                 misc |= ATOM_INTERLACE;
 305         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 306                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 307
 308         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 309         args.ucCRTC = radeon_crtc->crtc_id;
 310
 311         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 312 }
 313
 314 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 315                                      struct drm_display_mode *mode)
 316 {
 317         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 318         struct drm_device *dev = crtc->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 321         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 322         u16 misc = 0;
 323
 324         memset(&args, 0, sizeof(args));
 325         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 326         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 327         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 328         args.usH_SyncWidth =
 329                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 330         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 331         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 332         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 333         args.usV_SyncWidth =
 334                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 335
 336         args.ucOverscanRight = radeon_crtc->h_border;
 337         args.ucOverscanLeft = radeon_crtc->h_border;
 338         args.ucOverscanBottom = radeon_crtc->v_border;
 339         args.ucOverscanTop = radeon_crtc->v_border;
 340
 341         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 342                 misc |= ATOM_VSYNC_POLARITY;
 343         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 344                 misc |= ATOM_HSYNC_POLARITY;
 345         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 346                 misc |= ATOM_COMPOSITESYNC;
 347         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 348                 misc |= ATOM_INTERLACE;
 349         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 350                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 351
 352         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 353         args.ucCRTC = radeon_crtc->crtc_id;
 354
 355         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 356 }
 357
 358 static void atombios_disable_ss(struct drm_crtc *crtc)
 359 {
 360         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 361         struct drm_device *dev = crtc->dev;
 362         struct radeon_device *rdev = dev->dev_private;
 363         u32 ss_cntl;
 364
 365         if (ASIC_IS_DCE4(rdev)) {
 366                 switch (radeon_crtc->pll_id) {
 367                 case ATOM_PPLL1:
 368                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 369                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 370                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 371                         break;
 372                 case ATOM_PPLL2:
 373                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 374                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 375                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 376                         break;
 377                 case ATOM_DCPLL:
 378                 case ATOM_PPLL_INVALID:
 379                         return;
 380                 }
 381         } else if (ASIC_IS_AVIVO(rdev)) {
 382                 switch (radeon_crtc->pll_id) {
 383                 case ATOM_PPLL1:
 384                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 385                         ss_cntl &= ~1;
 386                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 387                         break;
 388                 case ATOM_PPLL2:
 389                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 390                         ss_cntl &= ~1;
 391                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 392                         break;
 393                 case ATOM_DCPLL:
 394                 case ATOM_PPLL_INVALID:
 395                         return;
 396                 }
 397         }
 398 }
 399
 400
 401 union atom_enable_ss {
 402         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 403         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 404         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 405         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 406 };
 407
 408 static void atombios_crtc_program_ss(struct drm_crtc *crtc,
 409                                      int enable,
 410                                      int pll_id,
 411                                      struct radeon_atom_ss *ss)
 412 {
 413         struct drm_device *dev = crtc->dev;
 414         struct radeon_device *rdev = dev->dev_private;
 415         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 416         union atom_enable_ss args;
 417
 418         memset(&args, 0, sizeof(args));
 419
 420         if (ASIC_IS_DCE4(rdev)) {
 421                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 422                 args.v2.ucSpreadSpectrumType = ss->type;
 423                 switch (pll_id) {
 424                 case ATOM_PPLL1:
 425                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 426                         args.v2.usSpreadSpectrumAmount = ss->amount;
 427                         args.v2.usSpreadSpectrumStep = ss->step;
 428                         break;
 429                 case ATOM_PPLL2:
 430                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 431                         args.v2.usSpreadSpectrumAmount = ss->amount;
 432                         args.v2.usSpreadSpectrumStep = ss->step;
 433                         break;
 434                 case ATOM_DCPLL:
 435                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 436                         args.v2.usSpreadSpectrumAmount = 0;
 437                         args.v2.usSpreadSpectrumStep = 0;
 438                         break;
 439                 case ATOM_PPLL_INVALID:
 440                         return;
 441                 }
 442                 args.v2.ucEnable = enable;
 443         } else if (ASIC_IS_DCE3(rdev)) {
 444                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 445                 args.v1.ucSpreadSpectrumType = ss->type;
 446                 args.v1.ucSpreadSpectrumStep = ss->step;
 447                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 448                 args.v1.ucSpreadSpectrumRange = ss->range;
 449                 args.v1.ucPpll = pll_id;
 450                 args.v1.ucEnable = enable;
 451         } else if (ASIC_IS_AVIVO(rdev)) {
 452                 if (enable == ATOM_DISABLE) {
 453                         atombios_disable_ss(crtc);
 454                         return;
 455                 }
 456                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 457                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
 458                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 459                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 460                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 461                 args.lvds_ss_2.ucEnable = enable;
 462         } else {
 463                 if (enable == ATOM_DISABLE) {
 464                         atombios_disable_ss(crtc);
 465                         return;
 466                 }
 467                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 468                 args.lvds_ss.ucSpreadSpectrumType = ss->type;
 469                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 470                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 471                 args.lvds_ss.ucEnable = enable;
 472         }
 473         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 474 }
 475
 476 union adjust_pixel_clock {
 477         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 478         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 479 };
 480
 481 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 482                                struct drm_display_mode *mode,
 483                                struct radeon_pll *pll,
 484                                bool ss_enabled,
 485                                struct radeon_atom_ss *ss)
 486 {
 487         struct drm_device *dev = crtc->dev;
 488         struct radeon_device *rdev = dev->dev_private;
 489         struct drm_encoder *encoder = NULL;
 490         struct radeon_encoder *radeon_encoder = NULL;
 491         u32 adjusted_clock = mode->clock;
 492         int encoder_mode = 0;
 493         u32 dp_clock = mode->clock;
 494         int bpc = 8;
 495
 496         /* reset the pll flags */
 497         pll->flags = 0;
 498
 499         if (ASIC_IS_AVIVO(rdev)) {
 500                 if ((rdev->family == CHIP_RS600) ||
 501                     (rdev->family == CHIP_RS690) ||
 502                     (rdev->family == CHIP_RS740))
 503                         pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 504                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 505
 506                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 507                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 508                 else
 509                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 510         } else {
 511                 pll->flags |= RADEON_PLL_LEGACY;
 512
 513                 if (mode->clock > 200000)       /* range limits??? */
 514                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 515                 else
 516                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 517
 518         }
 519
 520         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 521                 if (encoder->crtc == crtc) {
 522                         radeon_encoder = to_radeon_encoder(encoder);
 523                         encoder_mode = atombios_get_encoder_mode(encoder);
 524                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
 525                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 526                                 if (connector) {
 527                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 528                                         struct radeon_connector_atom_dig *dig_connector =
 529                                                 radeon_connector->con_priv;
 530
 531                                         dp_clock = dig_connector->dp_clock;
 532                                 }
 533                         }
 534 #if 0 /* doesn't work properly on some laptops */
 535                         /* use recommended ref_div for ss */
 536                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 537                                 if (ss_enabled) {
 538                                         if (ss->refdiv) {
 539                                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 540                                                 pll->reference_div = ss->refdiv;
 541                                         }
 542                                 }
 543                         }
 544 #endif
 545                         if (ASIC_IS_AVIVO(rdev)) {
 546                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 547                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 548                                         adjusted_clock = mode->clock * 2;
 549                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 550                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 551                         } else {
 552                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 553                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 554                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 555                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 556                         }
 557                         break;
 558                 }
 559         }
 560
 561         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 562          * accordingly based on the encoder/transmitter to work around
 563          * special hw requirements.
 564          */
 565         if (ASIC_IS_DCE3(rdev)) {
 566                 union adjust_pixel_clock args;
 567                 u8 frev, crev;
 568                 int index;
 569
 570                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 571                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 572                                            &crev))
 573                         return adjusted_clock;
 574
 575                 memset(&args, 0, sizeof(args));
 576
 577                 switch (frev) {
 578                 case 1:
 579                         switch (crev) {
 580                         case 1:
 581                         case 2:
 582                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 583                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 584                                 args.v1.ucEncodeMode = encoder_mode;
 585                                 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 586                                         if (ss_enabled)
 587                                                 args.v1.ucConfig |=
 588                                                         ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 589                                 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
 590                                         args.v1.ucConfig |=
 591                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 592                                 }
 593
 594                                 atom_execute_table(rdev->mode_info.atom_context,
 595                                                    index, (uint32_t *)&args);
 596                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 597                                 break;
 598                         case 3:
 599                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 600                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 601                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 602                                 args.v3.sInput.ucDispPllConfig = 0;
 603                                 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 604                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 605                                         if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 606                                                 if (ss_enabled)
 607                                                         args.v3.sInput.ucDispPllConfig |=
 608                                                                 DISPPLL_CONFIG_SS_ENABLE;
 609                                                 args.v3.sInput.ucDispPllConfig |=
 610                                                         DISPPLL_CONFIG_COHERENT_MODE;
 611                                                 /* 16200 or 27000 */
 612                                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 613                                         } else {
 614                                                 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
 615                                                         /* deep color support */
 616                                                         args.v3.sInput.usPixelClock =
 617                                                                 cpu_to_le16((mode->clock * bpc / 8) / 10);
 618                                                 }
 619                                                 if (dig->coherent_mode)
 620                                                         args.v3.sInput.ucDispPllConfig |=
 621                                                                 DISPPLL_CONFIG_COHERENT_MODE;
 622                                                 if (mode->clock > 165000)
 623                                                         args.v3.sInput.ucDispPllConfig |=
 624                                                                 DISPPLL_CONFIG_DUAL_LINK;
 625                                         }
 626                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 627                                         if (encoder_mode == ATOM_ENCODER_MODE_DP) {
 628                                                 if (ss_enabled)
 629                                                         args.v3.sInput.ucDispPllConfig |=
 630                                                                 DISPPLL_CONFIG_SS_ENABLE;
 631                                                 args.v3.sInput.ucDispPllConfig |=
 632                                                         DISPPLL_CONFIG_COHERENT_MODE;
 633                                                 /* 16200 or 27000 */
 634                                                 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 635                                         } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
 636                                                 if (ss_enabled)
 637                                                         args.v3.sInput.ucDispPllConfig |=
 638                                                                 DISPPLL_CONFIG_SS_ENABLE;
 639                                         } else {
 640                                                 if (mode->clock > 165000)
 641                                                         args.v3.sInput.ucDispPllConfig |=
 642                                                                 DISPPLL_CONFIG_DUAL_LINK;
 643                                         }
 644                                 }
 645                                 atom_execute_table(rdev->mode_info.atom_context,
 646                                                    index, (uint32_t *)&args);
 647                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 648                                 if (args.v3.sOutput.ucRefDiv) {
 649                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 650                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 651                                 }
 652                                 if (args.v3.sOutput.ucPostDiv) {
 653                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 654                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 655                                 }
 656                                 break;
 657                         default:
 658                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 659                                 return adjusted_clock;
 660                         }
 661                         break;
 662                 default:
 663                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 664                         return adjusted_clock;
 665                 }
 666         }
 667         return adjusted_clock;
 668 }
 669
 670 union set_pixel_clock {
 671         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 672         PIXEL_CLOCK_PARAMETERS v1;
 673         PIXEL_CLOCK_PARAMETERS_V2 v2;
 674         PIXEL_CLOCK_PARAMETERS_V3 v3;
 675         PIXEL_CLOCK_PARAMETERS_V5 v5;
 676         PIXEL_CLOCK_PARAMETERS_V6 v6;
 677 };
 678
 679 /* on DCE5, make sure the voltage is high enough to support the
 680  * required disp clk.
 681  */
 682 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
 683                                     u32 dispclk)
 684 {
 685         struct drm_device *dev = crtc->dev;
 686         struct radeon_device *rdev = dev->dev_private;
 687         u8 frev, crev;
 688         int index;
 689         union set_pixel_clock args;
 690
 691         memset(&args, 0, sizeof(args));
 692
 693         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 694         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 695                                    &crev))
 696                 return;
 697
 698         switch (frev) {
 699         case 1:
 700                 switch (crev) {
 701                 case 5:
 702                         /* if the default dcpll clock is specified,
 703                          * SetPixelClock provides the dividers
 704                          */
 705                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 706                         args.v5.usPixelClock = dispclk;
 707                         args.v5.ucPpll = ATOM_DCPLL;
 708                         break;
 709                 case 6:
 710                         /* if the default dcpll clock is specified,
 711                          * SetPixelClock provides the dividers
 712                          */
 713                         args.v6.ulDispEngClkFreq = dispclk;
 714                         args.v6.ucPpll = ATOM_DCPLL;
 715                         break;
 716                 default:
 717                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 718                         return;
 719                 }
 720                 break;
 721         default:
 722                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 723                 return;
 724         }
 725         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 726 }
 727
 728 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 729                                       int crtc_id,
 730                                       int pll_id,
 731                                       u32 encoder_mode,
 732                                       u32 encoder_id,
 733                                       u32 clock,
 734                                       u32 ref_div,
 735                                       u32 fb_div,
 736                                       u32 frac_fb_div,
 737                                       u32 post_div)
 738 {
 739         struct drm_device *dev = crtc->dev;
 740         struct radeon_device *rdev = dev->dev_private;
 741         u8 frev, crev;
 742         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 743         union set_pixel_clock args;
 744
 745         memset(&args, 0, sizeof(args));
 746
 747         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 748                                    &crev))
 749                 return;
 750
 751         switch (frev) {
 752         case 1:
 753                 switch (crev) {
 754                 case 1:
 755                         if (clock == ATOM_DISABLE)
 756                                 return;
 757                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 758                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 759                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 760                         args.v1.ucFracFbDiv = frac_fb_div;
 761                         args.v1.ucPostDiv = post_div;
 762                         args.v1.ucPpll = pll_id;
 763                         args.v1.ucCRTC = crtc_id;
 764                         args.v1.ucRefDivSrc = 1;
 765                         break;
 766                 case 2:
 767                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 768                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 769                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 770                         args.v2.ucFracFbDiv = frac_fb_div;
 771                         args.v2.ucPostDiv = post_div;
 772                         args.v2.ucPpll = pll_id;
 773                         args.v2.ucCRTC = crtc_id;
 774                         args.v2.ucRefDivSrc = 1;
 775                         break;
 776                 case 3:
 777                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 778                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 779                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 780                         args.v3.ucFracFbDiv = frac_fb_div;
 781                         args.v3.ucPostDiv = post_div;
 782                         args.v3.ucPpll = pll_id;
 783                         args.v3.ucMiscInfo = (pll_id << 2);
 784                         args.v3.ucTransmitterId = encoder_id;
 785                         args.v3.ucEncoderMode = encoder_mode;
 786                         break;
 787                 case 5:
 788                         args.v5.ucCRTC = crtc_id;
 789                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 790                         args.v5.ucRefDiv = ref_div;
 791                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 792                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 793                         args.v5.ucPostDiv = post_div;
 794                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 795                         args.v5.ucTransmitterID = encoder_id;
 796                         args.v5.ucEncoderMode = encoder_mode;
 797                         args.v5.ucPpll = pll_id;
 798                         break;
 799                 case 6:
 800                         args.v6.ulCrtcPclkFreq.ucCRTC = crtc_id;
 801                         args.v6.ulCrtcPclkFreq.ulPixelClock = cpu_to_le32(clock / 10);
 802                         args.v6.ucRefDiv = ref_div;
 803                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 804                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 805                         args.v6.ucPostDiv = post_div;
 806                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 807                         args.v6.ucTransmitterID = encoder_id;
 808                         args.v6.ucEncoderMode = encoder_mode;
 809                         args.v6.ucPpll = pll_id;
 810                         break;
 811                 default:
 812                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 813                         return;
 814                 }
 815                 break;
 816         default:
 817                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 818                 return;
 819         }
 820
 821         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 822 }
 823
 824 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 825 {
 826         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 827         struct drm_device *dev = crtc->dev;
 828         struct radeon_device *rdev = dev->dev_private;
 829         struct drm_encoder *encoder = NULL;
 830         struct radeon_encoder *radeon_encoder = NULL;
 831         u32 pll_clock = mode->clock;
 832         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 833         struct radeon_pll *pll;
 834         u32 adjusted_clock;
 835         int encoder_mode = 0;
 836         struct radeon_atom_ss ss;
 837         bool ss_enabled = false;
 838
 839         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 840                 if (encoder->crtc == crtc) {
 841                         radeon_encoder = to_radeon_encoder(encoder);
 842                         encoder_mode = atombios_get_encoder_mode(encoder);
 843                         break;
 844                 }
 845         }
 846
 847         if (!radeon_encoder)
 848                 return;
 849
 850         switch (radeon_crtc->pll_id) {
 851         case ATOM_PPLL1:
 852                 pll = &rdev->clock.p1pll;
 853                 break;
 854         case ATOM_PPLL2:
 855                 pll = &rdev->clock.p2pll;
 856                 break;
 857         case ATOM_DCPLL:
 858         case ATOM_PPLL_INVALID:
 859         default:
 860                 pll = &rdev->clock.dcpll;
 861                 break;
 862         }
 863
 864         if (radeon_encoder->active_device &
 865             (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
 866                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 867                 struct drm_connector *connector =
 868                         radeon_get_connector_for_encoder(encoder);
 869                 struct radeon_connector *radeon_connector =
 870                         to_radeon_connector(connector);
 871                 struct radeon_connector_atom_dig *dig_connector =
 872                         radeon_connector->con_priv;
 873                 int dp_clock;
 874
 875                 switch (encoder_mode) {
 876                 case ATOM_ENCODER_MODE_DP:
 877                         /* DP/eDP */
 878                         dp_clock = dig_connector->dp_clock / 10;
 879                         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 880                                 if (ASIC_IS_DCE4(rdev))
 881                                         ss_enabled =
 882                                                 radeon_atombios_get_asic_ss_info(rdev, &ss,
 883                                                                                  dig->lcd_ss_id,
 884                                                                                  dp_clock);
 885                                 else
 886                                         ss_enabled =
 887                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 888                                                                                  dig->lcd_ss_id);
 889                         } else {
 890                                 if (ASIC_IS_DCE4(rdev))
 891                                         ss_enabled =
 892                                                 radeon_atombios_get_asic_ss_info(rdev, &ss,
 893                                                                                  ASIC_INTERNAL_SS_ON_DP,
 894                                                                                  dp_clock);
 895                                 else {
 896                                         if (dp_clock == 16200) {
 897                                                 ss_enabled =
 898                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
 899                                                                                          ATOM_DP_SS_ID2);
 900                                                 if (!ss_enabled)
 901                                                         ss_enabled =
 902                                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 903                                                                                                  ATOM_DP_SS_ID1);
 904                                         } else
 905                                                 ss_enabled =
 906                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
 907                                                                                          ATOM_DP_SS_ID1);
 908                                 }
 909                         }
 910                         break;
 911                 case ATOM_ENCODER_MODE_LVDS:
 912                         if (ASIC_IS_DCE4(rdev))
 913                                 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
 914                                                                               dig->lcd_ss_id,
 915                                                                               mode->clock / 10);
 916                         else
 917                                 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
 918                                                                               dig->lcd_ss_id);
 919                         break;
 920                 case ATOM_ENCODER_MODE_DVI:
 921                         if (ASIC_IS_DCE4(rdev))
 922                                 ss_enabled =
 923                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
 924                                                                          ASIC_INTERNAL_SS_ON_TMDS,
 925                                                                          mode->clock / 10);
 926                         break;
 927                 case ATOM_ENCODER_MODE_HDMI:
 928                         if (ASIC_IS_DCE4(rdev))
 929                                 ss_enabled =
 930                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
 931                                                                          ASIC_INTERNAL_SS_ON_HDMI,
 932                                                                          mode->clock / 10);
 933                         break;
 934                 default:
 935                         break;
 936                 }
 937         }
 938
 939         /* adjust pixel clock as needed */
 940         adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
 941
 942         radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
 943                            &ref_div, &post_div);
 944
 945         atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
 946
 947         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
 948                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
 949                                   ref_div, fb_div, frac_fb_div, post_div);
 950
 951         if (ss_enabled) {
 952                 /* calculate ss amount and step size */
 953                 if (ASIC_IS_DCE4(rdev)) {
 954                         u32 step_size;
 955                         u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
 956                         ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
 957                         ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
 958                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
 959                         if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
 960                                 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
 961                                         (125 * 25 * pll->reference_freq / 100);
 962                         else
 963                                 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
 964                                         (125 * 25 * pll->reference_freq / 100);
 965                         ss.step = step_size;
 966                 }
 967
 968                 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
 969         }
 970 }
 971
 972 static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
 973                                       struct drm_framebuffer *fb,
 974                                       int x, int y, int atomic)
 975 {
 976         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 977         struct drm_device *dev = crtc->dev;
 978         struct radeon_device *rdev = dev->dev_private;
 979         struct radeon_framebuffer *radeon_fb;
 980         struct drm_framebuffer *target_fb;
 981         struct drm_gem_object *obj;
 982         struct radeon_bo *rbo;
 983         uint64_t fb_location;
 984         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 985         int r;
 986
 987         /* no fb bound */
 988         if (!atomic && !crtc->fb) {
 989                 DRM_DEBUG_KMS("No FB bound\n");
 990                 return 0;
 991         }
 992
 993         if (atomic) {
 994                 radeon_fb = to_radeon_framebuffer(fb);
 995                 target_fb = fb;
 996         }
 997         else {
 998                 radeon_fb = to_radeon_framebuffer(crtc->fb);
 999                 target_fb = crtc->fb;
1000         }
1001
1002         /* If atomic, assume fb object is pinned & idle & fenced and
1003          * just update base pointers
1004          */
1005         obj = radeon_fb->obj;
1006         rbo = obj->driver_private;
1007         r = radeon_bo_reserve(rbo, false);
1008         if (unlikely(r != 0))
1009                 return r;
1010
1011         if (atomic)
1012                 fb_location = radeon_bo_gpu_offset(rbo);
1013         else {
1014                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1015                 if (unlikely(r != 0)) {
1016                         radeon_bo_unreserve(rbo);
1017                         return -EINVAL;
1018                 }
1019         }
1020
1021         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1022         radeon_bo_unreserve(rbo);
1023
1024         switch (target_fb->bits_per_pixel) {
1025         case 8:
1026                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1027                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1028                 break;
1029         case 15:
1030                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1031                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1032                 break;
1033         case 16:
1034                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1035                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1036                 break;
1037         case 24:
1038         case 32:
1039                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1040                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1041                 break;
1042         default:
1043                 DRM_ERROR("Unsupported screen depth %d\n",
1044                           target_fb->bits_per_pixel);
1045                 return -EINVAL;
1046         }
1047
1048         if (tiling_flags & RADEON_TILING_MACRO)
1049                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1050         else if (tiling_flags & RADEON_TILING_MICRO)
1051                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1052
1053         switch (radeon_crtc->crtc_id) {
1054         case 0:
1055                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1056                 break;
1057         case 1:
1058                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1059                 break;
1060         case 2:
1061                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1062                 break;
1063         case 3:
1064                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1065                 break;
1066         case 4:
1067                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1068                 break;
1069         case 5:
1070                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1071                 break;
1072         default:
1073                 break;
1074         }
1075
1076         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1077                upper_32_bits(fb_location));
1078         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1079                upper_32_bits(fb_location));
1080         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1081                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1082         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1083                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1084         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1085
1086         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1087         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1088         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1089         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1090         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1091         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1092
1093         fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1094         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1095         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1096
1097         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1098                crtc->mode.vdisplay);
1099         x &= ~3;
1100         y &= ~1;
1101         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1102                (x << 16) | y);
1103         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1104                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1105
1106         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1107                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1108                        EVERGREEN_INTERLEAVE_EN);
1109         else
1110                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1111
1112         if (!atomic && fb && fb != crtc->fb) {
1113                 radeon_fb = to_radeon_framebuffer(fb);
1114                 rbo = radeon_fb->obj->driver_private;
1115                 r = radeon_bo_reserve(rbo, false);
1116                 if (unlikely(r != 0))
1117                         return r;
1118                 radeon_bo_unpin(rbo);
1119                 radeon_bo_unreserve(rbo);
1120         }
1121
1122         /* Bytes per pixel may have changed */
1123         radeon_bandwidth_update(rdev);
1124
1125         return 0;
1126 }
1127
1128 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1129                                   struct drm_framebuffer *fb,
1130                                   int x, int y, int atomic)
1131 {
1132         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1133         struct drm_device *dev = crtc->dev;
1134         struct radeon_device *rdev = dev->dev_private;
1135         struct radeon_framebuffer *radeon_fb;
1136         struct drm_gem_object *obj;
1137         struct radeon_bo *rbo;
1138         struct drm_framebuffer *target_fb;
1139         uint64_t fb_location;
1140         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1141         int r;
1142
1143         /* no fb bound */
1144         if (!atomic && !crtc->fb) {
1145                 DRM_DEBUG_KMS("No FB bound\n");
1146                 return 0;
1147         }
1148
1149         if (atomic) {
1150                 radeon_fb = to_radeon_framebuffer(fb);
1151                 target_fb = fb;
1152         }
1153         else {
1154                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1155                 target_fb = crtc->fb;
1156         }
1157
1158         obj = radeon_fb->obj;
1159         rbo = obj->driver_private;
1160         r = radeon_bo_reserve(rbo, false);
1161         if (unlikely(r != 0))
1162                 return r;
1163
1164         /* If atomic, assume fb object is pinned & idle & fenced and
1165          * just update base pointers
1166          */
1167         if (atomic)
1168                 fb_location = radeon_bo_gpu_offset(rbo);
1169         else {
1170                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1171                 if (unlikely(r != 0)) {
1172                         radeon_bo_unreserve(rbo);
1173                         return -EINVAL;
1174                 }
1175         }
1176         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1177         radeon_bo_unreserve(rbo);
1178
1179         switch (target_fb->bits_per_pixel) {
1180         case 8:
1181                 fb_format =
1182                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1183                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1184                 break;
1185         case 15:
1186                 fb_format =
1187                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1188                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1189                 break;
1190         case 16:
1191                 fb_format =
1192                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1193                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1194                 break;
1195         case 24:
1196         case 32:
1197                 fb_format =
1198                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1199                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1200                 break;
1201         default:
1202                 DRM_ERROR("Unsupported screen depth %d\n",
1203                           target_fb->bits_per_pixel);
1204                 return -EINVAL;
1205         }
1206
1207         if (rdev->family >= CHIP_R600) {
1208                 if (tiling_flags & RADEON_TILING_MACRO)
1209                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1210                 else if (tiling_flags & RADEON_TILING_MICRO)
1211                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1212         } else {
1213                 if (tiling_flags & RADEON_TILING_MACRO)
1214                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1215
1216                 if (tiling_flags & RADEON_TILING_MICRO)
1217                         fb_format |= AVIVO_D1GRPH_TILED;
1218         }
1219
1220         if (radeon_crtc->crtc_id == 0)
1221                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1222         else
1223                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1224
1225         if (rdev->family >= CHIP_RV770) {
1226                 if (radeon_crtc->crtc_id) {
1227                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1228                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1229                 } else {
1230                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1231                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1232                 }
1233         }
1234         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1235                (u32) fb_location);
1236         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1237                radeon_crtc->crtc_offset, (u32) fb_location);
1238         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1239
1240         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1241         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1242         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1243         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1244         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1245         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1246
1247         fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1248         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1249         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1250
1251         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1252                crtc->mode.vdisplay);
1253         x &= ~3;
1254         y &= ~1;
1255         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1256                (x << 16) | y);
1257         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1258                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1259
1260         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1261                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1262                        AVIVO_D1MODE_INTERLEAVE_EN);
1263         else
1264                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1265
1266         if (!atomic && fb && fb != crtc->fb) {
1267                 radeon_fb = to_radeon_framebuffer(fb);
1268                 rbo = radeon_fb->obj->driver_private;
1269                 r = radeon_bo_reserve(rbo, false);
1270                 if (unlikely(r != 0))
1271                         return r;
1272                 radeon_bo_unpin(rbo);
1273                 radeon_bo_unreserve(rbo);
1274         }
1275
1276         /* Bytes per pixel may have changed */
1277         radeon_bandwidth_update(rdev);
1278
1279         return 0;
1280 }
1281
1282 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1283                            struct drm_framebuffer *old_fb)
1284 {
1285         struct drm_device *dev = crtc->dev;
1286         struct radeon_device *rdev = dev->dev_private;
1287
1288         if (ASIC_IS_DCE4(rdev))
1289                 return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
1290         else if (ASIC_IS_AVIVO(rdev))
1291                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1292         else
1293                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1294 }
1295
1296 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1297                                   struct drm_framebuffer *fb,
1298                                   int x, int y, enum mode_set_atomic state)
1299 {
1300        struct drm_device *dev = crtc->dev;
1301        struct radeon_device *rdev = dev->dev_private;
1302
1303         if (ASIC_IS_DCE4(rdev))
1304                 return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
1305         else if (ASIC_IS_AVIVO(rdev))
1306                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1307         else
1308                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1309 }
1310
1311 /* properly set additional regs when using atombios */
1312 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1313 {
1314         struct drm_device *dev = crtc->dev;
1315         struct radeon_device *rdev = dev->dev_private;
1316         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1317         u32 disp_merge_cntl;
1318
1319         switch (radeon_crtc->crtc_id) {
1320         case 0:
1321                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1322                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1323                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1324                 break;
1325         case 1:
1326                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1327                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1328                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1329                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1330                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1331                 break;
1332         }
1333 }
1334
1335 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1336 {
1337         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1338         struct drm_device *dev = crtc->dev;
1339         struct radeon_device *rdev = dev->dev_private;
1340         struct drm_encoder *test_encoder;
1341         struct drm_crtc *test_crtc;
1342         uint32_t pll_in_use = 0;
1343
1344         if (ASIC_IS_DCE4(rdev)) {
1345                 /* if crtc is driving DP and we have an ext clock, use that */
1346                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1347                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1348                                 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1349                                         if (rdev->clock.dp_extclk)
1350                                                 return ATOM_PPLL_INVALID;
1351                                 }
1352                         }
1353                 }
1354
1355                 /* otherwise, pick one of the plls */
1356                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1357                         struct radeon_crtc *radeon_test_crtc;
1358
1359                         if (crtc == test_crtc)
1360                                 continue;
1361
1362                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1363                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1364                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1365                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1366                 }
1367                 if (!(pll_in_use & 1))
1368                         return ATOM_PPLL1;
1369                 return ATOM_PPLL2;
1370         } else
1371                 return radeon_crtc->crtc_id;
1372
1373 }
1374
1375 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1376                            struct drm_display_mode *mode,
1377                            struct drm_display_mode *adjusted_mode,
1378                            int x, int y, struct drm_framebuffer *old_fb)
1379 {
1380         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1381         struct drm_device *dev = crtc->dev;
1382         struct radeon_device *rdev = dev->dev_private;
1383         struct drm_encoder *encoder;
1384         bool is_tvcv = false;
1385
1386         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1387                 /* find tv std */
1388                 if (encoder->crtc == crtc) {
1389                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1390                         if (radeon_encoder->active_device &
1391                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1392                                 is_tvcv = true;
1393                 }
1394         }
1395
1396         /* always set DCPLL */
1397         if (ASIC_IS_DCE4(rdev)) {
1398                 struct radeon_atom_ss ss;
1399                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1400                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1401                                                                    rdev->clock.default_dispclk);
1402                 if (ss_enabled)
1403                         atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1404                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1405                 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
1406                 if (ss_enabled)
1407                         atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1408         }
1409         atombios_crtc_set_pll(crtc, adjusted_mode);
1410
1411         if (ASIC_IS_DCE4(rdev))
1412                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1413         else if (ASIC_IS_AVIVO(rdev)) {
1414                 if (is_tvcv)
1415                         atombios_crtc_set_timing(crtc, adjusted_mode);
1416                 else
1417                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1418         } else {
1419                 atombios_crtc_set_timing(crtc, adjusted_mode);
1420                 if (radeon_crtc->crtc_id == 0)
1421                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1422                 radeon_legacy_atom_fixup(crtc);
1423         }
1424         atombios_crtc_set_base(crtc, x, y, old_fb);
1425         atombios_overscan_setup(crtc, mode, adjusted_mode);
1426         atombios_scaler_setup(crtc);
1427         return 0;
1428 }
1429
1430 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1431                                      struct drm_display_mode *mode,
1432                                      struct drm_display_mode *adjusted_mode)
1433 {
1434         struct drm_device *dev = crtc->dev;
1435         struct radeon_device *rdev = dev->dev_private;
1436
1437         /* adjust pm to upcoming mode change */
1438         radeon_pm_compute_clocks(rdev);
1439
1440         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1441                 return false;
1442         return true;
1443 }
1444
1445 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1446 {
1447         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1448
1449         /* pick pll */
1450         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1451
1452         atombios_lock_crtc(crtc, ATOM_ENABLE);
1453         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1454 }
1455
1456 static void atombios_crtc_commit(struct drm_crtc *crtc)
1457 {
1458         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1459         atombios_lock_crtc(crtc, ATOM_DISABLE);
1460 }
1461
1462 static void atombios_crtc_disable(struct drm_crtc *crtc)
1463 {
1464         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1465         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1466
1467         switch (radeon_crtc->pll_id) {
1468         case ATOM_PPLL1:
1469         case ATOM_PPLL2:
1470                 /* disable the ppll */
1471                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1472                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1473                 break;
1474         default:
1475                 break;
1476         }
1477         radeon_crtc->pll_id = -1;
1478 }
1479
1480 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1481         .dpms = atombios_crtc_dpms,
1482         .mode_fixup = atombios_crtc_mode_fixup,
1483         .mode_set = atombios_crtc_mode_set,
1484         .mode_set_base = atombios_crtc_set_base,
1485         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1486         .prepare = atombios_crtc_prepare,
1487         .commit = atombios_crtc_commit,
1488         .load_lut = radeon_crtc_load_lut,
1489         .disable = atombios_crtc_disable,
1490 };
1491
1492 void radeon_atombios_init_crtc(struct drm_device *dev,
1493                                struct radeon_crtc *radeon_crtc)
1494 {
1495         struct radeon_device *rdev = dev->dev_private;
1496
1497         if (ASIC_IS_DCE4(rdev)) {
1498                 switch (radeon_crtc->crtc_id) {
1499                 case 0:
1500                 default:
1501                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1502                         break;
1503                 case 1:
1504                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1505                         break;
1506                 case 2:
1507                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1508                         break;
1509                 case 3:
1510                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1511                         break;
1512                 case 4:
1513                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1514                         break;
1515                 case 5:
1516                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1517                         break;
1518                 }
1519         } else {
1520                 if (radeon_crtc->crtc_id == 1)
1521                         radeon_crtc->crtc_offset =
1522                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1523                 else
1524                         radeon_crtc->crtc_offset = 0;
1525         }
1526         radeon_crtc->pll_id = -1;
1527         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1528 }