drivers/gpu/drm/radeon/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include <drm/drm_fixed.h>
  30 #include "radeon.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_overscan_setup(struct drm_crtc *crtc,
  35                                     struct drm_display_mode *mode,
  36                                     struct drm_display_mode *adjusted_mode)
  37 {
  38         struct drm_device *dev = crtc->dev;
  39         struct radeon_device *rdev = dev->dev_private;
  40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
  42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
  43         int a1, a2;
  44
  45         memset(&args, 0, sizeof(args));
  46
  47         args.ucCRTC = radeon_crtc->crtc_id;
  48
  49         switch (radeon_crtc->rmx_type) {
  50         case RMX_CENTER:
  51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
  53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
  55                 break;
  56         case RMX_ASPECT:
  57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
  58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
  59
  60                 if (a1 > a2) {
  61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
  63                 } else if (a2 > a1) {
  64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
  66                 }
  67                 break;
  68         case RMX_FULL:
  69         default:
  70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
  71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
  72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
  73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
  74                 break;
  75         }
  76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  77 }
  78
  79 static void atombios_scaler_setup(struct drm_crtc *crtc)
  80 {
  81         struct drm_device *dev = crtc->dev;
  82         struct radeon_device *rdev = dev->dev_private;
  83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  84         ENABLE_SCALER_PS_ALLOCATION args;
  85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
  86
  87         /* fixme - fill in enc_priv for atom dac */
  88         enum radeon_tv_std tv_std = TV_STD_NTSC;
  89         bool is_tv = false, is_cv = false;
  90         struct drm_encoder *encoder;
  91
  92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
  93                 return;
  94
  95         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  96                 /* find tv std */
  97                 if (encoder->crtc == crtc) {
  98                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  99                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
 100                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 101                                 tv_std = tv_dac->tv_std;
 102                                 is_tv = true;
 103                         }
 104                 }
 105         }
 106
 107         memset(&args, 0, sizeof(args));
 108
 109         args.ucScaler = radeon_crtc->crtc_id;
 110
 111         if (is_tv) {
 112                 switch (tv_std) {
 113                 case TV_STD_NTSC:
 114                 default:
 115                         args.ucTVStandard = ATOM_TV_NTSC;
 116                         break;
 117                 case TV_STD_PAL:
 118                         args.ucTVStandard = ATOM_TV_PAL;
 119                         break;
 120                 case TV_STD_PAL_M:
 121                         args.ucTVStandard = ATOM_TV_PALM;
 122                         break;
 123                 case TV_STD_PAL_60:
 124                         args.ucTVStandard = ATOM_TV_PAL60;
 125                         break;
 126                 case TV_STD_NTSC_J:
 127                         args.ucTVStandard = ATOM_TV_NTSCJ;
 128                         break;
 129                 case TV_STD_SCART_PAL:
 130                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
 131                         break;
 132                 case TV_STD_SECAM:
 133                         args.ucTVStandard = ATOM_TV_SECAM;
 134                         break;
 135                 case TV_STD_PAL_CN:
 136                         args.ucTVStandard = ATOM_TV_PALCN;
 137                         break;
 138                 }
 139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 140         } else if (is_cv) {
 141                 args.ucTVStandard = ATOM_TV_CV;
 142                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
 143         } else {
 144                 switch (radeon_crtc->rmx_type) {
 145                 case RMX_FULL:
 146                         args.ucEnable = ATOM_SCALER_EXPANSION;
 147                         break;
 148                 case RMX_CENTER:
 149                         args.ucEnable = ATOM_SCALER_CENTER;
 150                         break;
 151                 case RMX_ASPECT:
 152                         args.ucEnable = ATOM_SCALER_EXPANSION;
 153                         break;
 154                 default:
 155                         if (ASIC_IS_AVIVO(rdev))
 156                                 args.ucEnable = ATOM_SCALER_DISABLE;
 157                         else
 158                                 args.ucEnable = ATOM_SCALER_CENTER;
 159                         break;
 160                 }
 161         }
 162         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 163         if ((is_tv || is_cv)
 164             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
 165                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
 166         }
 167 }
 168
 169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
 170 {
 171         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 172         struct drm_device *dev = crtc->dev;
 173         struct radeon_device *rdev = dev->dev_private;
 174         int index =
 175             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
 176         ENABLE_CRTC_PS_ALLOCATION args;
 177
 178         memset(&args, 0, sizeof(args));
 179
 180         args.ucCRTC = radeon_crtc->crtc_id;
 181         args.ucEnable = lock;
 182
 183         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 184 }
 185
 186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
 187 {
 188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 189         struct drm_device *dev = crtc->dev;
 190         struct radeon_device *rdev = dev->dev_private;
 191         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
 192         ENABLE_CRTC_PS_ALLOCATION args;
 193
 194         memset(&args, 0, sizeof(args));
 195
 196         args.ucCRTC = radeon_crtc->crtc_id;
 197         args.ucEnable = state;
 198
 199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 200 }
 201
 202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
 203 {
 204         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 205         struct drm_device *dev = crtc->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
 208         ENABLE_CRTC_PS_ALLOCATION args;
 209
 210         memset(&args, 0, sizeof(args));
 211
 212         args.ucCRTC = radeon_crtc->crtc_id;
 213         args.ucEnable = state;
 214
 215         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 216 }
 217
 218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
 219 {
 220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 221         struct drm_device *dev = crtc->dev;
 222         struct radeon_device *rdev = dev->dev_private;
 223         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
 224         BLANK_CRTC_PS_ALLOCATION args;
 225
 226         memset(&args, 0, sizeof(args));
 227
 228         args.ucCRTC = radeon_crtc->crtc_id;
 229         args.ucBlanking = state;
 230
 231         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 232 }
 233
 234 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
 235 {
 236         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 237         struct drm_device *dev = crtc->dev;
 238         struct radeon_device *rdev = dev->dev_private;
 239         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
 240         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
 241
 242         memset(&args, 0, sizeof(args));
 243
 244         args.ucDispPipeId = radeon_crtc->crtc_id;
 245         args.ucEnable = state;
 246
 247         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 248 }
 249
 250 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
 251 {
 252         struct drm_device *dev = crtc->dev;
 253         struct radeon_device *rdev = dev->dev_private;
 254         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 255
 256         switch (mode) {
 257         case DRM_MODE_DPMS_ON:
 258                 radeon_crtc->enabled = true;
 259                 /* adjust pm to dpms changes BEFORE enabling crtcs */
 260                 radeon_pm_compute_clocks(rdev);
 261                 /* disable crtc pair power gating before programming */
 262                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
 263                         atombios_powergate_crtc(crtc, ATOM_DISABLE);
 264                 atombios_enable_crtc(crtc, ATOM_ENABLE);
 265                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 266                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
 267                 atombios_blank_crtc(crtc, ATOM_DISABLE);
 268                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
 269                 radeon_crtc_load_lut(crtc);
 270                 break;
 271         case DRM_MODE_DPMS_STANDBY:
 272         case DRM_MODE_DPMS_SUSPEND:
 273         case DRM_MODE_DPMS_OFF:
 274                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
 275                 if (radeon_crtc->enabled)
 276                         atombios_blank_crtc(crtc, ATOM_ENABLE);
 277                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
 278                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
 279                 atombios_enable_crtc(crtc, ATOM_DISABLE);
 280                 radeon_crtc->enabled = false;
 281                 /* power gating is per-pair */
 282                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {
 283                         struct drm_crtc *other_crtc;
 284                         struct radeon_crtc *other_radeon_crtc;
 285                         list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
 286                                 other_radeon_crtc = to_radeon_crtc(other_crtc);
 287                                 if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
 288                                     ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
 289                                     ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
 290                                     ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
 291                                     ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
 292                                     ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
 293                                         /* if both crtcs in the pair are off, enable power gating */
 294                                         if (other_radeon_crtc->enabled == false)
 295                                                 atombios_powergate_crtc(crtc, ATOM_ENABLE);
 296                                         break;
 297                                 }
 298                         }
 299                 }
 300                 /* adjust pm to dpms changes AFTER disabling crtcs */
 301                 radeon_pm_compute_clocks(rdev);
 302                 break;
 303         }
 304 }
 305
 306 static void
 307 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
 308                              struct drm_display_mode *mode)
 309 {
 310         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 311         struct drm_device *dev = crtc->dev;
 312         struct radeon_device *rdev = dev->dev_private;
 313         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
 314         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
 315         u16 misc = 0;
 316
 317         memset(&args, 0, sizeof(args));
 318         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
 319         args.usH_Blanking_Time =
 320                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
 321         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
 322         args.usV_Blanking_Time =
 323                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
 324         args.usH_SyncOffset =
 325                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
 326         args.usH_SyncWidth =
 327                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 328         args.usV_SyncOffset =
 329                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
 330         args.usV_SyncWidth =
 331                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 332         args.ucH_Border = radeon_crtc->h_border;
 333         args.ucV_Border = radeon_crtc->v_border;
 334
 335         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 336                 misc |= ATOM_VSYNC_POLARITY;
 337         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 338                 misc |= ATOM_HSYNC_POLARITY;
 339         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 340                 misc |= ATOM_COMPOSITESYNC;
 341         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 342                 misc |= ATOM_INTERLACE;
 343         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 344                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 345
 346         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 347         args.ucCRTC = radeon_crtc->crtc_id;
 348
 349         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 350 }
 351
 352 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
 353                                      struct drm_display_mode *mode)
 354 {
 355         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 356         struct drm_device *dev = crtc->dev;
 357         struct radeon_device *rdev = dev->dev_private;
 358         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
 359         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 360         u16 misc = 0;
 361
 362         memset(&args, 0, sizeof(args));
 363         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
 364         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
 365         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
 366         args.usH_SyncWidth =
 367                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
 368         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
 369         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
 370         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
 371         args.usV_SyncWidth =
 372                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 373
 374         args.ucOverscanRight = radeon_crtc->h_border;
 375         args.ucOverscanLeft = radeon_crtc->h_border;
 376         args.ucOverscanBottom = radeon_crtc->v_border;
 377         args.ucOverscanTop = radeon_crtc->v_border;
 378
 379         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 380                 misc |= ATOM_VSYNC_POLARITY;
 381         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 382                 misc |= ATOM_HSYNC_POLARITY;
 383         if (mode->flags & DRM_MODE_FLAG_CSYNC)
 384                 misc |= ATOM_COMPOSITESYNC;
 385         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 386                 misc |= ATOM_INTERLACE;
 387         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 388                 misc |= ATOM_DOUBLE_CLOCK_MODE;
 389
 390         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
 391         args.ucCRTC = radeon_crtc->crtc_id;
 392
 393         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 394 }
 395
 396 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
 397 {
 398         u32 ss_cntl;
 399
 400         if (ASIC_IS_DCE4(rdev)) {
 401                 switch (pll_id) {
 402                 case ATOM_PPLL1:
 403                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
 404                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 405                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
 406                         break;
 407                 case ATOM_PPLL2:
 408                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
 409                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
 410                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
 411                         break;
 412                 case ATOM_DCPLL:
 413                 case ATOM_PPLL_INVALID:
 414                         return;
 415                 }
 416         } else if (ASIC_IS_AVIVO(rdev)) {
 417                 switch (pll_id) {
 418                 case ATOM_PPLL1:
 419                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
 420                         ss_cntl &= ~1;
 421                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
 422                         break;
 423                 case ATOM_PPLL2:
 424                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
 425                         ss_cntl &= ~1;
 426                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
 427                         break;
 428                 case ATOM_DCPLL:
 429                 case ATOM_PPLL_INVALID:
 430                         return;
 431                 }
 432         }
 433 }
 434
 435
 436 union atom_enable_ss {
 437         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
 438         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
 439         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
 440         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
 441         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
 442 };
 443
 444 static void atombios_crtc_program_ss(struct radeon_device *rdev,
 445                                      int enable,
 446                                      int pll_id,
 447                                      struct radeon_atom_ss *ss)
 448 {
 449         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
 450         union atom_enable_ss args;
 451
 452         memset(&args, 0, sizeof(args));
 453
 454         if (ASIC_IS_DCE5(rdev)) {
 455                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
 456                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 457                 switch (pll_id) {
 458                 case ATOM_PPLL1:
 459                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
 460                         break;
 461                 case ATOM_PPLL2:
 462                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
 463                         break;
 464                 case ATOM_DCPLL:
 465                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
 466                         break;
 467                 case ATOM_PPLL_INVALID:
 468                         return;
 469                 }
 470                 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 471                 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 472                 args.v3.ucEnable = enable;
 473                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
 474                         args.v3.ucEnable = ATOM_DISABLE;
 475         } else if (ASIC_IS_DCE4(rdev)) {
 476                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 477                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 478                 switch (pll_id) {
 479                 case ATOM_PPLL1:
 480                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
 481                         break;
 482                 case ATOM_PPLL2:
 483                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
 484                         break;
 485                 case ATOM_DCPLL:
 486                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
 487                         break;
 488                 case ATOM_PPLL_INVALID:
 489                         return;
 490                 }
 491                 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
 492                 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
 493                 args.v2.ucEnable = enable;
 494                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
 495                         args.v2.ucEnable = ATOM_DISABLE;
 496         } else if (ASIC_IS_DCE3(rdev)) {
 497                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 498                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 499                 args.v1.ucSpreadSpectrumStep = ss->step;
 500                 args.v1.ucSpreadSpectrumDelay = ss->delay;
 501                 args.v1.ucSpreadSpectrumRange = ss->range;
 502                 args.v1.ucPpll = pll_id;
 503                 args.v1.ucEnable = enable;
 504         } else if (ASIC_IS_AVIVO(rdev)) {
 505                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 506                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 507                         atombios_disable_ss(rdev, pll_id);
 508                         return;
 509                 }
 510                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 511                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 512                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
 513                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
 514                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
 515                 args.lvds_ss_2.ucEnable = enable;
 516         } else {
 517                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
 518                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
 519                         atombios_disable_ss(rdev, pll_id);
 520                         return;
 521                 }
 522                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
 523                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
 524                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
 525                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
 526                 args.lvds_ss.ucEnable = enable;
 527         }
 528         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 529 }
 530
 531 union adjust_pixel_clock {
 532         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
 533         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
 534 };
 535
 536 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
 537                                struct drm_display_mode *mode,
 538                                struct radeon_pll *pll,
 539                                bool ss_enabled,
 540                                struct radeon_atom_ss *ss)
 541 {
 542         struct drm_device *dev = crtc->dev;
 543         struct radeon_device *rdev = dev->dev_private;
 544         struct drm_encoder *encoder = NULL;
 545         struct radeon_encoder *radeon_encoder = NULL;
 546         struct drm_connector *connector = NULL;
 547         u32 adjusted_clock = mode->clock;
 548         int encoder_mode = 0;
 549         u32 dp_clock = mode->clock;
 550         int bpc = 8;
 551         bool is_duallink = false;
 552
 553         /* reset the pll flags */
 554         pll->flags = 0;
 555
 556         if (ASIC_IS_AVIVO(rdev)) {
 557                 if ((rdev->family == CHIP_RS600) ||
 558                     (rdev->family == CHIP_RS690) ||
 559                     (rdev->family == CHIP_RS740))
 560                         pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
 561                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
 562
 563                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
 564                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 565                 else
 566                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 567
 568                 if (rdev->family < CHIP_RV770)
 569                         pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
 570                 /* use frac fb div on APUs */
 571                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
 572                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 573         } else {
 574                 pll->flags |= RADEON_PLL_LEGACY;
 575
 576                 if (mode->clock > 200000)       /* range limits??? */
 577                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 578                 else
 579                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 580         }
 581
 582         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 583                 if (encoder->crtc == crtc) {
 584                         radeon_encoder = to_radeon_encoder(encoder);
 585                         connector = radeon_get_connector_for_encoder(encoder);
 586                         bpc = radeon_get_monitor_bpc(connector);
 587                         encoder_mode = atombios_get_encoder_mode(encoder);
 588                         is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
 589                         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 590                             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 591                                 if (connector) {
 592                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 593                                         struct radeon_connector_atom_dig *dig_connector =
 594                                                 radeon_connector->con_priv;
 595
 596                                         dp_clock = dig_connector->dp_clock;
 597                                 }
 598                         }
 599
 600                         /* use recommended ref_div for ss */
 601                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 602                                 if (ss_enabled) {
 603                                         if (ss->refdiv) {
 604                                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
 605                                                 pll->reference_div = ss->refdiv;
 606                                                 if (ASIC_IS_AVIVO(rdev))
 607                                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 608                                         }
 609                                 }
 610                         }
 611
 612                         if (ASIC_IS_AVIVO(rdev)) {
 613                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
 614                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
 615                                         adjusted_clock = mode->clock * 2;
 616                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
 617                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
 618                                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 619                                         pll->flags |= RADEON_PLL_IS_LCD;
 620                         } else {
 621                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 622                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
 623                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
 624                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 625                         }
 626                         break;
 627                 }
 628         }
 629
 630         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
 631          * accordingly based on the encoder/transmitter to work around
 632          * special hw requirements.
 633          */
 634         if (ASIC_IS_DCE3(rdev)) {
 635                 union adjust_pixel_clock args;
 636                 u8 frev, crev;
 637                 int index;
 638
 639                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
 640                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 641                                            &crev))
 642                         return adjusted_clock;
 643
 644                 memset(&args, 0, sizeof(args));
 645
 646                 switch (frev) {
 647                 case 1:
 648                         switch (crev) {
 649                         case 1:
 650                         case 2:
 651                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
 652                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
 653                                 args.v1.ucEncodeMode = encoder_mode;
 654                                 if (ss_enabled && ss->percentage)
 655                                         args.v1.ucConfig |=
 656                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
 657
 658                                 atom_execute_table(rdev->mode_info.atom_context,
 659                                                    index, (uint32_t *)&args);
 660                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
 661                                 break;
 662                         case 3:
 663                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
 664                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
 665                                 args.v3.sInput.ucEncodeMode = encoder_mode;
 666                                 args.v3.sInput.ucDispPllConfig = 0;
 667                                 if (ss_enabled && ss->percentage)
 668                                         args.v3.sInput.ucDispPllConfig |=
 669                                                 DISPPLL_CONFIG_SS_ENABLE;
 670                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
 671                                         args.v3.sInput.ucDispPllConfig |=
 672                                                 DISPPLL_CONFIG_COHERENT_MODE;
 673                                         /* 16200 or 27000 */
 674                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
 675                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
 676                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 677                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
 678                                                 /* deep color support */
 679                                                 args.v3.sInput.usPixelClock =
 680                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
 681                                         if (dig->coherent_mode)
 682                                                 args.v3.sInput.ucDispPllConfig |=
 683                                                         DISPPLL_CONFIG_COHERENT_MODE;
 684                                         if (is_duallink)
 685                                                 args.v3.sInput.ucDispPllConfig |=
 686                                                         DISPPLL_CONFIG_DUAL_LINK;
 687                                 }
 688                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
 689                                     ENCODER_OBJECT_ID_NONE)
 690                                         args.v3.sInput.ucExtTransmitterID =
 691                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
 692                                 else
 693                                         args.v3.sInput.ucExtTransmitterID = 0;
 694
 695                                 atom_execute_table(rdev->mode_info.atom_context,
 696                                                    index, (uint32_t *)&args);
 697                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
 698                                 if (args.v3.sOutput.ucRefDiv) {
 699                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 700                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
 701                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
 702                                 }
 703                                 if (args.v3.sOutput.ucPostDiv) {
 704                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
 705                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
 706                                         pll->post_div = args.v3.sOutput.ucPostDiv;
 707                                 }
 708                                 break;
 709                         default:
 710                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 711                                 return adjusted_clock;
 712                         }
 713                         break;
 714                 default:
 715                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 716                         return adjusted_clock;
 717                 }
 718         }
 719         return adjusted_clock;
 720 }
 721
 722 union set_pixel_clock {
 723         SET_PIXEL_CLOCK_PS_ALLOCATION base;
 724         PIXEL_CLOCK_PARAMETERS v1;
 725         PIXEL_CLOCK_PARAMETERS_V2 v2;
 726         PIXEL_CLOCK_PARAMETERS_V3 v3;
 727         PIXEL_CLOCK_PARAMETERS_V5 v5;
 728         PIXEL_CLOCK_PARAMETERS_V6 v6;
 729 };
 730
 731 /* on DCE5, make sure the voltage is high enough to support the
 732  * required disp clk.
 733  */
 734 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
 735                                     u32 dispclk)
 736 {
 737         u8 frev, crev;
 738         int index;
 739         union set_pixel_clock args;
 740
 741         memset(&args, 0, sizeof(args));
 742
 743         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 744         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 745                                    &crev))
 746                 return;
 747
 748         switch (frev) {
 749         case 1:
 750                 switch (crev) {
 751                 case 5:
 752                         /* if the default dcpll clock is specified,
 753                          * SetPixelClock provides the dividers
 754                          */
 755                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
 756                         args.v5.usPixelClock = cpu_to_le16(dispclk);
 757                         args.v5.ucPpll = ATOM_DCPLL;
 758                         break;
 759                 case 6:
 760                         /* if the default dcpll clock is specified,
 761                          * SetPixelClock provides the dividers
 762                          */
 763                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
 764                         if (ASIC_IS_DCE61(rdev))
 765                                 args.v6.ucPpll = ATOM_EXT_PLL1;
 766                         else if (ASIC_IS_DCE6(rdev))
 767                                 args.v6.ucPpll = ATOM_PPLL0;
 768                         else
 769                                 args.v6.ucPpll = ATOM_DCPLL;
 770                         break;
 771                 default:
 772                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 773                         return;
 774                 }
 775                 break;
 776         default:
 777                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 778                 return;
 779         }
 780         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 781 }
 782
 783 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
 784                                       u32 crtc_id,
 785                                       int pll_id,
 786                                       u32 encoder_mode,
 787                                       u32 encoder_id,
 788                                       u32 clock,
 789                                       u32 ref_div,
 790                                       u32 fb_div,
 791                                       u32 frac_fb_div,
 792                                       u32 post_div,
 793                                       int bpc,
 794                                       bool ss_enabled,
 795                                       struct radeon_atom_ss *ss)
 796 {
 797         struct drm_device *dev = crtc->dev;
 798         struct radeon_device *rdev = dev->dev_private;
 799         u8 frev, crev;
 800         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 801         union set_pixel_clock args;
 802
 803         memset(&args, 0, sizeof(args));
 804
 805         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
 806                                    &crev))
 807                 return;
 808
 809         switch (frev) {
 810         case 1:
 811                 switch (crev) {
 812                 case 1:
 813                         if (clock == ATOM_DISABLE)
 814                                 return;
 815                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
 816                         args.v1.usRefDiv = cpu_to_le16(ref_div);
 817                         args.v1.usFbDiv = cpu_to_le16(fb_div);
 818                         args.v1.ucFracFbDiv = frac_fb_div;
 819                         args.v1.ucPostDiv = post_div;
 820                         args.v1.ucPpll = pll_id;
 821                         args.v1.ucCRTC = crtc_id;
 822                         args.v1.ucRefDivSrc = 1;
 823                         break;
 824                 case 2:
 825                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
 826                         args.v2.usRefDiv = cpu_to_le16(ref_div);
 827                         args.v2.usFbDiv = cpu_to_le16(fb_div);
 828                         args.v2.ucFracFbDiv = frac_fb_div;
 829                         args.v2.ucPostDiv = post_div;
 830                         args.v2.ucPpll = pll_id;
 831                         args.v2.ucCRTC = crtc_id;
 832                         args.v2.ucRefDivSrc = 1;
 833                         break;
 834                 case 3:
 835                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
 836                         args.v3.usRefDiv = cpu_to_le16(ref_div);
 837                         args.v3.usFbDiv = cpu_to_le16(fb_div);
 838                         args.v3.ucFracFbDiv = frac_fb_div;
 839                         args.v3.ucPostDiv = post_div;
 840                         args.v3.ucPpll = pll_id;
 841                         args.v3.ucMiscInfo = (pll_id << 2);
 842                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 843                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
 844                         args.v3.ucTransmitterId = encoder_id;
 845                         args.v3.ucEncoderMode = encoder_mode;
 846                         break;
 847                 case 5:
 848                         args.v5.ucCRTC = crtc_id;
 849                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
 850                         args.v5.ucRefDiv = ref_div;
 851                         args.v5.usFbDiv = cpu_to_le16(fb_div);
 852                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 853                         args.v5.ucPostDiv = post_div;
 854                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
 855                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 856                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
 857                         switch (bpc) {
 858                         case 8:
 859                         default:
 860                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
 861                                 break;
 862                         case 10:
 863                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
 864                                 break;
 865                         }
 866                         args.v5.ucTransmitterID = encoder_id;
 867                         args.v5.ucEncoderMode = encoder_mode;
 868                         args.v5.ucPpll = pll_id;
 869                         break;
 870                 case 6:
 871                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
 872                         args.v6.ucRefDiv = ref_div;
 873                         args.v6.usFbDiv = cpu_to_le16(fb_div);
 874                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
 875                         args.v6.ucPostDiv = post_div;
 876                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
 877                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
 878                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
 879                         switch (bpc) {
 880                         case 8:
 881                         default:
 882                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
 883                                 break;
 884                         case 10:
 885                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
 886                                 break;
 887                         case 12:
 888                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
 889                                 break;
 890                         case 16:
 891                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
 892                                 break;
 893                         }
 894                         args.v6.ucTransmitterID = encoder_id;
 895                         args.v6.ucEncoderMode = encoder_mode;
 896                         args.v6.ucPpll = pll_id;
 897                         break;
 898                 default:
 899                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 900                         return;
 901                 }
 902                 break;
 903         default:
 904                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 905                 return;
 906         }
 907
 908         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 909 }
 910
 911 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 912 {
 913         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 914         struct drm_device *dev = crtc->dev;
 915         struct radeon_device *rdev = dev->dev_private;
 916         struct drm_encoder *encoder = NULL;
 917         struct radeon_encoder *radeon_encoder = NULL;
 918         u32 pll_clock = mode->clock;
 919         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
 920         struct radeon_pll *pll;
 921         u32 adjusted_clock;
 922         int encoder_mode = 0;
 923         struct radeon_atom_ss ss;
 924         bool ss_enabled = false;
 925         int bpc = 8;
 926
 927         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 928                 if (encoder->crtc == crtc) {
 929                         radeon_encoder = to_radeon_encoder(encoder);
 930                         encoder_mode = atombios_get_encoder_mode(encoder);
 931                         break;
 932                 }
 933         }
 934
 935         if (!radeon_encoder)
 936                 return;
 937
 938         switch (radeon_crtc->pll_id) {
 939         case ATOM_PPLL1:
 940                 pll = &rdev->clock.p1pll;
 941                 break;
 942         case ATOM_PPLL2:
 943                 pll = &rdev->clock.p2pll;
 944                 break;
 945         case ATOM_DCPLL:
 946         case ATOM_PPLL_INVALID:
 947         default:
 948                 pll = &rdev->clock.dcpll;
 949                 break;
 950         }
 951
 952         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
 953             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
 954                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 955                 struct drm_connector *connector =
 956                         radeon_get_connector_for_encoder(encoder);
 957                 struct radeon_connector *radeon_connector =
 958                         to_radeon_connector(connector);
 959                 struct radeon_connector_atom_dig *dig_connector =
 960                         radeon_connector->con_priv;
 961                 int dp_clock;
 962                 bpc = radeon_get_monitor_bpc(connector);
 963
 964                 switch (encoder_mode) {
 965                 case ATOM_ENCODER_MODE_DP_MST:
 966                 case ATOM_ENCODER_MODE_DP:
 967                         /* DP/eDP */
 968                         dp_clock = dig_connector->dp_clock / 10;
 969                         if (ASIC_IS_DCE4(rdev))
 970                                 ss_enabled =
 971                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
 972                                                                          ASIC_INTERNAL_SS_ON_DP,
 973                                                                          dp_clock);
 974                         else {
 975                                 if (dp_clock == 16200) {
 976                                         ss_enabled =
 977                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 978                                                                                  ATOM_DP_SS_ID2);
 979                                         if (!ss_enabled)
 980                                                 ss_enabled =
 981                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
 982                                                                                          ATOM_DP_SS_ID1);
 983                                 } else
 984                                         ss_enabled =
 985                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
 986                                                                                  ATOM_DP_SS_ID1);
 987                         }
 988                         break;
 989                 case ATOM_ENCODER_MODE_LVDS:
 990                         if (ASIC_IS_DCE4(rdev))
 991                                 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
 992                                                                               dig->lcd_ss_id,
 993                                                                               mode->clock / 10);
 994                         else
 995                                 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
 996                                                                               dig->lcd_ss_id);
 997                         break;
 998                 case ATOM_ENCODER_MODE_DVI:
 999                         if (ASIC_IS_DCE4(rdev))
1000                                 ss_enabled =
1001                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
1002                                                                          ASIC_INTERNAL_SS_ON_TMDS,
1003                                                                          mode->clock / 10);
1004                         break;
1005                 case ATOM_ENCODER_MODE_HDMI:
1006                         if (ASIC_IS_DCE4(rdev))
1007                                 ss_enabled =
1008                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
1009                                                                          ASIC_INTERNAL_SS_ON_HDMI,
1010                                                                          mode->clock / 10);
1011                         break;
1012                 default:
1013                         break;
1014                 }
1015         }
1016
1017         /* adjust pixel clock as needed */
1018         adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1019
1020         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1021                 /* TV seems to prefer the legacy algo on some boards */
1022                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1023                                           &ref_div, &post_div);
1024         else if (ASIC_IS_AVIVO(rdev))
1025                 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1026                                          &ref_div, &post_div);
1027         else
1028                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1029                                           &ref_div, &post_div);
1030
1031         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1032
1033         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1034                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1035                                   ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1036
1037         if (ss_enabled) {
1038                 /* calculate ss amount and step size */
1039                 if (ASIC_IS_DCE4(rdev)) {
1040                         u32 step_size;
1041                         u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1042                         ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1043                         ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1044                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1045                         if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1046                                 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1047                                         (125 * 25 * pll->reference_freq / 100);
1048                         else
1049                                 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1050                                         (125 * 25 * pll->reference_freq / 100);
1051                         ss.step = step_size;
1052                 }
1053
1054                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1055         }
1056 }
1057
1058 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1059                                  struct drm_framebuffer *fb,
1060                                  int x, int y, int atomic)
1061 {
1062         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1063         struct drm_device *dev = crtc->dev;
1064         struct radeon_device *rdev = dev->dev_private;
1065         struct radeon_framebuffer *radeon_fb;
1066         struct drm_framebuffer *target_fb;
1067         struct drm_gem_object *obj;
1068         struct radeon_bo *rbo;
1069         uint64_t fb_location;
1070         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1071         unsigned bankw, bankh, mtaspect, tile_split;
1072         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1073         u32 tmp, viewport_w, viewport_h;
1074         int r;
1075
1076         /* no fb bound */
1077         if (!atomic && !crtc->fb) {
1078                 DRM_DEBUG_KMS("No FB bound\n");
1079                 return 0;
1080         }
1081
1082         if (atomic) {
1083                 radeon_fb = to_radeon_framebuffer(fb);
1084                 target_fb = fb;
1085         }
1086         else {
1087                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1088                 target_fb = crtc->fb;
1089         }
1090
1091         /* If atomic, assume fb object is pinned & idle & fenced and
1092          * just update base pointers
1093          */
1094         obj = radeon_fb->obj;
1095         rbo = gem_to_radeon_bo(obj);
1096         r = radeon_bo_reserve(rbo, false);
1097         if (unlikely(r != 0))
1098                 return r;
1099
1100         if (atomic)
1101                 fb_location = radeon_bo_gpu_offset(rbo);
1102         else {
1103                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1104                 if (unlikely(r != 0)) {
1105                         radeon_bo_unreserve(rbo);
1106                         return -EINVAL;
1107                 }
1108         }
1109
1110         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1111         radeon_bo_unreserve(rbo);
1112
1113         switch (target_fb->bits_per_pixel) {
1114         case 8:
1115                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1116                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1117                 break;
1118         case 15:
1119                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1120                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1121                 break;
1122         case 16:
1123                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1124                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1125 #ifdef __BIG_ENDIAN
1126                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1127 #endif
1128                 break;
1129         case 24:
1130         case 32:
1131                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1132                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1133 #ifdef __BIG_ENDIAN
1134                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1135 #endif
1136                 break;
1137         default:
1138                 DRM_ERROR("Unsupported screen depth %d\n",
1139                           target_fb->bits_per_pixel);
1140                 return -EINVAL;
1141         }
1142
1143         if (tiling_flags & RADEON_TILING_MACRO) {
1144                 if (rdev->family >= CHIP_TAHITI)
1145                         tmp = rdev->config.si.tile_config;
1146                 else if (rdev->family >= CHIP_CAYMAN)
1147                         tmp = rdev->config.cayman.tile_config;
1148                 else
1149                         tmp = rdev->config.evergreen.tile_config;
1150
1151                 switch ((tmp & 0xf0) >> 4) {
1152                 case 0: /* 4 banks */
1153                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1154                         break;
1155                 case 1: /* 8 banks */
1156                 default:
1157                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1158                         break;
1159                 case 2: /* 16 banks */
1160                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1161                         break;
1162                 }
1163
1164                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1165
1166                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1167                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1168                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1169                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1170                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1171         } else if (tiling_flags & RADEON_TILING_MICRO)
1172                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1173
1174         if ((rdev->family == CHIP_TAHITI) ||
1175             (rdev->family == CHIP_PITCAIRN))
1176                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1177         else if (rdev->family == CHIP_VERDE)
1178                 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1179
1180         switch (radeon_crtc->crtc_id) {
1181         case 0:
1182                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1183                 break;
1184         case 1:
1185                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1186                 break;
1187         case 2:
1188                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1189                 break;
1190         case 3:
1191                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1192                 break;
1193         case 4:
1194                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1195                 break;
1196         case 5:
1197                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1198                 break;
1199         default:
1200                 break;
1201         }
1202
1203         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1204                upper_32_bits(fb_location));
1205         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1206                upper_32_bits(fb_location));
1207         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1208                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1209         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1210                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1211         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1212         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1213
1214         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1215         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1216         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1217         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1218         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1219         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1220
1221         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1222         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1223         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1224
1225         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1226                target_fb->height);
1227         x &= ~3;
1228         y &= ~1;
1229         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1230                (x << 16) | y);
1231         viewport_w = crtc->mode.hdisplay;
1232         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1233         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1234                (viewport_w << 16) | viewport_h);
1235
1236         /* pageflip setup */
1237         /* make sure flip is at vb rather than hb */
1238         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1239         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1240         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1241
1242         /* set pageflip to happen anywhere in vblank interval */
1243         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1244
1245         if (!atomic && fb && fb != crtc->fb) {
1246                 radeon_fb = to_radeon_framebuffer(fb);
1247                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1248                 r = radeon_bo_reserve(rbo, false);
1249                 if (unlikely(r != 0))
1250                         return r;
1251                 radeon_bo_unpin(rbo);
1252                 radeon_bo_unreserve(rbo);
1253         }
1254
1255         /* Bytes per pixel may have changed */
1256         radeon_bandwidth_update(rdev);
1257
1258         return 0;
1259 }
1260
1261 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1262                                   struct drm_framebuffer *fb,
1263                                   int x, int y, int atomic)
1264 {
1265         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1266         struct drm_device *dev = crtc->dev;
1267         struct radeon_device *rdev = dev->dev_private;
1268         struct radeon_framebuffer *radeon_fb;
1269         struct drm_gem_object *obj;
1270         struct radeon_bo *rbo;
1271         struct drm_framebuffer *target_fb;
1272         uint64_t fb_location;
1273         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1274         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1275         u32 tmp, viewport_w, viewport_h;
1276         int r;
1277
1278         /* no fb bound */
1279         if (!atomic && !crtc->fb) {
1280                 DRM_DEBUG_KMS("No FB bound\n");
1281                 return 0;
1282         }
1283
1284         if (atomic) {
1285                 radeon_fb = to_radeon_framebuffer(fb);
1286                 target_fb = fb;
1287         }
1288         else {
1289                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1290                 target_fb = crtc->fb;
1291         }
1292
1293         obj = radeon_fb->obj;
1294         rbo = gem_to_radeon_bo(obj);
1295         r = radeon_bo_reserve(rbo, false);
1296         if (unlikely(r != 0))
1297                 return r;
1298
1299         /* If atomic, assume fb object is pinned & idle & fenced and
1300          * just update base pointers
1301          */
1302         if (atomic)
1303                 fb_location = radeon_bo_gpu_offset(rbo);
1304         else {
1305                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1306                 if (unlikely(r != 0)) {
1307                         radeon_bo_unreserve(rbo);
1308                         return -EINVAL;
1309                 }
1310         }
1311         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1312         radeon_bo_unreserve(rbo);
1313
1314         switch (target_fb->bits_per_pixel) {
1315         case 8:
1316                 fb_format =
1317                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1318                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1319                 break;
1320         case 15:
1321                 fb_format =
1322                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1323                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1324                 break;
1325         case 16:
1326                 fb_format =
1327                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1328                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1329 #ifdef __BIG_ENDIAN
1330                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1331 #endif
1332                 break;
1333         case 24:
1334         case 32:
1335                 fb_format =
1336                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1337                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1338 #ifdef __BIG_ENDIAN
1339                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1340 #endif
1341                 break;
1342         default:
1343                 DRM_ERROR("Unsupported screen depth %d\n",
1344                           target_fb->bits_per_pixel);
1345                 return -EINVAL;
1346         }
1347
1348         if (rdev->family >= CHIP_R600) {
1349                 if (tiling_flags & RADEON_TILING_MACRO)
1350                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1351                 else if (tiling_flags & RADEON_TILING_MICRO)
1352                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1353         } else {
1354                 if (tiling_flags & RADEON_TILING_MACRO)
1355                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1356
1357                 if (tiling_flags & RADEON_TILING_MICRO)
1358                         fb_format |= AVIVO_D1GRPH_TILED;
1359         }
1360
1361         if (radeon_crtc->crtc_id == 0)
1362                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1363         else
1364                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1365
1366         if (rdev->family >= CHIP_RV770) {
1367                 if (radeon_crtc->crtc_id) {
1368                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1369                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1370                 } else {
1371                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1372                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1373                 }
1374         }
1375         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1376                (u32) fb_location);
1377         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1378                radeon_crtc->crtc_offset, (u32) fb_location);
1379         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1380         if (rdev->family >= CHIP_R600)
1381                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1382
1383         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1384         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1385         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1386         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1387         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1388         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1389
1390         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1391         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1392         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1393
1394         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1395                target_fb->height);
1396         x &= ~3;
1397         y &= ~1;
1398         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1399                (x << 16) | y);
1400         viewport_w = crtc->mode.hdisplay;
1401         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1402         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1403                (viewport_w << 16) | viewport_h);
1404
1405         /* pageflip setup */
1406         /* make sure flip is at vb rather than hb */
1407         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1408         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1409         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1410
1411         /* set pageflip to happen anywhere in vblank interval */
1412         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1413
1414         if (!atomic && fb && fb != crtc->fb) {
1415                 radeon_fb = to_radeon_framebuffer(fb);
1416                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1417                 r = radeon_bo_reserve(rbo, false);
1418                 if (unlikely(r != 0))
1419                         return r;
1420                 radeon_bo_unpin(rbo);
1421                 radeon_bo_unreserve(rbo);
1422         }
1423
1424         /* Bytes per pixel may have changed */
1425         radeon_bandwidth_update(rdev);
1426
1427         return 0;
1428 }
1429
1430 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1431                            struct drm_framebuffer *old_fb)
1432 {
1433         struct drm_device *dev = crtc->dev;
1434         struct radeon_device *rdev = dev->dev_private;
1435
1436         if (ASIC_IS_DCE4(rdev))
1437                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1438         else if (ASIC_IS_AVIVO(rdev))
1439                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1440         else
1441                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1442 }
1443
1444 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1445                                   struct drm_framebuffer *fb,
1446                                   int x, int y, enum mode_set_atomic state)
1447 {
1448        struct drm_device *dev = crtc->dev;
1449        struct radeon_device *rdev = dev->dev_private;
1450
1451         if (ASIC_IS_DCE4(rdev))
1452                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1453         else if (ASIC_IS_AVIVO(rdev))
1454                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1455         else
1456                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1457 }
1458
1459 /* properly set additional regs when using atombios */
1460 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1461 {
1462         struct drm_device *dev = crtc->dev;
1463         struct radeon_device *rdev = dev->dev_private;
1464         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1465         u32 disp_merge_cntl;
1466
1467         switch (radeon_crtc->crtc_id) {
1468         case 0:
1469                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1470                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1471                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1472                 break;
1473         case 1:
1474                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1475                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1476                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1477                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1478                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1479                 break;
1480         }
1481 }
1482
1483 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1484 {
1485         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1486         struct drm_device *dev = crtc->dev;
1487         struct radeon_device *rdev = dev->dev_private;
1488         struct drm_encoder *test_encoder;
1489         struct drm_crtc *test_crtc;
1490         uint32_t pll_in_use = 0;
1491
1492         if (ASIC_IS_DCE61(rdev)) {
1493                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1494                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1495                                 struct radeon_encoder *test_radeon_encoder =
1496                                         to_radeon_encoder(test_encoder);
1497                                 struct radeon_encoder_atom_dig *dig =
1498                                         test_radeon_encoder->enc_priv;
1499
1500                                 if ((test_radeon_encoder->encoder_id ==
1501                                      ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1502                                     (dig->linkb == false)) /* UNIPHY A uses PPLL2 */
1503                                         return ATOM_PPLL2;
1504                         }
1505                 }
1506                 /* UNIPHY B/C/D/E/F */
1507                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1508                         struct radeon_crtc *radeon_test_crtc;
1509
1510                         if (crtc == test_crtc)
1511                                 continue;
1512
1513                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1514                         if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
1515                             (radeon_test_crtc->pll_id == ATOM_PPLL1))
1516                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1517                 }
1518                 if (!(pll_in_use & 4))
1519                         return ATOM_PPLL0;
1520                 return ATOM_PPLL1;
1521         } else if (ASIC_IS_DCE4(rdev)) {
1522                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1523                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1524                                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1525                                  * depending on the asic:
1526                                  * DCE4: PPLL or ext clock
1527                                  * DCE5: DCPLL or ext clock
1528                                  *
1529                                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1530                                  * PPLL/DCPLL programming and only program the DP DTO for the
1531                                  * crtc virtual pixel clock.
1532                                  */
1533                                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1534                                         if (rdev->clock.dp_extclk)
1535                                                 return ATOM_PPLL_INVALID;
1536                                         else if (ASIC_IS_DCE6(rdev))
1537                                                 return ATOM_PPLL0;
1538                                         else if (ASIC_IS_DCE5(rdev))
1539                                                 return ATOM_DCPLL;
1540                                 }
1541                         }
1542                 }
1543
1544                 /* otherwise, pick one of the plls */
1545                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1546                         struct radeon_crtc *radeon_test_crtc;
1547
1548                         if (crtc == test_crtc)
1549                                 continue;
1550
1551                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1552                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1553                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1554                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1555                 }
1556                 if (!(pll_in_use & 1))
1557                         return ATOM_PPLL1;
1558                 return ATOM_PPLL2;
1559         } else
1560                 return radeon_crtc->crtc_id;
1561
1562 }
1563
1564 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1565 {
1566         /* always set DCPLL */
1567         if (ASIC_IS_DCE6(rdev))
1568                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1569         else if (ASIC_IS_DCE4(rdev)) {
1570                 struct radeon_atom_ss ss;
1571                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1572                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1573                                                                    rdev->clock.default_dispclk);
1574                 if (ss_enabled)
1575                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
1576                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1577                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1578                 if (ss_enabled)
1579                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
1580         }
1581
1582 }
1583
1584 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1585                            struct drm_display_mode *mode,
1586                            struct drm_display_mode *adjusted_mode,
1587                            int x, int y, struct drm_framebuffer *old_fb)
1588 {
1589         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1590         struct drm_device *dev = crtc->dev;
1591         struct radeon_device *rdev = dev->dev_private;
1592         struct drm_encoder *encoder;
1593         bool is_tvcv = false;
1594
1595         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1596                 /* find tv std */
1597                 if (encoder->crtc == crtc) {
1598                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1599                         if (radeon_encoder->active_device &
1600                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1601                                 is_tvcv = true;
1602                 }
1603         }
1604
1605         atombios_crtc_set_pll(crtc, adjusted_mode);
1606
1607         if (ASIC_IS_DCE4(rdev))
1608                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1609         else if (ASIC_IS_AVIVO(rdev)) {
1610                 if (is_tvcv)
1611                         atombios_crtc_set_timing(crtc, adjusted_mode);
1612                 else
1613                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1614         } else {
1615                 atombios_crtc_set_timing(crtc, adjusted_mode);
1616                 if (radeon_crtc->crtc_id == 0)
1617                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1618                 radeon_legacy_atom_fixup(crtc);
1619         }
1620         atombios_crtc_set_base(crtc, x, y, old_fb);
1621         atombios_overscan_setup(crtc, mode, adjusted_mode);
1622         atombios_scaler_setup(crtc);
1623         return 0;
1624 }
1625
1626 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1627                                      const struct drm_display_mode *mode,
1628                                      struct drm_display_mode *adjusted_mode)
1629 {
1630         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1631                 return false;
1632         return true;
1633 }
1634
1635 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1636 {
1637         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1638         struct drm_device *dev = crtc->dev;
1639         struct radeon_device *rdev = dev->dev_private;
1640
1641         radeon_crtc->in_mode_set = true;
1642         /* pick pll */
1643         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1644
1645         /* disable crtc pair power gating before programming */
1646         if (ASIC_IS_DCE6(rdev))
1647                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1648
1649         atombios_lock_crtc(crtc, ATOM_ENABLE);
1650         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1651 }
1652
1653 static void atombios_crtc_commit(struct drm_crtc *crtc)
1654 {
1655         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1656
1657         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1658         atombios_lock_crtc(crtc, ATOM_DISABLE);
1659         radeon_crtc->in_mode_set = false;
1660 }
1661
1662 static void atombios_crtc_disable(struct drm_crtc *crtc)
1663 {
1664         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1665         struct drm_device *dev = crtc->dev;
1666         struct radeon_device *rdev = dev->dev_private;
1667         struct radeon_atom_ss ss;
1668
1669         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1670
1671         switch (radeon_crtc->pll_id) {
1672         case ATOM_PPLL1:
1673         case ATOM_PPLL2:
1674                 /* disable the ppll */
1675                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1676                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1677                 break;
1678         case ATOM_PPLL0:
1679                 /* disable the ppll */
1680                 if (ASIC_IS_DCE61(rdev))
1681                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1682                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1683                 break;
1684         default:
1685                 break;
1686         }
1687         radeon_crtc->pll_id = -1;
1688 }
1689
1690 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1691         .dpms = atombios_crtc_dpms,
1692         .mode_fixup = atombios_crtc_mode_fixup,
1693         .mode_set = atombios_crtc_mode_set,
1694         .mode_set_base = atombios_crtc_set_base,
1695         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1696         .prepare = atombios_crtc_prepare,
1697         .commit = atombios_crtc_commit,
1698         .load_lut = radeon_crtc_load_lut,
1699         .disable = atombios_crtc_disable,
1700 };
1701
1702 void radeon_atombios_init_crtc(struct drm_device *dev,
1703                                struct radeon_crtc *radeon_crtc)
1704 {
1705         struct radeon_device *rdev = dev->dev_private;
1706
1707         if (ASIC_IS_DCE4(rdev)) {
1708                 switch (radeon_crtc->crtc_id) {
1709                 case 0:
1710                 default:
1711                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1712                         break;
1713                 case 1:
1714                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1715                         break;
1716                 case 2:
1717                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1718                         break;
1719                 case 3:
1720                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1721                         break;
1722                 case 4:
1723                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1724                         break;
1725                 case 5:
1726                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1727                         break;
1728                 }
1729         } else {
1730                 if (radeon_crtc->crtc_id == 1)
1731                         radeon_crtc->crtc_offset =
1732                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1733                 else
1734                         radeon_crtc->crtc_offset = 0;
1735         }
1736         radeon_crtc->pll_id = -1;
1737         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1738 }