2 * Copyright 2013 Advanced Micro Devices, Inc.
3 * Copyright 2014 Rafał Miłecki
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/hdmi.h>
26 #include "radeon_asic.h"
27 #include "radeon_audio.h"
30 void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
31 u8 *sadb, int sad_count)
33 struct radeon_device *rdev = encoder->dev->dev_private;
36 /* program the speaker allocation */
37 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
38 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
40 tmp |= HDMI_CONNECTION;
42 tmp |= SPEAKER_ALLOCATION(sadb[0]);
44 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
45 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
48 void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
49 u8 *sadb, int sad_count)
51 struct radeon_device *rdev = encoder->dev->dev_private;
54 /* program the speaker allocation */
55 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
56 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
60 tmp |= SPEAKER_ALLOCATION(sadb[0]);
62 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
63 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
66 void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,
67 struct cea_sad *sads, int sad_count)
70 struct radeon_device *rdev = encoder->dev->dev_private;
71 static const u16 eld_reg_to_type[][2] = {
72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
78 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
79 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
80 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
81 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
82 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
83 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
86 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
89 int max_channels = -1;
92 for (j = 0; j < sad_count; j++) {
93 struct cea_sad *sad = &sads[j];
95 if (sad->format == eld_reg_to_type[i][1]) {
96 if (sad->channels > max_channels) {
97 value = MAX_CHANNELS(sad->channels) |
98 DESCRIPTOR_BYTE_2(sad->byte2) |
99 SUPPORTED_FREQUENCIES(sad->freq);
100 max_channels = sad->channels;
103 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
104 stereo_freqs |= sad->freq;
110 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
112 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
116 void dce3_2_audio_set_dto(struct radeon_device *rdev,
117 struct radeon_crtc *crtc, unsigned int clock)
119 struct radeon_encoder *radeon_encoder;
120 struct radeon_encoder_atom_dig *dig;
121 unsigned int max_ratio = clock / 24000;
129 radeon_encoder = to_radeon_encoder(crtc->encoder);
130 dig = radeon_encoder->enc_priv;
135 if (max_ratio >= 8) {
136 dto_phase = 192 * 1000;
138 } else if (max_ratio >= 4) {
139 dto_phase = 96 * 1000;
141 } else if (max_ratio >= 2) {
142 dto_phase = 48 * 1000;
145 dto_phase = 24 * 1000;
149 /* Express [24MHz / target pixel clock] as an exact rational
150 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
151 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
153 if (dig->dig_encoder == 0) {
154 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
155 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
156 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
157 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
158 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);
159 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
161 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
162 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
163 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);
164 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);
165 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);
166 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */
171 * update the info frames with the data from the current display mode
173 void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
175 struct drm_device *dev = encoder->dev;
176 struct radeon_device *rdev = dev->dev_private;
177 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
178 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
179 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
180 struct hdmi_avi_infoframe frame;
184 if (!dig || !dig->afmt)
187 /* Silent, r600_hdmi_enable will raise WARN for us */
188 if (!dig->afmt->enabled)
190 offset = dig->afmt->offset;
192 /* disable audio prior to setting up hw */
193 dig->afmt->pin = radeon_audio_get_pin(encoder);
194 radeon_audio_enable(rdev, dig->afmt->pin, 0);
196 radeon_audio_set_dto(encoder, mode->clock);
198 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
199 HDMI0_NULL_SEND); /* send null packets when required */
201 WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000);
203 if (ASIC_IS_DCE32(rdev)) {
204 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
205 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
206 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
207 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
208 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
209 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
211 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
212 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
213 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
214 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
215 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
218 if (ASIC_IS_DCE32(rdev)) {
219 radeon_audio_write_speaker_allocation(encoder);
220 radeon_audio_write_sad_regs(encoder);
223 WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
224 HDMI0_ACR_SOURCE | /* select SW CTS value - XXX verify that hw CTS works on all families */
225 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
227 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
228 HDMI0_NULL_SEND | /* send null packets when required */
229 HDMI0_GC_SEND | /* send general control packets */
230 HDMI0_GC_CONT); /* send general control packets every frame */
232 /* TODO: HDMI0_AUDIO_INFO_UPDATE */
233 WREG32(HDMI0_INFOFRAME_CONTROL0 + offset,
234 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */
235 HDMI0_AVI_INFO_CONT | /* send AVI info frames every frame/field */
236 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
237 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */
239 WREG32(HDMI0_INFOFRAME_CONTROL1 + offset,
240 HDMI0_AVI_INFO_LINE(2) | /* anything other than 0 */
241 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */
243 WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */
245 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
247 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
251 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
253 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
257 radeon_update_avi_infoframe(encoder, buffer, sizeof(buffer));
258 r600_hdmi_update_ACR(encoder, mode->clock);
260 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
261 WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);
262 WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);
263 WREG32(HDMI0_RAMP_CONTROL2 + offset, 0x00000001);
264 WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
266 r600_hdmi_audio_workaround(encoder);
268 /* enable audio after to setting up hw */
269 radeon_audio_enable(rdev, dig->afmt->pin, 0xf);