drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <drm/drmP.h>
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include <drm/radeon_drm.h>
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static const u32 crtc_offsets[6] =
  41 {
  42         EVERGREEN_CRTC0_REGISTER_OFFSET,
  43         EVERGREEN_CRTC1_REGISTER_OFFSET,
  44         EVERGREEN_CRTC2_REGISTER_OFFSET,
  45         EVERGREEN_CRTC3_REGISTER_OFFSET,
  46         EVERGREEN_CRTC4_REGISTER_OFFSET,
  47         EVERGREEN_CRTC5_REGISTER_OFFSET
  48 };
  49
  50 static void evergreen_gpu_init(struct radeon_device *rdev);
  51 void evergreen_fini(struct radeon_device *rdev);
  52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  53 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  54                                      int ring, u32 cp_int_cntl);
  55
  56 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  57                              unsigned *bankh, unsigned *mtaspect,
  58                              unsigned *tile_split)
  59 {
  60         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  61         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  62         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  63         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  64         switch (*bankw) {
  65         default:
  66         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  67         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  68         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  69         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  70         }
  71         switch (*bankh) {
  72         default:
  73         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  74         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  75         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  76         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  77         }
  78         switch (*mtaspect) {
  79         default:
  80         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  81         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  82         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  83         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  84         }
  85 }
  86
  87 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  88 {
  89         u16 ctl, v;
  90         int err;
  91
  92         err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
  93         if (err)
  94                 return;
  95
  96         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  97
  98         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  99          * to avoid hangs or perfomance issues
 100          */
 101         if ((v == 0) || (v == 6) || (v == 7)) {
 102                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
 103                 ctl |= (2 << 12);
 104                 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
 105         }
 106 }
 107
 108 /**
 109  * dce4_wait_for_vblank - vblank wait asic callback.
 110  *
 111  * @rdev: radeon_device pointer
 112  * @crtc: crtc to wait for vblank on
 113  *
 114  * Wait for vblank on the requested crtc (evergreen+).
 115  */
 116 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 117 {
 118         int i;
 119
 120         if (crtc >= rdev->num_crtc)
 121                 return;
 122
 123         if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
 124                 for (i = 0; i < rdev->usec_timeout; i++) {
 125                         if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
 126                                 break;
 127                         udelay(1);
 128                 }
 129                 for (i = 0; i < rdev->usec_timeout; i++) {
 130                         if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
 131                                 break;
 132                         udelay(1);
 133                 }
 134         }
 135 }
 136
 137 /**
 138  * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
 139  *
 140  * @rdev: radeon_device pointer
 141  * @crtc: crtc to prepare for pageflip on
 142  *
 143  * Pre-pageflip callback (evergreen+).
 144  * Enables the pageflip irq (vblank irq).
 145  */
 146 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 147 {
 148         /* enable the pflip int */
 149         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 150 }
 151
 152 /**
 153  * evergreen_post_page_flip - pos-pageflip callback.
 154  *
 155  * @rdev: radeon_device pointer
 156  * @crtc: crtc to cleanup pageflip on
 157  *
 158  * Post-pageflip callback (evergreen+).
 159  * Disables the pageflip irq (vblank irq).
 160  */
 161 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 162 {
 163         /* disable the pflip int */
 164         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 165 }
 166
 167 /**
 168  * evergreen_page_flip - pageflip callback.
 169  *
 170  * @rdev: radeon_device pointer
 171  * @crtc_id: crtc to cleanup pageflip on
 172  * @crtc_base: new address of the crtc (GPU MC address)
 173  *
 174  * Does the actual pageflip (evergreen+).
 175  * During vblank we take the crtc lock and wait for the update_pending
 176  * bit to go high, when it does, we release the lock, and allow the
 177  * double buffered update to take place.
 178  * Returns the current update pending status.
 179  */
 180 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 181 {
 182         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 183         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 184         int i;
 185
 186         /* Lock the graphics update lock */
 187         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 188         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 189
 190         /* update the scanout addresses */
 191         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 192                upper_32_bits(crtc_base));
 193         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 194                (u32)crtc_base);
 195
 196         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 197                upper_32_bits(crtc_base));
 198         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 199                (u32)crtc_base);
 200
 201         /* Wait for update_pending to go high. */
 202         for (i = 0; i < rdev->usec_timeout; i++) {
 203                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 204                         break;
 205                 udelay(1);
 206         }
 207         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 208
 209         /* Unlock the lock, so double-buffering can take place inside vblank */
 210         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 211         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 212
 213         /* Return current update_pending status: */
 214         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 215 }
 216
 217 /* get temperature in millidegrees */
 218 int evergreen_get_temp(struct radeon_device *rdev)
 219 {
 220         u32 temp, toffset;
 221         int actual_temp = 0;
 222
 223         if (rdev->family == CHIP_JUNIPER) {
 224                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 225                         TOFFSET_SHIFT;
 226                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 227                         TS0_ADC_DOUT_SHIFT;
 228
 229                 if (toffset & 0x100)
 230                         actual_temp = temp / 2 - (0x200 - toffset);
 231                 else
 232                         actual_temp = temp / 2 + toffset;
 233
 234                 actual_temp = actual_temp * 1000;
 235
 236         } else {
 237                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 238                         ASIC_T_SHIFT;
 239
 240                 if (temp & 0x400)
 241                         actual_temp = -256;
 242                 else if (temp & 0x200)
 243                         actual_temp = 255;
 244                 else if (temp & 0x100) {
 245                         actual_temp = temp & 0x1ff;
 246                         actual_temp |= ~0x1ff;
 247                 } else
 248                         actual_temp = temp & 0xff;
 249
 250                 actual_temp = (actual_temp * 1000) / 2;
 251         }
 252
 253         return actual_temp;
 254 }
 255
 256 int sumo_get_temp(struct radeon_device *rdev)
 257 {
 258         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 259         int actual_temp = temp - 49;
 260
 261         return actual_temp * 1000;
 262 }
 263
 264 /**
 265  * sumo_pm_init_profile - Initialize power profiles callback.
 266  *
 267  * @rdev: radeon_device pointer
 268  *
 269  * Initialize the power states used in profile mode
 270  * (sumo, trinity, SI).
 271  * Used for profile mode only.
 272  */
 273 void sumo_pm_init_profile(struct radeon_device *rdev)
 274 {
 275         int idx;
 276
 277         /* default */
 278         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 279         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 280         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 281         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 282
 283         /* low,mid sh/mh */
 284         if (rdev->flags & RADEON_IS_MOBILITY)
 285                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 286         else
 287                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 288
 289         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 290         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 291         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 292         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 293
 294         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 295         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 296         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 297         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 298
 299         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 300         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 301         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 303
 304         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 305         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 306         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 308
 309         /* high sh/mh */
 310         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 311         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 314         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 315                 rdev->pm.power_state[idx].num_clock_modes - 1;
 316
 317         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 318         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 319         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 320         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 321                 rdev->pm.power_state[idx].num_clock_modes - 1;
 322 }
 323
 324 /**
 325  * btc_pm_init_profile - Initialize power profiles callback.
 326  *
 327  * @rdev: radeon_device pointer
 328  *
 329  * Initialize the power states used in profile mode
 330  * (BTC, cayman).
 331  * Used for profile mode only.
 332  */
 333 void btc_pm_init_profile(struct radeon_device *rdev)
 334 {
 335         int idx;
 336
 337         /* default */
 338         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 339         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 340         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 341         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 342         /* starting with BTC, there is one state that is used for both
 343          * MH and SH.  Difference is that we always use the high clock index for
 344          * mclk.
 345          */
 346         if (rdev->flags & RADEON_IS_MOBILITY)
 347                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 348         else
 349                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 350         /* low sh */
 351         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 352         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 353         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 354         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 355         /* mid sh */
 356         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 357         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 358         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 359         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 360         /* high sh */
 361         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 362         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 363         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 364         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 365         /* low mh */
 366         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 367         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 368         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 369         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 370         /* mid mh */
 371         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 372         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 373         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 374         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 375         /* high mh */
 376         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 377         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 378         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 379         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 380 }
 381
 382 /**
 383  * evergreen_pm_misc - set additional pm hw parameters callback.
 384  *
 385  * @rdev: radeon_device pointer
 386  *
 387  * Set non-clock parameters associated with a power state
 388  * (voltage, etc.) (evergreen+).
 389  */
 390 void evergreen_pm_misc(struct radeon_device *rdev)
 391 {
 392         int req_ps_idx = rdev->pm.requested_power_state_index;
 393         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 394         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 395         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 396
 397         if (voltage->type == VOLTAGE_SW) {
 398                 /* 0xff01 is a flag rather then an actual voltage */
 399                 if (voltage->voltage == 0xff01)
 400                         return;
 401                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 402                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 403                         rdev->pm.current_vddc = voltage->voltage;
 404                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 405                 }
 406                 /* 0xff01 is a flag rather then an actual voltage */
 407                 if (voltage->vddci == 0xff01)
 408                         return;
 409                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 410                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 411                         rdev->pm.current_vddci = voltage->vddci;
 412                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 413                 }
 414         }
 415 }
 416
 417 /**
 418  * evergreen_pm_prepare - pre-power state change callback.
 419  *
 420  * @rdev: radeon_device pointer
 421  *
 422  * Prepare for a power state change (evergreen+).
 423  */
 424 void evergreen_pm_prepare(struct radeon_device *rdev)
 425 {
 426         struct drm_device *ddev = rdev->ddev;
 427         struct drm_crtc *crtc;
 428         struct radeon_crtc *radeon_crtc;
 429         u32 tmp;
 430
 431         /* disable any active CRTCs */
 432         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 433                 radeon_crtc = to_radeon_crtc(crtc);
 434                 if (radeon_crtc->enabled) {
 435                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 436                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 437                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 438                 }
 439         }
 440 }
 441
 442 /**
 443  * evergreen_pm_finish - post-power state change callback.
 444  *
 445  * @rdev: radeon_device pointer
 446  *
 447  * Clean up after a power state change (evergreen+).
 448  */
 449 void evergreen_pm_finish(struct radeon_device *rdev)
 450 {
 451         struct drm_device *ddev = rdev->ddev;
 452         struct drm_crtc *crtc;
 453         struct radeon_crtc *radeon_crtc;
 454         u32 tmp;
 455
 456         /* enable any active CRTCs */
 457         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 458                 radeon_crtc = to_radeon_crtc(crtc);
 459                 if (radeon_crtc->enabled) {
 460                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 461                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 462                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 463                 }
 464         }
 465 }
 466
 467 /**
 468  * evergreen_hpd_sense - hpd sense callback.
 469  *
 470  * @rdev: radeon_device pointer
 471  * @hpd: hpd (hotplug detect) pin
 472  *
 473  * Checks if a digital monitor is connected (evergreen+).
 474  * Returns true if connected, false if not connected.
 475  */
 476 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 477 {
 478         bool connected = false;
 479
 480         switch (hpd) {
 481         case RADEON_HPD_1:
 482                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 483                         connected = true;
 484                 break;
 485         case RADEON_HPD_2:
 486                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 487                         connected = true;
 488                 break;
 489         case RADEON_HPD_3:
 490                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 491                         connected = true;
 492                 break;
 493         case RADEON_HPD_4:
 494                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 495                         connected = true;
 496                 break;
 497         case RADEON_HPD_5:
 498                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 499                         connected = true;
 500                 break;
 501         case RADEON_HPD_6:
 502                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 503                         connected = true;
 504                         break;
 505         default:
 506                 break;
 507         }
 508
 509         return connected;
 510 }
 511
 512 /**
 513  * evergreen_hpd_set_polarity - hpd set polarity callback.
 514  *
 515  * @rdev: radeon_device pointer
 516  * @hpd: hpd (hotplug detect) pin
 517  *
 518  * Set the polarity of the hpd pin (evergreen+).
 519  */
 520 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 521                                 enum radeon_hpd_id hpd)
 522 {
 523         u32 tmp;
 524         bool connected = evergreen_hpd_sense(rdev, hpd);
 525
 526         switch (hpd) {
 527         case RADEON_HPD_1:
 528                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 529                 if (connected)
 530                         tmp &= ~DC_HPDx_INT_POLARITY;
 531                 else
 532                         tmp |= DC_HPDx_INT_POLARITY;
 533                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 534                 break;
 535         case RADEON_HPD_2:
 536                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 537                 if (connected)
 538                         tmp &= ~DC_HPDx_INT_POLARITY;
 539                 else
 540                         tmp |= DC_HPDx_INT_POLARITY;
 541                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 542                 break;
 543         case RADEON_HPD_3:
 544                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 545                 if (connected)
 546                         tmp &= ~DC_HPDx_INT_POLARITY;
 547                 else
 548                         tmp |= DC_HPDx_INT_POLARITY;
 549                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 550                 break;
 551         case RADEON_HPD_4:
 552                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 553                 if (connected)
 554                         tmp &= ~DC_HPDx_INT_POLARITY;
 555                 else
 556                         tmp |= DC_HPDx_INT_POLARITY;
 557                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 558                 break;
 559         case RADEON_HPD_5:
 560                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 561                 if (connected)
 562                         tmp &= ~DC_HPDx_INT_POLARITY;
 563                 else
 564                         tmp |= DC_HPDx_INT_POLARITY;
 565                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 566                         break;
 567         case RADEON_HPD_6:
 568                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 569                 if (connected)
 570                         tmp &= ~DC_HPDx_INT_POLARITY;
 571                 else
 572                         tmp |= DC_HPDx_INT_POLARITY;
 573                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 574                 break;
 575         default:
 576                 break;
 577         }
 578 }
 579
 580 /**
 581  * evergreen_hpd_init - hpd setup callback.
 582  *
 583  * @rdev: radeon_device pointer
 584  *
 585  * Setup the hpd pins used by the card (evergreen+).
 586  * Enable the pin, set the polarity, and enable the hpd interrupts.
 587  */
 588 void evergreen_hpd_init(struct radeon_device *rdev)
 589 {
 590         struct drm_device *dev = rdev->ddev;
 591         struct drm_connector *connector;
 592         unsigned enabled = 0;
 593         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 594                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 595
 596         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 597                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 598                 switch (radeon_connector->hpd.hpd) {
 599                 case RADEON_HPD_1:
 600                         WREG32(DC_HPD1_CONTROL, tmp);
 601                         break;
 602                 case RADEON_HPD_2:
 603                         WREG32(DC_HPD2_CONTROL, tmp);
 604                         break;
 605                 case RADEON_HPD_3:
 606                         WREG32(DC_HPD3_CONTROL, tmp);
 607                         break;
 608                 case RADEON_HPD_4:
 609                         WREG32(DC_HPD4_CONTROL, tmp);
 610                         break;
 611                 case RADEON_HPD_5:
 612                         WREG32(DC_HPD5_CONTROL, tmp);
 613                         break;
 614                 case RADEON_HPD_6:
 615                         WREG32(DC_HPD6_CONTROL, tmp);
 616                         break;
 617                 default:
 618                         break;
 619                 }
 620                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 621                 enabled |= 1 << radeon_connector->hpd.hpd;
 622         }
 623         radeon_irq_kms_enable_hpd(rdev, enabled);
 624 }
 625
 626 /**
 627  * evergreen_hpd_fini - hpd tear down callback.
 628  *
 629  * @rdev: radeon_device pointer
 630  *
 631  * Tear down the hpd pins used by the card (evergreen+).
 632  * Disable the hpd interrupts.
 633  */
 634 void evergreen_hpd_fini(struct radeon_device *rdev)
 635 {
 636         struct drm_device *dev = rdev->ddev;
 637         struct drm_connector *connector;
 638         unsigned disabled = 0;
 639
 640         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 641                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 642                 switch (radeon_connector->hpd.hpd) {
 643                 case RADEON_HPD_1:
 644                         WREG32(DC_HPD1_CONTROL, 0);
 645                         break;
 646                 case RADEON_HPD_2:
 647                         WREG32(DC_HPD2_CONTROL, 0);
 648                         break;
 649                 case RADEON_HPD_3:
 650                         WREG32(DC_HPD3_CONTROL, 0);
 651                         break;
 652                 case RADEON_HPD_4:
 653                         WREG32(DC_HPD4_CONTROL, 0);
 654                         break;
 655                 case RADEON_HPD_5:
 656                         WREG32(DC_HPD5_CONTROL, 0);
 657                         break;
 658                 case RADEON_HPD_6:
 659                         WREG32(DC_HPD6_CONTROL, 0);
 660                         break;
 661                 default:
 662                         break;
 663                 }
 664                 disabled |= 1 << radeon_connector->hpd.hpd;
 665         }
 666         radeon_irq_kms_disable_hpd(rdev, disabled);
 667 }
 668
 669 /* watermark setup */
 670
 671 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 672                                         struct radeon_crtc *radeon_crtc,
 673                                         struct drm_display_mode *mode,
 674                                         struct drm_display_mode *other_mode)
 675 {
 676         u32 tmp;
 677         /*
 678          * Line Buffer Setup
 679          * There are 3 line buffers, each one shared by 2 display controllers.
 680          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 681          * the display controllers.  The paritioning is done via one of four
 682          * preset allocations specified in bits 2:0:
 683          * first display controller
 684          *  0 - first half of lb (3840 * 2)
 685          *  1 - first 3/4 of lb (5760 * 2)
 686          *  2 - whole lb (7680 * 2), other crtc must be disabled
 687          *  3 - first 1/4 of lb (1920 * 2)
 688          * second display controller
 689          *  4 - second half of lb (3840 * 2)
 690          *  5 - second 3/4 of lb (5760 * 2)
 691          *  6 - whole lb (7680 * 2), other crtc must be disabled
 692          *  7 - last 1/4 of lb (1920 * 2)
 693          */
 694         /* this can get tricky if we have two large displays on a paired group
 695          * of crtcs.  Ideally for multiple large displays we'd assign them to
 696          * non-linked crtcs for maximum line buffer allocation.
 697          */
 698         if (radeon_crtc->base.enabled && mode) {
 699                 if (other_mode)
 700                         tmp = 0; /* 1/2 */
 701                 else
 702                         tmp = 2; /* whole */
 703         } else
 704                 tmp = 0;
 705
 706         /* second controller of the pair uses second half of the lb */
 707         if (radeon_crtc->crtc_id % 2)
 708                 tmp += 4;
 709         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 710
 711         if (radeon_crtc->base.enabled && mode) {
 712                 switch (tmp) {
 713                 case 0:
 714                 case 4:
 715                 default:
 716                         if (ASIC_IS_DCE5(rdev))
 717                                 return 4096 * 2;
 718                         else
 719                                 return 3840 * 2;
 720                 case 1:
 721                 case 5:
 722                         if (ASIC_IS_DCE5(rdev))
 723                                 return 6144 * 2;
 724                         else
 725                                 return 5760 * 2;
 726                 case 2:
 727                 case 6:
 728                         if (ASIC_IS_DCE5(rdev))
 729                                 return 8192 * 2;
 730                         else
 731                                 return 7680 * 2;
 732                 case 3:
 733                 case 7:
 734                         if (ASIC_IS_DCE5(rdev))
 735                                 return 2048 * 2;
 736                         else
 737                                 return 1920 * 2;
 738                 }
 739         }
 740
 741         /* controller not enabled, so no lb used */
 742         return 0;
 743 }
 744
 745 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 746 {
 747         u32 tmp = RREG32(MC_SHARED_CHMAP);
 748
 749         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 750         case 0:
 751         default:
 752                 return 1;
 753         case 1:
 754                 return 2;
 755         case 2:
 756                 return 4;
 757         case 3:
 758                 return 8;
 759         }
 760 }
 761
 762 struct evergreen_wm_params {
 763         u32 dram_channels; /* number of dram channels */
 764         u32 yclk;          /* bandwidth per dram data pin in kHz */
 765         u32 sclk;          /* engine clock in kHz */
 766         u32 disp_clk;      /* display clock in kHz */
 767         u32 src_width;     /* viewport width */
 768         u32 active_time;   /* active display time in ns */
 769         u32 blank_time;    /* blank time in ns */
 770         bool interlaced;    /* mode is interlaced */
 771         fixed20_12 vsc;    /* vertical scale ratio */
 772         u32 num_heads;     /* number of active crtcs */
 773         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 774         u32 lb_size;       /* line buffer allocated to pipe */
 775         u32 vtaps;         /* vertical scaler taps */
 776 };
 777
 778 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 779 {
 780         /* Calculate DRAM Bandwidth and the part allocated to display. */
 781         fixed20_12 dram_efficiency; /* 0.7 */
 782         fixed20_12 yclk, dram_channels, bandwidth;
 783         fixed20_12 a;
 784
 785         a.full = dfixed_const(1000);
 786         yclk.full = dfixed_const(wm->yclk);
 787         yclk.full = dfixed_div(yclk, a);
 788         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 789         a.full = dfixed_const(10);
 790         dram_efficiency.full = dfixed_const(7);
 791         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 792         bandwidth.full = dfixed_mul(dram_channels, yclk);
 793         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 794
 795         return dfixed_trunc(bandwidth);
 796 }
 797
 798 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 799 {
 800         /* Calculate DRAM Bandwidth and the part allocated to display. */
 801         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 802         fixed20_12 yclk, dram_channels, bandwidth;
 803         fixed20_12 a;
 804
 805         a.full = dfixed_const(1000);
 806         yclk.full = dfixed_const(wm->yclk);
 807         yclk.full = dfixed_div(yclk, a);
 808         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 809         a.full = dfixed_const(10);
 810         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 811         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 812         bandwidth.full = dfixed_mul(dram_channels, yclk);
 813         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 814
 815         return dfixed_trunc(bandwidth);
 816 }
 817
 818 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 819 {
 820         /* Calculate the display Data return Bandwidth */
 821         fixed20_12 return_efficiency; /* 0.8 */
 822         fixed20_12 sclk, bandwidth;
 823         fixed20_12 a;
 824
 825         a.full = dfixed_const(1000);
 826         sclk.full = dfixed_const(wm->sclk);
 827         sclk.full = dfixed_div(sclk, a);
 828         a.full = dfixed_const(10);
 829         return_efficiency.full = dfixed_const(8);
 830         return_efficiency.full = dfixed_div(return_efficiency, a);
 831         a.full = dfixed_const(32);
 832         bandwidth.full = dfixed_mul(a, sclk);
 833         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 834
 835         return dfixed_trunc(bandwidth);
 836 }
 837
 838 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 839 {
 840         /* Calculate the DMIF Request Bandwidth */
 841         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 842         fixed20_12 disp_clk, bandwidth;
 843         fixed20_12 a;
 844
 845         a.full = dfixed_const(1000);
 846         disp_clk.full = dfixed_const(wm->disp_clk);
 847         disp_clk.full = dfixed_div(disp_clk, a);
 848         a.full = dfixed_const(10);
 849         disp_clk_request_efficiency.full = dfixed_const(8);
 850         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 851         a.full = dfixed_const(32);
 852         bandwidth.full = dfixed_mul(a, disp_clk);
 853         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 854
 855         return dfixed_trunc(bandwidth);
 856 }
 857
 858 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 859 {
 860         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 861         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 862         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 863         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 864
 865         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 866 }
 867
 868 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 869 {
 870         /* Calculate the display mode Average Bandwidth
 871          * DisplayMode should contain the source and destination dimensions,
 872          * timing, etc.
 873          */
 874         fixed20_12 bpp;
 875         fixed20_12 line_time;
 876         fixed20_12 src_width;
 877         fixed20_12 bandwidth;
 878         fixed20_12 a;
 879
 880         a.full = dfixed_const(1000);
 881         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 882         line_time.full = dfixed_div(line_time, a);
 883         bpp.full = dfixed_const(wm->bytes_per_pixel);
 884         src_width.full = dfixed_const(wm->src_width);
 885         bandwidth.full = dfixed_mul(src_width, bpp);
 886         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 887         bandwidth.full = dfixed_div(bandwidth, line_time);
 888
 889         return dfixed_trunc(bandwidth);
 890 }
 891
 892 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 893 {
 894         /* First calcualte the latency in ns */
 895         u32 mc_latency = 2000; /* 2000 ns. */
 896         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 897         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 898         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 899         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 900         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 901                 (wm->num_heads * cursor_line_pair_return_time);
 902         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 903         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 904         fixed20_12 a, b, c;
 905
 906         if (wm->num_heads == 0)
 907                 return 0;
 908
 909         a.full = dfixed_const(2);
 910         b.full = dfixed_const(1);
 911         if ((wm->vsc.full > a.full) ||
 912             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 913             (wm->vtaps >= 5) ||
 914             ((wm->vsc.full >= a.full) && wm->interlaced))
 915                 max_src_lines_per_dst_line = 4;
 916         else
 917                 max_src_lines_per_dst_line = 2;
 918
 919         a.full = dfixed_const(available_bandwidth);
 920         b.full = dfixed_const(wm->num_heads);
 921         a.full = dfixed_div(a, b);
 922
 923         b.full = dfixed_const(1000);
 924         c.full = dfixed_const(wm->disp_clk);
 925         b.full = dfixed_div(c, b);
 926         c.full = dfixed_const(wm->bytes_per_pixel);
 927         b.full = dfixed_mul(b, c);
 928
 929         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 930
 931         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 932         b.full = dfixed_const(1000);
 933         c.full = dfixed_const(lb_fill_bw);
 934         b.full = dfixed_div(c, b);
 935         a.full = dfixed_div(a, b);
 936         line_fill_time = dfixed_trunc(a);
 937
 938         if (line_fill_time < wm->active_time)
 939                 return latency;
 940         else
 941                 return latency + (line_fill_time - wm->active_time);
 942
 943 }
 944
 945 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 946 {
 947         if (evergreen_average_bandwidth(wm) <=
 948             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 949                 return true;
 950         else
 951                 return false;
 952 };
 953
 954 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 955 {
 956         if (evergreen_average_bandwidth(wm) <=
 957             (evergreen_available_bandwidth(wm) / wm->num_heads))
 958                 return true;
 959         else
 960                 return false;
 961 };
 962
 963 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 964 {
 965         u32 lb_partitions = wm->lb_size / wm->src_width;
 966         u32 line_time = wm->active_time + wm->blank_time;
 967         u32 latency_tolerant_lines;
 968         u32 latency_hiding;
 969         fixed20_12 a;
 970
 971         a.full = dfixed_const(1);
 972         if (wm->vsc.full > a.full)
 973                 latency_tolerant_lines = 1;
 974         else {
 975                 if (lb_partitions <= (wm->vtaps + 1))
 976                         latency_tolerant_lines = 1;
 977                 else
 978                         latency_tolerant_lines = 2;
 979         }
 980
 981         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 982
 983         if (evergreen_latency_watermark(wm) <= latency_hiding)
 984                 return true;
 985         else
 986                 return false;
 987 }
 988
 989 static void evergreen_program_watermarks(struct radeon_device *rdev,
 990                                          struct radeon_crtc *radeon_crtc,
 991                                          u32 lb_size, u32 num_heads)
 992 {
 993         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 994         struct evergreen_wm_params wm;
 995         u32 pixel_period;
 996         u32 line_time = 0;
 997         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 998         u32 priority_a_mark = 0, priority_b_mark = 0;
 999         u32 priority_a_cnt = PRIORITY_OFF;
1000         u32 priority_b_cnt = PRIORITY_OFF;
1001         u32 pipe_offset = radeon_crtc->crtc_id * 16;
1002         u32 tmp, arb_control3;
1003         fixed20_12 a, b, c;
1004
1005         if (radeon_crtc->base.enabled && num_heads && mode) {
1006                 pixel_period = 1000000 / (u32)mode->clock;
1007                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1008                 priority_a_cnt = 0;
1009                 priority_b_cnt = 0;
1010
1011                 wm.yclk = rdev->pm.current_mclk * 10;
1012                 wm.sclk = rdev->pm.current_sclk * 10;
1013                 wm.disp_clk = mode->clock;
1014                 wm.src_width = mode->crtc_hdisplay;
1015                 wm.active_time = mode->crtc_hdisplay * pixel_period;
1016                 wm.blank_time = line_time - wm.active_time;
1017                 wm.interlaced = false;
1018                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1019                         wm.interlaced = true;
1020                 wm.vsc = radeon_crtc->vsc;
1021                 wm.vtaps = 1;
1022                 if (radeon_crtc->rmx_type != RMX_OFF)
1023                         wm.vtaps = 2;
1024                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1025                 wm.lb_size = lb_size;
1026                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1027                 wm.num_heads = num_heads;
1028
1029                 /* set for high clocks */
1030                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1031                 /* set for low clocks */
1032                 /* wm.yclk = low clk; wm.sclk = low clk */
1033                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1034
1035                 /* possibly force display priority to high */
1036                 /* should really do this at mode validation time... */
1037                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1038                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1039                     !evergreen_check_latency_hiding(&wm) ||
1040                     (rdev->disp_priority == 2)) {
1041                         DRM_DEBUG_KMS("force priority to high\n");
1042                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
1043                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
1044                 }
1045
1046                 a.full = dfixed_const(1000);
1047                 b.full = dfixed_const(mode->clock);
1048                 b.full = dfixed_div(b, a);
1049                 c.full = dfixed_const(latency_watermark_a);
1050                 c.full = dfixed_mul(c, b);
1051                 c.full = dfixed_mul(c, radeon_crtc->hsc);
1052                 c.full = dfixed_div(c, a);
1053                 a.full = dfixed_const(16);
1054                 c.full = dfixed_div(c, a);
1055                 priority_a_mark = dfixed_trunc(c);
1056                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1057
1058                 a.full = dfixed_const(1000);
1059                 b.full = dfixed_const(mode->clock);
1060                 b.full = dfixed_div(b, a);
1061                 c.full = dfixed_const(latency_watermark_b);
1062                 c.full = dfixed_mul(c, b);
1063                 c.full = dfixed_mul(c, radeon_crtc->hsc);
1064                 c.full = dfixed_div(c, a);
1065                 a.full = dfixed_const(16);
1066                 c.full = dfixed_div(c, a);
1067                 priority_b_mark = dfixed_trunc(c);
1068                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1069         }
1070
1071         /* select wm A */
1072         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1073         tmp = arb_control3;
1074         tmp &= ~LATENCY_WATERMARK_MASK(3);
1075         tmp |= LATENCY_WATERMARK_MASK(1);
1076         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1077         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1078                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1079                 LATENCY_HIGH_WATERMARK(line_time)));
1080         /* select wm B */
1081         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1082         tmp &= ~LATENCY_WATERMARK_MASK(3);
1083         tmp |= LATENCY_WATERMARK_MASK(2);
1084         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1085         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1086                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1087                 LATENCY_HIGH_WATERMARK(line_time)));
1088         /* restore original selection */
1089         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1090
1091         /* write the priority marks */
1092         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1093         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1094
1095 }
1096
1097 /**
1098  * evergreen_bandwidth_update - update display watermarks callback.
1099  *
1100  * @rdev: radeon_device pointer
1101  *
1102  * Update the display watermarks based on the requested mode(s)
1103  * (evergreen+).
1104  */
1105 void evergreen_bandwidth_update(struct radeon_device *rdev)
1106 {
1107         struct drm_display_mode *mode0 = NULL;
1108         struct drm_display_mode *mode1 = NULL;
1109         u32 num_heads = 0, lb_size;
1110         int i;
1111
1112         radeon_update_display_priority(rdev);
1113
1114         for (i = 0; i < rdev->num_crtc; i++) {
1115                 if (rdev->mode_info.crtcs[i]->base.enabled)
1116                         num_heads++;
1117         }
1118         for (i = 0; i < rdev->num_crtc; i += 2) {
1119                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1120                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1121                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1122                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1123                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1124                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1125         }
1126 }
1127
1128 /**
1129  * evergreen_mc_wait_for_idle - wait for MC idle callback.
1130  *
1131  * @rdev: radeon_device pointer
1132  *
1133  * Wait for the MC (memory controller) to be idle.
1134  * (evergreen+).
1135  * Returns 0 if the MC is idle, -1 if not.
1136  */
1137 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1138 {
1139         unsigned i;
1140         u32 tmp;
1141
1142         for (i = 0; i < rdev->usec_timeout; i++) {
1143                 /* read MC_STATUS */
1144                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1145                 if (!tmp)
1146                         return 0;
1147                 udelay(1);
1148         }
1149         return -1;
1150 }
1151
1152 /*
1153  * GART
1154  */
1155 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1156 {
1157         unsigned i;
1158         u32 tmp;
1159
1160         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1161
1162         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1163         for (i = 0; i < rdev->usec_timeout; i++) {
1164                 /* read MC_STATUS */
1165                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1166                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1167                 if (tmp == 2) {
1168                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1169                         return;
1170                 }
1171                 if (tmp) {
1172                         return;
1173                 }
1174                 udelay(1);
1175         }
1176 }
1177
1178 static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1179 {
1180         u32 tmp;
1181         int r;
1182
1183         if (rdev->gart.robj == NULL) {
1184                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1185                 return -EINVAL;
1186         }
1187         r = radeon_gart_table_vram_pin(rdev);
1188         if (r)
1189                 return r;
1190         radeon_gart_restore(rdev);
1191         /* Setup L2 cache */
1192         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1193                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1194                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1195         WREG32(VM_L2_CNTL2, 0);
1196         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1197         /* Setup TLB control */
1198         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1199                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1200                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1201                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1202         if (rdev->flags & RADEON_IS_IGP) {
1203                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1204                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1205                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1206         } else {
1207                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1208                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1209                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1210                 if ((rdev->family == CHIP_JUNIPER) ||
1211                     (rdev->family == CHIP_CYPRESS) ||
1212                     (rdev->family == CHIP_HEMLOCK) ||
1213                     (rdev->family == CHIP_BARTS))
1214                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1215         }
1216         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1217         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1218         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1219         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1220         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1221         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1222         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1223         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1224                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1225         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1226                         (u32)(rdev->dummy_page.addr >> 12));
1227         WREG32(VM_CONTEXT1_CNTL, 0);
1228
1229         evergreen_pcie_gart_tlb_flush(rdev);
1230         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1231                  (unsigned)(rdev->mc.gtt_size >> 20),
1232                  (unsigned long long)rdev->gart.table_addr);
1233         rdev->gart.ready = true;
1234         return 0;
1235 }
1236
1237 static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1238 {
1239         u32 tmp;
1240
1241         /* Disable all tables */
1242         WREG32(VM_CONTEXT0_CNTL, 0);
1243         WREG32(VM_CONTEXT1_CNTL, 0);
1244
1245         /* Setup L2 cache */
1246         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1247                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1248         WREG32(VM_L2_CNTL2, 0);
1249         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1250         /* Setup TLB control */
1251         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1252         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1253         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1254         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1255         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1256         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1257         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1258         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1259         radeon_gart_table_vram_unpin(rdev);
1260 }
1261
1262 static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1263 {
1264         evergreen_pcie_gart_disable(rdev);
1265         radeon_gart_table_vram_free(rdev);
1266         radeon_gart_fini(rdev);
1267 }
1268
1269
1270 static void evergreen_agp_enable(struct radeon_device *rdev)
1271 {
1272         u32 tmp;
1273
1274         /* Setup L2 cache */
1275         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1276                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1277                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1278         WREG32(VM_L2_CNTL2, 0);
1279         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1280         /* Setup TLB control */
1281         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1282                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1283                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1284                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1285         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1286         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1287         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1288         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1289         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1290         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1291         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1292         WREG32(VM_CONTEXT0_CNTL, 0);
1293         WREG32(VM_CONTEXT1_CNTL, 0);
1294 }
1295
1296 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1297 {
1298         u32 crtc_enabled, tmp, frame_count, blackout;
1299         int i, j;
1300
1301         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1302         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1303
1304         /* disable VGA render */
1305         WREG32(VGA_RENDER_CONTROL, 0);
1306         /* blank the display controllers */
1307         for (i = 0; i < rdev->num_crtc; i++) {
1308                 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1309                 if (crtc_enabled) {
1310                         save->crtc_enabled[i] = true;
1311                         if (ASIC_IS_DCE6(rdev)) {
1312                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1313                                 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1314                                         radeon_wait_for_vblank(rdev, i);
1315                                         tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1316                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1317                                         WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1318                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1319                                 }
1320                         } else {
1321                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1322                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1323                                         radeon_wait_for_vblank(rdev, i);
1324                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1325                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1326                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1327                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1328                                 }
1329                         }
1330                         /* wait for the next frame */
1331                         frame_count = radeon_get_vblank_counter(rdev, i);
1332                         for (j = 0; j < rdev->usec_timeout; j++) {
1333                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1334                                         break;
1335                                 udelay(1);
1336                         }
1337                 } else {
1338                         save->crtc_enabled[i] = false;
1339                 }
1340         }
1341
1342         radeon_mc_wait_for_idle(rdev);
1343
1344         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1345         if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1346                 /* Block CPU access */
1347                 WREG32(BIF_FB_EN, 0);
1348                 /* blackout the MC */
1349                 blackout &= ~BLACKOUT_MODE_MASK;
1350                 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1351         }
1352         /* wait for the MC to settle */
1353         udelay(100);
1354 }
1355
1356 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1357 {
1358         u32 tmp, frame_count;
1359         int i, j;
1360
1361         /* update crtc base addresses */
1362         for (i = 0; i < rdev->num_crtc; i++) {
1363                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1364                        upper_32_bits(rdev->mc.vram_start));
1365                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1366                        upper_32_bits(rdev->mc.vram_start));
1367                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1368                        (u32)rdev->mc.vram_start);
1369                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1370                        (u32)rdev->mc.vram_start);
1371         }
1372         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1373         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1374
1375         /* unblackout the MC */
1376         tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1377         tmp &= ~BLACKOUT_MODE_MASK;
1378         WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1379         /* allow CPU access */
1380         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1381
1382         for (i = 0; i < rdev->num_crtc; i++) {
1383                 if (save->crtc_enabled[i]) {
1384                         if (ASIC_IS_DCE6(rdev)) {
1385                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1386                                 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1387                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1388                                 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1389                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1390                         } else {
1391                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1392                                 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1393                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1394                                 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1395                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1396                         }
1397                         /* wait for the next frame */
1398                         frame_count = radeon_get_vblank_counter(rdev, i);
1399                         for (j = 0; j < rdev->usec_timeout; j++) {
1400                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1401                                         break;
1402                                 udelay(1);
1403                         }
1404                 }
1405         }
1406         /* Unlock vga access */
1407         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1408         mdelay(1);
1409         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1410 }
1411
1412 void evergreen_mc_program(struct radeon_device *rdev)
1413 {
1414         struct evergreen_mc_save save;
1415         u32 tmp;
1416         int i, j;
1417
1418         /* Initialize HDP */
1419         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1420                 WREG32((0x2c14 + j), 0x00000000);
1421                 WREG32((0x2c18 + j), 0x00000000);
1422                 WREG32((0x2c1c + j), 0x00000000);
1423                 WREG32((0x2c20 + j), 0x00000000);
1424                 WREG32((0x2c24 + j), 0x00000000);
1425         }
1426         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1427
1428         evergreen_mc_stop(rdev, &save);
1429         if (evergreen_mc_wait_for_idle(rdev)) {
1430                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1431         }
1432         /* Lockout access through VGA aperture*/
1433         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1434         /* Update configuration */
1435         if (rdev->flags & RADEON_IS_AGP) {
1436                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1437                         /* VRAM before AGP */
1438                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1439                                 rdev->mc.vram_start >> 12);
1440                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1441                                 rdev->mc.gtt_end >> 12);
1442                 } else {
1443                         /* VRAM after AGP */
1444                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1445                                 rdev->mc.gtt_start >> 12);
1446                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1447                                 rdev->mc.vram_end >> 12);
1448                 }
1449         } else {
1450                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1451                         rdev->mc.vram_start >> 12);
1452                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1453                         rdev->mc.vram_end >> 12);
1454         }
1455         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1456         /* llano/ontario only */
1457         if ((rdev->family == CHIP_PALM) ||
1458             (rdev->family == CHIP_SUMO) ||
1459             (rdev->family == CHIP_SUMO2)) {
1460                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1461                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1462                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1463                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1464         }
1465         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1466         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1467         WREG32(MC_VM_FB_LOCATION, tmp);
1468         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1469         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1470         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1471         if (rdev->flags & RADEON_IS_AGP) {
1472                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1473                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1474                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1475         } else {
1476                 WREG32(MC_VM_AGP_BASE, 0);
1477                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1478                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1479         }
1480         if (evergreen_mc_wait_for_idle(rdev)) {
1481                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1482         }
1483         evergreen_mc_resume(rdev, &save);
1484         /* we need to own VRAM, so turn off the VGA renderer here
1485          * to stop it overwriting our objects */
1486         rv515_vga_render_disable(rdev);
1487 }
1488
1489 /*
1490  * CP.
1491  */
1492 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1493 {
1494         struct radeon_ring *ring = &rdev->ring[ib->ring];
1495         u32 next_rptr;
1496
1497         /* set to DX10/11 mode */
1498         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1499         radeon_ring_write(ring, 1);
1500
1501         if (ring->rptr_save_reg) {
1502                 next_rptr = ring->wptr + 3 + 4;
1503                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1504                 radeon_ring_write(ring, ((ring->rptr_save_reg -
1505                                           PACKET3_SET_CONFIG_REG_START) >> 2));
1506                 radeon_ring_write(ring, next_rptr);
1507         } else if (rdev->wb.enabled) {
1508                 next_rptr = ring->wptr + 5 + 4;
1509                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1510                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1511                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1512                 radeon_ring_write(ring, next_rptr);
1513                 radeon_ring_write(ring, 0);
1514         }
1515
1516         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1517         radeon_ring_write(ring,
1518 #ifdef __BIG_ENDIAN
1519                           (2 << 0) |
1520 #endif
1521                           (ib->gpu_addr & 0xFFFFFFFC));
1522         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1523         radeon_ring_write(ring, ib->length_dw);
1524 }
1525
1526
1527 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1528 {
1529         const __be32 *fw_data;
1530         int i;
1531
1532         if (!rdev->me_fw || !rdev->pfp_fw)
1533                 return -EINVAL;
1534
1535         r700_cp_stop(rdev);
1536         WREG32(CP_RB_CNTL,
1537 #ifdef __BIG_ENDIAN
1538                BUF_SWAP_32BIT |
1539 #endif
1540                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1541
1542         fw_data = (const __be32 *)rdev->pfp_fw->data;
1543         WREG32(CP_PFP_UCODE_ADDR, 0);
1544         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1545                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1546         WREG32(CP_PFP_UCODE_ADDR, 0);
1547
1548         fw_data = (const __be32 *)rdev->me_fw->data;
1549         WREG32(CP_ME_RAM_WADDR, 0);
1550         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1551                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1552
1553         WREG32(CP_PFP_UCODE_ADDR, 0);
1554         WREG32(CP_ME_RAM_WADDR, 0);
1555         WREG32(CP_ME_RAM_RADDR, 0);
1556         return 0;
1557 }
1558
1559 static int evergreen_cp_start(struct radeon_device *rdev)
1560 {
1561         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1562         int r, i;
1563         uint32_t cp_me;
1564
1565         r = radeon_ring_lock(rdev, ring, 7);
1566         if (r) {
1567                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1568                 return r;
1569         }
1570         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1571         radeon_ring_write(ring, 0x1);
1572         radeon_ring_write(ring, 0x0);
1573         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1574         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1575         radeon_ring_write(ring, 0);
1576         radeon_ring_write(ring, 0);
1577         radeon_ring_unlock_commit(rdev, ring);
1578
1579         cp_me = 0xff;
1580         WREG32(CP_ME_CNTL, cp_me);
1581
1582         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1583         if (r) {
1584                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1585                 return r;
1586         }
1587
1588         /* setup clear context state */
1589         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1590         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1591
1592         for (i = 0; i < evergreen_default_size; i++)
1593                 radeon_ring_write(ring, evergreen_default_state[i]);
1594
1595         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1596         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1597
1598         /* set clear context state */
1599         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1600         radeon_ring_write(ring, 0);
1601
1602         /* SQ_VTX_BASE_VTX_LOC */
1603         radeon_ring_write(ring, 0xc0026f00);
1604         radeon_ring_write(ring, 0x00000000);
1605         radeon_ring_write(ring, 0x00000000);
1606         radeon_ring_write(ring, 0x00000000);
1607
1608         /* Clear consts */
1609         radeon_ring_write(ring, 0xc0036f00);
1610         radeon_ring_write(ring, 0x00000bc4);
1611         radeon_ring_write(ring, 0xffffffff);
1612         radeon_ring_write(ring, 0xffffffff);
1613         radeon_ring_write(ring, 0xffffffff);
1614
1615         radeon_ring_write(ring, 0xc0026900);
1616         radeon_ring_write(ring, 0x00000316);
1617         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1618         radeon_ring_write(ring, 0x00000010); /*  */
1619
1620         radeon_ring_unlock_commit(rdev, ring);
1621
1622         return 0;
1623 }
1624
1625 static int evergreen_cp_resume(struct radeon_device *rdev)
1626 {
1627         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1628         u32 tmp;
1629         u32 rb_bufsz;
1630         int r;
1631
1632         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1633         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1634                                  SOFT_RESET_PA |
1635                                  SOFT_RESET_SH |
1636                                  SOFT_RESET_VGT |
1637                                  SOFT_RESET_SPI |
1638                                  SOFT_RESET_SX));
1639         RREG32(GRBM_SOFT_RESET);
1640         mdelay(15);
1641         WREG32(GRBM_SOFT_RESET, 0);
1642         RREG32(GRBM_SOFT_RESET);
1643
1644         /* Set ring buffer size */
1645         rb_bufsz = drm_order(ring->ring_size / 8);
1646         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1647 #ifdef __BIG_ENDIAN
1648         tmp |= BUF_SWAP_32BIT;
1649 #endif
1650         WREG32(CP_RB_CNTL, tmp);
1651         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1652         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1653
1654         /* Set the write pointer delay */
1655         WREG32(CP_RB_WPTR_DELAY, 0);
1656
1657         /* Initialize the ring buffer's read and write pointers */
1658         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1659         WREG32(CP_RB_RPTR_WR, 0);
1660         ring->wptr = 0;
1661         WREG32(CP_RB_WPTR, ring->wptr);
1662
1663         /* set the wb address whether it's enabled or not */
1664         WREG32(CP_RB_RPTR_ADDR,
1665                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1666         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1667         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1668
1669         if (rdev->wb.enabled)
1670                 WREG32(SCRATCH_UMSK, 0xff);
1671         else {
1672                 tmp |= RB_NO_UPDATE;
1673                 WREG32(SCRATCH_UMSK, 0);
1674         }
1675
1676         mdelay(1);
1677         WREG32(CP_RB_CNTL, tmp);
1678
1679         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1680         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1681
1682         ring->rptr = RREG32(CP_RB_RPTR);
1683
1684         evergreen_cp_start(rdev);
1685         ring->ready = true;
1686         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1687         if (r) {
1688                 ring->ready = false;
1689                 return r;
1690         }
1691         return 0;
1692 }
1693
1694 /*
1695  * Core functions
1696  */
1697 static void evergreen_gpu_init(struct radeon_device *rdev)
1698 {
1699         u32 gb_addr_config;
1700         u32 mc_shared_chmap, mc_arb_ramcfg;
1701         u32 sx_debug_1;
1702         u32 smx_dc_ctl0;
1703         u32 sq_config;
1704         u32 sq_lds_resource_mgmt;
1705         u32 sq_gpr_resource_mgmt_1;
1706         u32 sq_gpr_resource_mgmt_2;
1707         u32 sq_gpr_resource_mgmt_3;
1708         u32 sq_thread_resource_mgmt;
1709         u32 sq_thread_resource_mgmt_2;
1710         u32 sq_stack_resource_mgmt_1;
1711         u32 sq_stack_resource_mgmt_2;
1712         u32 sq_stack_resource_mgmt_3;
1713         u32 vgt_cache_invalidation;
1714         u32 hdp_host_path_cntl, tmp;
1715         u32 disabled_rb_mask;
1716         int i, j, num_shader_engines, ps_thread_count;
1717
1718         switch (rdev->family) {
1719         case CHIP_CYPRESS:
1720         case CHIP_HEMLOCK:
1721                 rdev->config.evergreen.num_ses = 2;
1722                 rdev->config.evergreen.max_pipes = 4;
1723                 rdev->config.evergreen.max_tile_pipes = 8;
1724                 rdev->config.evergreen.max_simds = 10;
1725                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1726                 rdev->config.evergreen.max_gprs = 256;
1727                 rdev->config.evergreen.max_threads = 248;
1728                 rdev->config.evergreen.max_gs_threads = 32;
1729                 rdev->config.evergreen.max_stack_entries = 512;
1730                 rdev->config.evergreen.sx_num_of_sets = 4;
1731                 rdev->config.evergreen.sx_max_export_size = 256;
1732                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1733                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1734                 rdev->config.evergreen.max_hw_contexts = 8;
1735                 rdev->config.evergreen.sq_num_cf_insts = 2;
1736
1737                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1738                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1739                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1740                 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1741                 break;
1742         case CHIP_JUNIPER:
1743                 rdev->config.evergreen.num_ses = 1;
1744                 rdev->config.evergreen.max_pipes = 4;
1745                 rdev->config.evergreen.max_tile_pipes = 4;
1746                 rdev->config.evergreen.max_simds = 10;
1747                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1748                 rdev->config.evergreen.max_gprs = 256;
1749                 rdev->config.evergreen.max_threads = 248;
1750                 rdev->config.evergreen.max_gs_threads = 32;
1751                 rdev->config.evergreen.max_stack_entries = 512;
1752                 rdev->config.evergreen.sx_num_of_sets = 4;
1753                 rdev->config.evergreen.sx_max_export_size = 256;
1754                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1755                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1756                 rdev->config.evergreen.max_hw_contexts = 8;
1757                 rdev->config.evergreen.sq_num_cf_insts = 2;
1758
1759                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1760                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1761                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1762                 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1763                 break;
1764         case CHIP_REDWOOD:
1765                 rdev->config.evergreen.num_ses = 1;
1766                 rdev->config.evergreen.max_pipes = 4;
1767                 rdev->config.evergreen.max_tile_pipes = 4;
1768                 rdev->config.evergreen.max_simds = 5;
1769                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1770                 rdev->config.evergreen.max_gprs = 256;
1771                 rdev->config.evergreen.max_threads = 248;
1772                 rdev->config.evergreen.max_gs_threads = 32;
1773                 rdev->config.evergreen.max_stack_entries = 256;
1774                 rdev->config.evergreen.sx_num_of_sets = 4;
1775                 rdev->config.evergreen.sx_max_export_size = 256;
1776                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1777                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1778                 rdev->config.evergreen.max_hw_contexts = 8;
1779                 rdev->config.evergreen.sq_num_cf_insts = 2;
1780
1781                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1782                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1783                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1784                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1785                 break;
1786         case CHIP_CEDAR:
1787         default:
1788                 rdev->config.evergreen.num_ses = 1;
1789                 rdev->config.evergreen.max_pipes = 2;
1790                 rdev->config.evergreen.max_tile_pipes = 2;
1791                 rdev->config.evergreen.max_simds = 2;
1792                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1793                 rdev->config.evergreen.max_gprs = 256;
1794                 rdev->config.evergreen.max_threads = 192;
1795                 rdev->config.evergreen.max_gs_threads = 16;
1796                 rdev->config.evergreen.max_stack_entries = 256;
1797                 rdev->config.evergreen.sx_num_of_sets = 4;
1798                 rdev->config.evergreen.sx_max_export_size = 128;
1799                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1800                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1801                 rdev->config.evergreen.max_hw_contexts = 4;
1802                 rdev->config.evergreen.sq_num_cf_insts = 1;
1803
1804                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1805                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1806                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1807                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1808                 break;
1809         case CHIP_PALM:
1810                 rdev->config.evergreen.num_ses = 1;
1811                 rdev->config.evergreen.max_pipes = 2;
1812                 rdev->config.evergreen.max_tile_pipes = 2;
1813                 rdev->config.evergreen.max_simds = 2;
1814                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1815                 rdev->config.evergreen.max_gprs = 256;
1816                 rdev->config.evergreen.max_threads = 192;
1817                 rdev->config.evergreen.max_gs_threads = 16;
1818                 rdev->config.evergreen.max_stack_entries = 256;
1819                 rdev->config.evergreen.sx_num_of_sets = 4;
1820                 rdev->config.evergreen.sx_max_export_size = 128;
1821                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1822                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1823                 rdev->config.evergreen.max_hw_contexts = 4;
1824                 rdev->config.evergreen.sq_num_cf_insts = 1;
1825
1826                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1827                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1828                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1829                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1830                 break;
1831         case CHIP_SUMO:
1832                 rdev->config.evergreen.num_ses = 1;
1833                 rdev->config.evergreen.max_pipes = 4;
1834                 rdev->config.evergreen.max_tile_pipes = 4;
1835                 if (rdev->pdev->device == 0x9648)
1836                         rdev->config.evergreen.max_simds = 3;
1837                 else if ((rdev->pdev->device == 0x9647) ||
1838                          (rdev->pdev->device == 0x964a))
1839                         rdev->config.evergreen.max_simds = 4;
1840                 else
1841                         rdev->config.evergreen.max_simds = 5;
1842                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1843                 rdev->config.evergreen.max_gprs = 256;
1844                 rdev->config.evergreen.max_threads = 248;
1845                 rdev->config.evergreen.max_gs_threads = 32;
1846                 rdev->config.evergreen.max_stack_entries = 256;
1847                 rdev->config.evergreen.sx_num_of_sets = 4;
1848                 rdev->config.evergreen.sx_max_export_size = 256;
1849                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1850                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1851                 rdev->config.evergreen.max_hw_contexts = 8;
1852                 rdev->config.evergreen.sq_num_cf_insts = 2;
1853
1854                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1855                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1856                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1857                 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
1858                 break;
1859         case CHIP_SUMO2:
1860                 rdev->config.evergreen.num_ses = 1;
1861                 rdev->config.evergreen.max_pipes = 4;
1862                 rdev->config.evergreen.max_tile_pipes = 4;
1863                 rdev->config.evergreen.max_simds = 2;
1864                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1865                 rdev->config.evergreen.max_gprs = 256;
1866                 rdev->config.evergreen.max_threads = 248;
1867                 rdev->config.evergreen.max_gs_threads = 32;
1868                 rdev->config.evergreen.max_stack_entries = 512;
1869                 rdev->config.evergreen.sx_num_of_sets = 4;
1870                 rdev->config.evergreen.sx_max_export_size = 256;
1871                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1872                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1873                 rdev->config.evergreen.max_hw_contexts = 8;
1874                 rdev->config.evergreen.sq_num_cf_insts = 2;
1875
1876                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1877                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1878                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1879                 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
1880                 break;
1881         case CHIP_BARTS:
1882                 rdev->config.evergreen.num_ses = 2;
1883                 rdev->config.evergreen.max_pipes = 4;
1884                 rdev->config.evergreen.max_tile_pipes = 8;
1885                 rdev->config.evergreen.max_simds = 7;
1886                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1887                 rdev->config.evergreen.max_gprs = 256;
1888                 rdev->config.evergreen.max_threads = 248;
1889                 rdev->config.evergreen.max_gs_threads = 32;
1890                 rdev->config.evergreen.max_stack_entries = 512;
1891                 rdev->config.evergreen.sx_num_of_sets = 4;
1892                 rdev->config.evergreen.sx_max_export_size = 256;
1893                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1894                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1895                 rdev->config.evergreen.max_hw_contexts = 8;
1896                 rdev->config.evergreen.sq_num_cf_insts = 2;
1897
1898                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1899                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1900                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1901                 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1902                 break;
1903         case CHIP_TURKS:
1904                 rdev->config.evergreen.num_ses = 1;
1905                 rdev->config.evergreen.max_pipes = 4;
1906                 rdev->config.evergreen.max_tile_pipes = 4;
1907                 rdev->config.evergreen.max_simds = 6;
1908                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1909                 rdev->config.evergreen.max_gprs = 256;
1910                 rdev->config.evergreen.max_threads = 248;
1911                 rdev->config.evergreen.max_gs_threads = 32;
1912                 rdev->config.evergreen.max_stack_entries = 256;
1913                 rdev->config.evergreen.sx_num_of_sets = 4;
1914                 rdev->config.evergreen.sx_max_export_size = 256;
1915                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1916                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1917                 rdev->config.evergreen.max_hw_contexts = 8;
1918                 rdev->config.evergreen.sq_num_cf_insts = 2;
1919
1920                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1921                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1922                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1923                 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1924                 break;
1925         case CHIP_CAICOS:
1926                 rdev->config.evergreen.num_ses = 1;
1927                 rdev->config.evergreen.max_pipes = 2;
1928                 rdev->config.evergreen.max_tile_pipes = 2;
1929                 rdev->config.evergreen.max_simds = 2;
1930                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1931                 rdev->config.evergreen.max_gprs = 256;
1932                 rdev->config.evergreen.max_threads = 192;
1933                 rdev->config.evergreen.max_gs_threads = 16;
1934                 rdev->config.evergreen.max_stack_entries = 256;
1935                 rdev->config.evergreen.sx_num_of_sets = 4;
1936                 rdev->config.evergreen.sx_max_export_size = 128;
1937                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1938                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1939                 rdev->config.evergreen.max_hw_contexts = 4;
1940                 rdev->config.evergreen.sq_num_cf_insts = 1;
1941
1942                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1943                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1944                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1945                 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1946                 break;
1947         }
1948
1949         /* Initialize HDP */
1950         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1951                 WREG32((0x2c14 + j), 0x00000000);
1952                 WREG32((0x2c18 + j), 0x00000000);
1953                 WREG32((0x2c1c + j), 0x00000000);
1954                 WREG32((0x2c20 + j), 0x00000000);
1955                 WREG32((0x2c24 + j), 0x00000000);
1956         }
1957
1958         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1959
1960         evergreen_fix_pci_max_read_req_size(rdev);
1961
1962         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1963         if ((rdev->family == CHIP_PALM) ||
1964             (rdev->family == CHIP_SUMO) ||
1965             (rdev->family == CHIP_SUMO2))
1966                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1967         else
1968                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1969
1970         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1971          * not have bank info, so create a custom tiling dword.
1972          * bits 3:0   num_pipes
1973          * bits 7:4   num_banks
1974          * bits 11:8  group_size
1975          * bits 15:12 row_size
1976          */
1977         rdev->config.evergreen.tile_config = 0;
1978         switch (rdev->config.evergreen.max_tile_pipes) {
1979         case 1:
1980         default:
1981                 rdev->config.evergreen.tile_config |= (0 << 0);
1982                 break;
1983         case 2:
1984                 rdev->config.evergreen.tile_config |= (1 << 0);
1985                 break;
1986         case 4:
1987                 rdev->config.evergreen.tile_config |= (2 << 0);
1988                 break;
1989         case 8:
1990                 rdev->config.evergreen.tile_config |= (3 << 0);
1991                 break;
1992         }
1993         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1994         if (rdev->flags & RADEON_IS_IGP)
1995                 rdev->config.evergreen.tile_config |= 1 << 4;
1996         else {
1997                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1998                 case 0: /* four banks */
1999                         rdev->config.evergreen.tile_config |= 0 << 4;
2000                         break;
2001                 case 1: /* eight banks */
2002                         rdev->config.evergreen.tile_config |= 1 << 4;
2003                         break;
2004                 case 2: /* sixteen banks */
2005                 default:
2006                         rdev->config.evergreen.tile_config |= 2 << 4;
2007                         break;
2008                 }
2009         }
2010         rdev->config.evergreen.tile_config |= 0 << 8;
2011         rdev->config.evergreen.tile_config |=
2012                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2013
2014         num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
2015
2016         if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2017                 u32 efuse_straps_4;
2018                 u32 efuse_straps_3;
2019
2020                 WREG32(RCU_IND_INDEX, 0x204);
2021                 efuse_straps_4 = RREG32(RCU_IND_DATA);
2022                 WREG32(RCU_IND_INDEX, 0x203);
2023                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2024                 tmp = (((efuse_straps_4 & 0xf) << 4) |
2025                       ((efuse_straps_3 & 0xf0000000) >> 28));
2026         } else {
2027                 tmp = 0;
2028                 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2029                         u32 rb_disable_bitmap;
2030
2031                         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2032                         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2033                         rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2034                         tmp <<= 4;
2035                         tmp |= rb_disable_bitmap;
2036                 }
2037         }
2038         /* enabled rb are just the one not disabled :) */
2039         disabled_rb_mask = tmp;
2040
2041         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2042         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2043
2044         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2045         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2046         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2047         WREG32(DMA_TILING_CONFIG, gb_addr_config);
2048
2049         if ((rdev->config.evergreen.max_backends == 1) &&
2050             (rdev->flags & RADEON_IS_IGP)) {
2051                 if ((disabled_rb_mask & 3) == 1) {
2052                         /* RB0 disabled, RB1 enabled */
2053                         tmp = 0x11111111;
2054                 } else {
2055                         /* RB1 disabled, RB0 enabled */
2056                         tmp = 0x00000000;
2057                 }
2058         } else {
2059                 tmp = gb_addr_config & NUM_PIPES_MASK;
2060                 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2061                                                 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2062         }
2063         WREG32(GB_BACKEND_MAP, tmp);
2064
2065         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2066         WREG32(CGTS_TCC_DISABLE, 0);
2067         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2068         WREG32(CGTS_USER_TCC_DISABLE, 0);
2069
2070         /* set HW defaults for 3D engine */
2071         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2072                                      ROQ_IB2_START(0x2b)));
2073
2074         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2075
2076         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2077                              SYNC_GRADIENT |
2078                              SYNC_WALKER |
2079                              SYNC_ALIGNER));
2080
2081         sx_debug_1 = RREG32(SX_DEBUG_1);
2082         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2083         WREG32(SX_DEBUG_1, sx_debug_1);
2084
2085
2086         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2087         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2088         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2089         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2090
2091         if (rdev->family <= CHIP_SUMO2)
2092                 WREG32(SMX_SAR_CTL0, 0x00010000);
2093
2094         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2095                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2096                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2097
2098         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2099                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2100                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2101
2102         WREG32(VGT_NUM_INSTANCES, 1);
2103         WREG32(SPI_CONFIG_CNTL, 0);
2104         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2105         WREG32(CP_PERFMON_CNTL, 0);
2106
2107         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2108                                   FETCH_FIFO_HIWATER(0x4) |
2109                                   DONE_FIFO_HIWATER(0xe0) |
2110                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2111
2112         sq_config = RREG32(SQ_CONFIG);
2113         sq_config &= ~(PS_PRIO(3) |
2114                        VS_PRIO(3) |
2115                        GS_PRIO(3) |
2116                        ES_PRIO(3));
2117         sq_config |= (VC_ENABLE |
2118                       EXPORT_SRC_C |
2119                       PS_PRIO(0) |
2120                       VS_PRIO(1) |
2121                       GS_PRIO(2) |
2122                       ES_PRIO(3));
2123
2124         switch (rdev->family) {
2125         case CHIP_CEDAR:
2126         case CHIP_PALM:
2127         case CHIP_SUMO:
2128         case CHIP_SUMO2:
2129         case CHIP_CAICOS:
2130                 /* no vertex cache */
2131                 sq_config &= ~VC_ENABLE;
2132                 break;
2133         default:
2134                 break;
2135         }
2136
2137         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2138
2139         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2140         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2141         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2142         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2143         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2144         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2145         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2146
2147         switch (rdev->family) {
2148         case CHIP_CEDAR:
2149         case CHIP_PALM:
2150         case CHIP_SUMO:
2151         case CHIP_SUMO2:
2152                 ps_thread_count = 96;
2153                 break;
2154         default:
2155                 ps_thread_count = 128;
2156                 break;
2157         }
2158
2159         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2160         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2161         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2163         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2164         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2165
2166         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2167         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2171         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2172
2173         WREG32(SQ_CONFIG, sq_config);
2174         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2175         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2176         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2177         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2178         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2179         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2180         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2181         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2182         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2183         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2184
2185         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2186                                           FORCE_EOV_MAX_REZ_CNT(255)));
2187
2188         switch (rdev->family) {
2189         case CHIP_CEDAR:
2190         case CHIP_PALM:
2191         case CHIP_SUMO:
2192         case CHIP_SUMO2:
2193         case CHIP_CAICOS:
2194                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2195                 break;
2196         default:
2197                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2198                 break;
2199         }
2200         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2201         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2202
2203         WREG32(VGT_GS_VERTEX_REUSE, 16);
2204         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2205         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2206
2207         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2208         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2209
2210         WREG32(CB_PERF_CTR0_SEL_0, 0);
2211         WREG32(CB_PERF_CTR0_SEL_1, 0);
2212         WREG32(CB_PERF_CTR1_SEL_0, 0);
2213         WREG32(CB_PERF_CTR1_SEL_1, 0);
2214         WREG32(CB_PERF_CTR2_SEL_0, 0);
2215         WREG32(CB_PERF_CTR2_SEL_1, 0);
2216         WREG32(CB_PERF_CTR3_SEL_0, 0);
2217         WREG32(CB_PERF_CTR3_SEL_1, 0);
2218
2219         /* clear render buffer base addresses */
2220         WREG32(CB_COLOR0_BASE, 0);
2221         WREG32(CB_COLOR1_BASE, 0);
2222         WREG32(CB_COLOR2_BASE, 0);
2223         WREG32(CB_COLOR3_BASE, 0);
2224         WREG32(CB_COLOR4_BASE, 0);
2225         WREG32(CB_COLOR5_BASE, 0);
2226         WREG32(CB_COLOR6_BASE, 0);
2227         WREG32(CB_COLOR7_BASE, 0);
2228         WREG32(CB_COLOR8_BASE, 0);
2229         WREG32(CB_COLOR9_BASE, 0);
2230         WREG32(CB_COLOR10_BASE, 0);
2231         WREG32(CB_COLOR11_BASE, 0);
2232
2233         /* set the shader const cache sizes to 0 */
2234         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2235                 WREG32(i, 0);
2236         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2237                 WREG32(i, 0);
2238
2239         tmp = RREG32(HDP_MISC_CNTL);
2240         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2241         WREG32(HDP_MISC_CNTL, tmp);
2242
2243         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2244         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2245
2246         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2247
2248         udelay(50);
2249
2250 }
2251
2252 int evergreen_mc_init(struct radeon_device *rdev)
2253 {
2254         u32 tmp;
2255         int chansize, numchan;
2256
2257         /* Get VRAM informations */
2258         rdev->mc.vram_is_ddr = true;
2259         if ((rdev->family == CHIP_PALM) ||
2260             (rdev->family == CHIP_SUMO) ||
2261             (rdev->family == CHIP_SUMO2))
2262                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2263         else
2264                 tmp = RREG32(MC_ARB_RAMCFG);
2265         if (tmp & CHANSIZE_OVERRIDE) {
2266                 chansize = 16;
2267         } else if (tmp & CHANSIZE_MASK) {
2268                 chansize = 64;
2269         } else {
2270                 chansize = 32;
2271         }
2272         tmp = RREG32(MC_SHARED_CHMAP);
2273         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2274         case 0:
2275         default:
2276                 numchan = 1;
2277                 break;
2278         case 1:
2279                 numchan = 2;
2280                 break;
2281         case 2:
2282                 numchan = 4;
2283                 break;
2284         case 3:
2285                 numchan = 8;
2286                 break;
2287         }
2288         rdev->mc.vram_width = numchan * chansize;
2289         /* Could aper size report 0 ? */
2290         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2291         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2292         /* Setup GPU memory space */
2293         if ((rdev->family == CHIP_PALM) ||
2294             (rdev->family == CHIP_SUMO) ||
2295             (rdev->family == CHIP_SUMO2)) {
2296                 /* size in bytes on fusion */
2297                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2298                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2299         } else {
2300                 /* size in MB on evergreen/cayman/tn */
2301                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2302                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2303         }
2304         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2305         r700_vram_gtt_location(rdev, &rdev->mc);
2306         radeon_update_bandwidth_info(rdev);
2307
2308         return 0;
2309 }
2310
2311 void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
2312 {
2313         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
2314                 RREG32(GRBM_STATUS));
2315         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
2316                 RREG32(GRBM_STATUS_SE0));
2317         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
2318                 RREG32(GRBM_STATUS_SE1));
2319         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
2320                 RREG32(SRBM_STATUS));
2321         dev_info(rdev->dev, "  SRBM_STATUS2              = 0x%08X\n",
2322                 RREG32(SRBM_STATUS2));
2323         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2324                 RREG32(CP_STALLED_STAT1));
2325         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2326                 RREG32(CP_STALLED_STAT2));
2327         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2328                 RREG32(CP_BUSY_STAT));
2329         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2330                 RREG32(CP_STAT));
2331         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
2332                 RREG32(DMA_STATUS_REG));
2333         if (rdev->family >= CHIP_CAYMAN) {
2334                 dev_info(rdev->dev, "  R_00D834_DMA_STATUS_REG   = 0x%08X\n",
2335                          RREG32(DMA_STATUS_REG + 0x800));
2336         }
2337 }
2338
2339 bool evergreen_is_display_hung(struct radeon_device *rdev)
2340 {
2341         u32 crtc_hung = 0;
2342         u32 crtc_status[6];
2343         u32 i, j, tmp;
2344
2345         for (i = 0; i < rdev->num_crtc; i++) {
2346                 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
2347                         crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2348                         crtc_hung |= (1 << i);
2349                 }
2350         }
2351
2352         for (j = 0; j < 10; j++) {
2353                 for (i = 0; i < rdev->num_crtc; i++) {
2354                         if (crtc_hung & (1 << i)) {
2355                                 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2356                                 if (tmp != crtc_status[i])
2357                                         crtc_hung &= ~(1 << i);
2358                         }
2359                 }
2360                 if (crtc_hung == 0)
2361                         return false;
2362                 udelay(100);
2363         }
2364
2365         return true;
2366 }
2367
2368 static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
2369 {
2370         u32 reset_mask = 0;
2371         u32 tmp;
2372
2373         /* GRBM_STATUS */
2374         tmp = RREG32(GRBM_STATUS);
2375         if (tmp & (PA_BUSY | SC_BUSY |
2376                    SH_BUSY | SX_BUSY |
2377                    TA_BUSY | VGT_BUSY |
2378                    DB_BUSY | CB_BUSY |
2379                    SPI_BUSY | VGT_BUSY_NO_DMA))
2380                 reset_mask |= RADEON_RESET_GFX;
2381
2382         if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2383                    CP_BUSY | CP_COHERENCY_BUSY))
2384                 reset_mask |= RADEON_RESET_CP;
2385
2386         if (tmp & GRBM_EE_BUSY)
2387                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2388
2389         /* DMA_STATUS_REG */
2390         tmp = RREG32(DMA_STATUS_REG);
2391         if (!(tmp & DMA_IDLE))
2392                 reset_mask |= RADEON_RESET_DMA;
2393
2394         /* SRBM_STATUS2 */
2395         tmp = RREG32(SRBM_STATUS2);
2396         if (tmp & DMA_BUSY)
2397                 reset_mask |= RADEON_RESET_DMA;
2398
2399         /* SRBM_STATUS */
2400         tmp = RREG32(SRBM_STATUS);
2401         if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2402                 reset_mask |= RADEON_RESET_RLC;
2403
2404         if (tmp & IH_BUSY)
2405                 reset_mask |= RADEON_RESET_IH;
2406
2407         if (tmp & SEM_BUSY)
2408                 reset_mask |= RADEON_RESET_SEM;
2409
2410         if (tmp & GRBM_RQ_PENDING)
2411                 reset_mask |= RADEON_RESET_GRBM;
2412
2413         if (tmp & VMC_BUSY)
2414                 reset_mask |= RADEON_RESET_VMC;
2415
2416         if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2417                    MCC_BUSY | MCD_BUSY))
2418                 reset_mask |= RADEON_RESET_MC;
2419
2420         if (evergreen_is_display_hung(rdev))
2421                 reset_mask |= RADEON_RESET_DISPLAY;
2422
2423         /* VM_L2_STATUS */
2424         tmp = RREG32(VM_L2_STATUS);
2425         if (tmp & L2_BUSY)
2426                 reset_mask |= RADEON_RESET_VMC;
2427
2428         return reset_mask;
2429 }
2430
2431 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2432 {
2433         struct evergreen_mc_save save;
2434         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2435         u32 tmp;
2436
2437         if (reset_mask == 0)
2438                 return;
2439
2440         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2441
2442         evergreen_print_gpu_status_regs(rdev);
2443
2444         /* Disable CP parsing/prefetching */
2445         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2446
2447         if (reset_mask & RADEON_RESET_DMA) {
2448                 /* Disable DMA */
2449                 tmp = RREG32(DMA_RB_CNTL);
2450                 tmp &= ~DMA_RB_ENABLE;
2451                 WREG32(DMA_RB_CNTL, tmp);
2452         }
2453
2454         udelay(50);
2455
2456         evergreen_mc_stop(rdev, &save);
2457         if (evergreen_mc_wait_for_idle(rdev)) {
2458                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2459         }
2460
2461         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
2462                 grbm_soft_reset |= SOFT_RESET_DB |
2463                         SOFT_RESET_CB |
2464                         SOFT_RESET_PA |
2465                         SOFT_RESET_SC |
2466                         SOFT_RESET_SPI |
2467                         SOFT_RESET_SX |
2468                         SOFT_RESET_SH |
2469                         SOFT_RESET_TC |
2470                         SOFT_RESET_TA |
2471                         SOFT_RESET_VC |
2472                         SOFT_RESET_VGT;
2473         }
2474
2475         if (reset_mask & RADEON_RESET_CP) {
2476                 grbm_soft_reset |= SOFT_RESET_CP |
2477                         SOFT_RESET_VGT;
2478
2479                 srbm_soft_reset |= SOFT_RESET_GRBM;
2480         }
2481
2482         if (reset_mask & RADEON_RESET_DMA)
2483                 srbm_soft_reset |= SOFT_RESET_DMA;
2484
2485         if (reset_mask & RADEON_RESET_DISPLAY)
2486                 srbm_soft_reset |= SOFT_RESET_DC;
2487
2488         if (reset_mask & RADEON_RESET_RLC)
2489                 srbm_soft_reset |= SOFT_RESET_RLC;
2490
2491         if (reset_mask & RADEON_RESET_SEM)
2492                 srbm_soft_reset |= SOFT_RESET_SEM;
2493
2494         if (reset_mask & RADEON_RESET_IH)
2495                 srbm_soft_reset |= SOFT_RESET_IH;
2496
2497         if (reset_mask & RADEON_RESET_GRBM)
2498                 srbm_soft_reset |= SOFT_RESET_GRBM;
2499
2500         if (reset_mask & RADEON_RESET_VMC)
2501                 srbm_soft_reset |= SOFT_RESET_VMC;
2502
2503         if (!(rdev->flags & RADEON_IS_IGP)) {
2504                 if (reset_mask & RADEON_RESET_MC)
2505                         srbm_soft_reset |= SOFT_RESET_MC;
2506         }
2507
2508         if (grbm_soft_reset) {
2509                 tmp = RREG32(GRBM_SOFT_RESET);
2510                 tmp |= grbm_soft_reset;
2511                 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2512                 WREG32(GRBM_SOFT_RESET, tmp);
2513                 tmp = RREG32(GRBM_SOFT_RESET);
2514
2515                 udelay(50);
2516
2517                 tmp &= ~grbm_soft_reset;
2518                 WREG32(GRBM_SOFT_RESET, tmp);
2519                 tmp = RREG32(GRBM_SOFT_RESET);
2520         }
2521
2522         if (srbm_soft_reset) {
2523                 tmp = RREG32(SRBM_SOFT_RESET);
2524                 tmp |= srbm_soft_reset;
2525                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2526                 WREG32(SRBM_SOFT_RESET, tmp);
2527                 tmp = RREG32(SRBM_SOFT_RESET);
2528
2529                 udelay(50);
2530
2531                 tmp &= ~srbm_soft_reset;
2532                 WREG32(SRBM_SOFT_RESET, tmp);
2533                 tmp = RREG32(SRBM_SOFT_RESET);
2534         }
2535
2536         /* Wait a little for things to settle down */
2537         udelay(50);
2538
2539         evergreen_mc_resume(rdev, &save);
2540         udelay(50);
2541
2542         evergreen_print_gpu_status_regs(rdev);
2543 }
2544
2545 int evergreen_asic_reset(struct radeon_device *rdev)
2546 {
2547         u32 reset_mask;
2548
2549         reset_mask = evergreen_gpu_check_soft_reset(rdev);
2550
2551         if (reset_mask)
2552                 r600_set_bios_scratch_engine_hung(rdev, true);
2553
2554         evergreen_gpu_soft_reset(rdev, reset_mask);
2555
2556         reset_mask = evergreen_gpu_check_soft_reset(rdev);
2557
2558         if (!reset_mask)
2559                 r600_set_bios_scratch_engine_hung(rdev, false);
2560
2561         return 0;
2562 }
2563
2564 /**
2565  * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
2566  *
2567  * @rdev: radeon_device pointer
2568  * @ring: radeon_ring structure holding ring information
2569  *
2570  * Check if the GFX engine is locked up.
2571  * Returns true if the engine appears to be locked up, false if not.
2572  */
2573 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2574 {
2575         u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2576
2577         if (!(reset_mask & (RADEON_RESET_GFX |
2578                             RADEON_RESET_COMPUTE |
2579                             RADEON_RESET_CP))) {
2580                 radeon_ring_lockup_update(ring);
2581                 return false;
2582         }
2583         /* force CP activities */
2584         radeon_ring_force_activity(rdev, ring);
2585         return radeon_ring_test_lockup(rdev, ring);
2586 }
2587
2588 /**
2589  * evergreen_dma_is_lockup - Check if the DMA engine is locked up
2590  *
2591  * @rdev: radeon_device pointer
2592  * @ring: radeon_ring structure holding ring information
2593  *
2594  * Check if the async DMA engine is locked up.
2595  * Returns true if the engine appears to be locked up, false if not.
2596  */
2597 bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2598 {
2599         u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2600
2601         if (!(reset_mask & RADEON_RESET_DMA)) {
2602                 radeon_ring_lockup_update(ring);
2603                 return false;
2604         }
2605         /* force ring activities */
2606         radeon_ring_force_activity(rdev, ring);
2607         return radeon_ring_test_lockup(rdev, ring);
2608 }
2609
2610 /* Interrupts */
2611
2612 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2613 {
2614         if (crtc >= rdev->num_crtc)
2615                 return 0;
2616         else
2617                 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
2618 }
2619
2620 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2621 {
2622         u32 tmp;
2623
2624         if (rdev->family >= CHIP_CAYMAN) {
2625                 cayman_cp_int_cntl_setup(rdev, 0,
2626                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2627                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2628                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2629                 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2630                 WREG32(CAYMAN_DMA1_CNTL, tmp);
2631         } else
2632                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2633         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2634         WREG32(DMA_CNTL, tmp);
2635         WREG32(GRBM_INT_CNTL, 0);
2636         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2637         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2638         if (rdev->num_crtc >= 4) {
2639                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2640                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2641         }
2642         if (rdev->num_crtc >= 6) {
2643                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2644                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2645         }
2646
2647         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2648         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2649         if (rdev->num_crtc >= 4) {
2650                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2651                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2652         }
2653         if (rdev->num_crtc >= 6) {
2654                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2655                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2656         }
2657
2658         /* only one DAC on DCE6 */
2659         if (!ASIC_IS_DCE6(rdev))
2660                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2661         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2662
2663         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2664         WREG32(DC_HPD1_INT_CONTROL, tmp);
2665         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2666         WREG32(DC_HPD2_INT_CONTROL, tmp);
2667         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2668         WREG32(DC_HPD3_INT_CONTROL, tmp);
2669         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2670         WREG32(DC_HPD4_INT_CONTROL, tmp);
2671         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2672         WREG32(DC_HPD5_INT_CONTROL, tmp);
2673         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2674         WREG32(DC_HPD6_INT_CONTROL, tmp);
2675
2676 }
2677
2678 int evergreen_irq_set(struct radeon_device *rdev)
2679 {
2680         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2681         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2682         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2683         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2684         u32 grbm_int_cntl = 0;
2685         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2686         u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2687         u32 dma_cntl, dma_cntl1 = 0;
2688
2689         if (!rdev->irq.installed) {
2690                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2691                 return -EINVAL;
2692         }
2693         /* don't enable anything if the ih is disabled */
2694         if (!rdev->ih.enabled) {
2695                 r600_disable_interrupts(rdev);
2696                 /* force the active interrupt state to all disabled */
2697                 evergreen_disable_interrupt_state(rdev);
2698                 return 0;
2699         }
2700
2701         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2702         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2703         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2704         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2705         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2706         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2707
2708         afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2709         afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2710         afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2711         afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2712         afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2713         afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2714
2715         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2716
2717         if (rdev->family >= CHIP_CAYMAN) {
2718                 /* enable CP interrupts on all rings */
2719                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2720                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2721                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2722                 }
2723                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2724                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2725                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2726                 }
2727                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2728                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2729                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2730                 }
2731         } else {
2732                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2733                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2734                         cp_int_cntl |= RB_INT_ENABLE;
2735                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2736                 }
2737         }
2738
2739         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
2740                 DRM_DEBUG("r600_irq_set: sw int dma\n");
2741                 dma_cntl |= TRAP_ENABLE;
2742         }
2743
2744         if (rdev->family >= CHIP_CAYMAN) {
2745                 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2746                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
2747                         DRM_DEBUG("r600_irq_set: sw int dma1\n");
2748                         dma_cntl1 |= TRAP_ENABLE;
2749                 }
2750         }
2751
2752         if (rdev->irq.crtc_vblank_int[0] ||
2753             atomic_read(&rdev->irq.pflip[0])) {
2754                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2755                 crtc1 |= VBLANK_INT_MASK;
2756         }
2757         if (rdev->irq.crtc_vblank_int[1] ||
2758             atomic_read(&rdev->irq.pflip[1])) {
2759                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2760                 crtc2 |= VBLANK_INT_MASK;
2761         }
2762         if (rdev->irq.crtc_vblank_int[2] ||
2763             atomic_read(&rdev->irq.pflip[2])) {
2764                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2765                 crtc3 |= VBLANK_INT_MASK;
2766         }
2767         if (rdev->irq.crtc_vblank_int[3] ||
2768             atomic_read(&rdev->irq.pflip[3])) {
2769                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2770                 crtc4 |= VBLANK_INT_MASK;
2771         }
2772         if (rdev->irq.crtc_vblank_int[4] ||
2773             atomic_read(&rdev->irq.pflip[4])) {
2774                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2775                 crtc5 |= VBLANK_INT_MASK;
2776         }
2777         if (rdev->irq.crtc_vblank_int[5] ||
2778             atomic_read(&rdev->irq.pflip[5])) {
2779                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2780                 crtc6 |= VBLANK_INT_MASK;
2781         }
2782         if (rdev->irq.hpd[0]) {
2783                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2784                 hpd1 |= DC_HPDx_INT_EN;
2785         }
2786         if (rdev->irq.hpd[1]) {
2787                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2788                 hpd2 |= DC_HPDx_INT_EN;
2789         }
2790         if (rdev->irq.hpd[2]) {
2791                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2792                 hpd3 |= DC_HPDx_INT_EN;
2793         }
2794         if (rdev->irq.hpd[3]) {
2795                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2796                 hpd4 |= DC_HPDx_INT_EN;
2797         }
2798         if (rdev->irq.hpd[4]) {
2799                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2800                 hpd5 |= DC_HPDx_INT_EN;
2801         }
2802         if (rdev->irq.hpd[5]) {
2803                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2804                 hpd6 |= DC_HPDx_INT_EN;
2805         }
2806         if (rdev->irq.afmt[0]) {
2807                 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2808                 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2809         }
2810         if (rdev->irq.afmt[1]) {
2811                 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2812                 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2813         }
2814         if (rdev->irq.afmt[2]) {
2815                 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2816                 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2817         }
2818         if (rdev->irq.afmt[3]) {
2819                 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2820                 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2821         }
2822         if (rdev->irq.afmt[4]) {
2823                 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2824                 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2825         }
2826         if (rdev->irq.afmt[5]) {
2827                 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2828                 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2829         }
2830
2831         if (rdev->family >= CHIP_CAYMAN) {
2832                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2833                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2834                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2835         } else
2836                 WREG32(CP_INT_CNTL, cp_int_cntl);
2837
2838         WREG32(DMA_CNTL, dma_cntl);
2839
2840         if (rdev->family >= CHIP_CAYMAN)
2841                 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
2842
2843         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2844
2845         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2846         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2847         if (rdev->num_crtc >= 4) {
2848                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2849                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2850         }
2851         if (rdev->num_crtc >= 6) {
2852                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2853                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2854         }
2855
2856         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2857         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2858         if (rdev->num_crtc >= 4) {
2859                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2860                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2861         }
2862         if (rdev->num_crtc >= 6) {
2863                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2864                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2865         }
2866
2867         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2868         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2869         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2870         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2871         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2872         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2873
2874         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2875         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2876         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2877         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2878         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2879         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2880
2881         return 0;
2882 }
2883
2884 static void evergreen_irq_ack(struct radeon_device *rdev)
2885 {
2886         u32 tmp;
2887
2888         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2889         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2890         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2891         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2892         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2893         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2894         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2895         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2896         if (rdev->num_crtc >= 4) {
2897                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2898                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2899         }
2900         if (rdev->num_crtc >= 6) {
2901                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2902                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2903         }
2904
2905         rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2906         rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2907         rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2908         rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2909         rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2910         rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2911
2912         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2913                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2914         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2915                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2916         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2917                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2918         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2919                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2920         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2921                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2922         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2923                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2924
2925         if (rdev->num_crtc >= 4) {
2926                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2927                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2928                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2929                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2930                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2931                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2932                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2933                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2934                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2935                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2936                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2937                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2938         }
2939
2940         if (rdev->num_crtc >= 6) {
2941                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2942                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2943                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2944                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2945                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2946                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2947                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2948                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2949                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2950                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2951                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2952                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2953         }
2954
2955         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2956                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2957                 tmp |= DC_HPDx_INT_ACK;
2958                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2959         }
2960         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2961                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2962                 tmp |= DC_HPDx_INT_ACK;
2963                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2964         }
2965         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2966                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2967                 tmp |= DC_HPDx_INT_ACK;
2968                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2969         }
2970         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2971                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2972                 tmp |= DC_HPDx_INT_ACK;
2973                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2974         }
2975         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2976                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2977                 tmp |= DC_HPDx_INT_ACK;
2978                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2979         }
2980         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2981                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2982                 tmp |= DC_HPDx_INT_ACK;
2983                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2984         }
2985         if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2986                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2987                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2988                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2989         }
2990         if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2991                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2992                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2993                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2994         }
2995         if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2996                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2997                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2998                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2999         }
3000         if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3001                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
3002                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3003                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
3004         }
3005         if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3006                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
3007                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3008                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
3009         }
3010         if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3011                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
3012                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3013                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
3014         }
3015 }
3016
3017 static void evergreen_irq_disable(struct radeon_device *rdev)
3018 {
3019         r600_disable_interrupts(rdev);
3020         /* Wait and acknowledge irq */
3021         mdelay(1);
3022         evergreen_irq_ack(rdev);
3023         evergreen_disable_interrupt_state(rdev);
3024 }
3025
3026 void evergreen_irq_suspend(struct radeon_device *rdev)
3027 {
3028         evergreen_irq_disable(rdev);
3029         r600_rlc_stop(rdev);
3030 }
3031
3032 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
3033 {
3034         u32 wptr, tmp;
3035
3036         if (rdev->wb.enabled)
3037                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3038         else
3039                 wptr = RREG32(IH_RB_WPTR);
3040
3041         if (wptr & RB_OVERFLOW) {
3042                 /* When a ring buffer overflow happen start parsing interrupt
3043                  * from the last not overwritten vector (wptr + 16). Hopefully
3044                  * this should allow us to catchup.
3045                  */
3046                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3047                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3048                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3049                 tmp = RREG32(IH_RB_CNTL);
3050                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3051                 WREG32(IH_RB_CNTL, tmp);
3052         }
3053         return (wptr & rdev->ih.ptr_mask);
3054 }
3055
3056 int evergreen_irq_process(struct radeon_device *rdev)
3057 {
3058         u32 wptr;
3059         u32 rptr;
3060         u32 src_id, src_data;
3061         u32 ring_index;
3062         bool queue_hotplug = false;
3063         bool queue_hdmi = false;
3064
3065         if (!rdev->ih.enabled || rdev->shutdown)
3066                 return IRQ_NONE;
3067
3068         wptr = evergreen_get_ih_wptr(rdev);
3069
3070 restart_ih:
3071         /* is somebody else already processing irqs? */
3072         if (atomic_xchg(&rdev->ih.lock, 1))
3073                 return IRQ_NONE;
3074
3075         rptr = rdev->ih.rptr;
3076         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3077
3078         /* Order reading of wptr vs. reading of IH ring data */
3079         rmb();
3080
3081         /* display interrupts */
3082         evergreen_irq_ack(rdev);
3083
3084         while (rptr != wptr) {
3085                 /* wptr/rptr are in bytes! */
3086                 ring_index = rptr / 4;
3087                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3088                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3089
3090                 switch (src_id) {
3091                 case 1: /* D1 vblank/vline */
3092                         switch (src_data) {
3093                         case 0: /* D1 vblank */
3094                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
3095                                         if (rdev->irq.crtc_vblank_int[0]) {
3096                                                 drm_handle_vblank(rdev->ddev, 0);
3097                                                 rdev->pm.vblank_sync = true;
3098                                                 wake_up(&rdev->irq.vblank_queue);
3099                                         }
3100                                         if (atomic_read(&rdev->irq.pflip[0]))
3101                                                 radeon_crtc_handle_flip(rdev, 0);
3102                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3103                                         DRM_DEBUG("IH: D1 vblank\n");
3104                                 }
3105                                 break;
3106                         case 1: /* D1 vline */
3107                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
3108                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3109                                         DRM_DEBUG("IH: D1 vline\n");
3110                                 }
3111                                 break;
3112                         default:
3113                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3114                                 break;
3115                         }
3116                         break;
3117                 case 2: /* D2 vblank/vline */
3118                         switch (src_data) {
3119                         case 0: /* D2 vblank */
3120                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
3121                                         if (rdev->irq.crtc_vblank_int[1]) {
3122                                                 drm_handle_vblank(rdev->ddev, 1);
3123                                                 rdev->pm.vblank_sync = true;
3124                                                 wake_up(&rdev->irq.vblank_queue);
3125                                         }
3126                                         if (atomic_read(&rdev->irq.pflip[1]))
3127                                                 radeon_crtc_handle_flip(rdev, 1);
3128                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
3129                                         DRM_DEBUG("IH: D2 vblank\n");
3130                                 }
3131                                 break;
3132                         case 1: /* D2 vline */
3133                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
3134                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
3135                                         DRM_DEBUG("IH: D2 vline\n");
3136                                 }
3137                                 break;
3138                         default:
3139                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3140                                 break;
3141                         }
3142                         break;
3143                 case 3: /* D3 vblank/vline */
3144                         switch (src_data) {
3145                         case 0: /* D3 vblank */
3146                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
3147                                         if (rdev->irq.crtc_vblank_int[2]) {
3148                                                 drm_handle_vblank(rdev->ddev, 2);
3149                                                 rdev->pm.vblank_sync = true;
3150                                                 wake_up(&rdev->irq.vblank_queue);
3151                                         }
3152                                         if (atomic_read(&rdev->irq.pflip[2]))
3153                                                 radeon_crtc_handle_flip(rdev, 2);
3154                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3155                                         DRM_DEBUG("IH: D3 vblank\n");
3156                                 }
3157                                 break;
3158                         case 1: /* D3 vline */
3159                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3160                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3161                                         DRM_DEBUG("IH: D3 vline\n");
3162                                 }
3163                                 break;
3164                         default:
3165                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3166                                 break;
3167                         }
3168                         break;
3169                 case 4: /* D4 vblank/vline */
3170                         switch (src_data) {
3171                         case 0: /* D4 vblank */
3172                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3173                                         if (rdev->irq.crtc_vblank_int[3]) {
3174                                                 drm_handle_vblank(rdev->ddev, 3);
3175                                                 rdev->pm.vblank_sync = true;
3176                                                 wake_up(&rdev->irq.vblank_queue);
3177                                         }
3178                                         if (atomic_read(&rdev->irq.pflip[3]))
3179                                                 radeon_crtc_handle_flip(rdev, 3);
3180                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3181                                         DRM_DEBUG("IH: D4 vblank\n");
3182                                 }
3183                                 break;
3184                         case 1: /* D4 vline */
3185                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3186                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3187                                         DRM_DEBUG("IH: D4 vline\n");
3188                                 }
3189                                 break;
3190                         default:
3191                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3192                                 break;
3193                         }
3194                         break;
3195                 case 5: /* D5 vblank/vline */
3196                         switch (src_data) {
3197                         case 0: /* D5 vblank */
3198                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3199                                         if (rdev->irq.crtc_vblank_int[4]) {
3200                                                 drm_handle_vblank(rdev->ddev, 4);
3201                                                 rdev->pm.vblank_sync = true;
3202                                                 wake_up(&rdev->irq.vblank_queue);
3203                                         }
3204                                         if (atomic_read(&rdev->irq.pflip[4]))
3205                                                 radeon_crtc_handle_flip(rdev, 4);
3206                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3207                                         DRM_DEBUG("IH: D5 vblank\n");
3208                                 }
3209                                 break;
3210                         case 1: /* D5 vline */
3211                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3212                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3213                                         DRM_DEBUG("IH: D5 vline\n");
3214                                 }
3215                                 break;
3216                         default:
3217                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3218                                 break;
3219                         }
3220                         break;
3221                 case 6: /* D6 vblank/vline */
3222                         switch (src_data) {
3223                         case 0: /* D6 vblank */
3224                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3225                                         if (rdev->irq.crtc_vblank_int[5]) {
3226                                                 drm_handle_vblank(rdev->ddev, 5);
3227                                                 rdev->pm.vblank_sync = true;
3228                                                 wake_up(&rdev->irq.vblank_queue);
3229                                         }
3230                                         if (atomic_read(&rdev->irq.pflip[5]))
3231                                                 radeon_crtc_handle_flip(rdev, 5);
3232                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3233                                         DRM_DEBUG("IH: D6 vblank\n");
3234                                 }
3235                                 break;
3236                         case 1: /* D6 vline */
3237                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3238                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3239                                         DRM_DEBUG("IH: D6 vline\n");
3240                                 }
3241                                 break;
3242                         default:
3243                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3244                                 break;
3245                         }
3246                         break;
3247                 case 42: /* HPD hotplug */
3248                         switch (src_data) {
3249                         case 0:
3250                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3251                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3252                                         queue_hotplug = true;
3253                                         DRM_DEBUG("IH: HPD1\n");
3254                                 }
3255                                 break;
3256                         case 1:
3257                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3258                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3259                                         queue_hotplug = true;
3260                                         DRM_DEBUG("IH: HPD2\n");
3261                                 }
3262                                 break;
3263                         case 2:
3264                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3265                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3266                                         queue_hotplug = true;
3267                                         DRM_DEBUG("IH: HPD3\n");
3268                                 }
3269                                 break;
3270                         case 3:
3271                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3272                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3273                                         queue_hotplug = true;
3274                                         DRM_DEBUG("IH: HPD4\n");
3275                                 }
3276                                 break;
3277                         case 4:
3278                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3279                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3280                                         queue_hotplug = true;
3281                                         DRM_DEBUG("IH: HPD5\n");
3282                                 }
3283                                 break;
3284                         case 5:
3285                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3286                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3287                                         queue_hotplug = true;
3288                                         DRM_DEBUG("IH: HPD6\n");
3289                                 }
3290                                 break;
3291                         default:
3292                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3293                                 break;
3294                         }
3295                         break;
3296                 case 44: /* hdmi */
3297                         switch (src_data) {
3298                         case 0:
3299                                 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3300                                         rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3301                                         queue_hdmi = true;
3302                                         DRM_DEBUG("IH: HDMI0\n");
3303                                 }
3304                                 break;
3305                         case 1:
3306                                 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3307                                         rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3308                                         queue_hdmi = true;
3309                                         DRM_DEBUG("IH: HDMI1\n");
3310                                 }
3311                                 break;
3312                         case 2:
3313                                 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3314                                         rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3315                                         queue_hdmi = true;
3316                                         DRM_DEBUG("IH: HDMI2\n");
3317                                 }
3318                                 break;
3319                         case 3:
3320                                 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3321                                         rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3322                                         queue_hdmi = true;
3323                                         DRM_DEBUG("IH: HDMI3\n");
3324                                 }
3325                                 break;
3326                         case 4:
3327                                 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3328                                         rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3329                                         queue_hdmi = true;
3330                                         DRM_DEBUG("IH: HDMI4\n");
3331                                 }
3332                                 break;
3333                         case 5:
3334                                 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3335                                         rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3336                                         queue_hdmi = true;
3337                                         DRM_DEBUG("IH: HDMI5\n");
3338                                 }
3339                                 break;
3340                         default:
3341                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3342                                 break;
3343                         }
3344                         break;
3345                 case 146:
3346                 case 147:
3347                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3348                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
3349                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3350                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3351                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3352                         /* reset addr and status */
3353                         WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3354                         break;
3355                 case 176: /* CP_INT in ring buffer */
3356                 case 177: /* CP_INT in IB1 */
3357                 case 178: /* CP_INT in IB2 */
3358                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3359                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3360                         break;
3361                 case 181: /* CP EOP event */
3362                         DRM_DEBUG("IH: CP EOP\n");
3363                         if (rdev->family >= CHIP_CAYMAN) {
3364                                 switch (src_data) {
3365                                 case 0:
3366                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3367                                         break;
3368                                 case 1:
3369                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3370                                         break;
3371                                 case 2:
3372                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3373                                         break;
3374                                 }
3375                         } else
3376                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3377                         break;
3378                 case 224: /* DMA trap event */
3379                         DRM_DEBUG("IH: DMA trap\n");
3380                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3381                         break;
3382                 case 233: /* GUI IDLE */
3383                         DRM_DEBUG("IH: GUI idle\n");
3384                         break;
3385                 case 244: /* DMA trap event */
3386                         if (rdev->family >= CHIP_CAYMAN) {
3387                                 DRM_DEBUG("IH: DMA1 trap\n");
3388                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3389                         }
3390                         break;
3391                 default:
3392                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3393                         break;
3394                 }
3395
3396                 /* wptr/rptr are in bytes! */
3397                 rptr += 16;
3398                 rptr &= rdev->ih.ptr_mask;
3399         }
3400         if (queue_hotplug)
3401                 schedule_work(&rdev->hotplug_work);
3402         if (queue_hdmi)
3403                 schedule_work(&rdev->audio_work);
3404         rdev->ih.rptr = rptr;
3405         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3406         atomic_set(&rdev->ih.lock, 0);
3407
3408         /* make sure wptr hasn't changed while processing */
3409         wptr = evergreen_get_ih_wptr(rdev);
3410         if (wptr != rptr)
3411                 goto restart_ih;
3412
3413         return IRQ_HANDLED;
3414 }
3415
3416 /**
3417  * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3418  *
3419  * @rdev: radeon_device pointer
3420  * @fence: radeon fence object
3421  *
3422  * Add a DMA fence packet to the ring to write
3423  * the fence seq number and DMA trap packet to generate
3424  * an interrupt if needed (evergreen-SI).
3425  */
3426 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3427                                    struct radeon_fence *fence)
3428 {
3429         struct radeon_ring *ring = &rdev->ring[fence->ring];
3430         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3431         /* write the fence */
3432         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
3433         radeon_ring_write(ring, addr & 0xfffffffc);
3434         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3435         radeon_ring_write(ring, fence->seq);
3436         /* generate an interrupt */
3437         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
3438         /* flush HDP */
3439         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
3440         radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3441         radeon_ring_write(ring, 1);
3442 }
3443
3444 /**
3445  * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3446  *
3447  * @rdev: radeon_device pointer
3448  * @ib: IB object to schedule
3449  *
3450  * Schedule an IB in the DMA ring (evergreen).
3451  */
3452 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3453                                    struct radeon_ib *ib)
3454 {
3455         struct radeon_ring *ring = &rdev->ring[ib->ring];
3456
3457         if (rdev->wb.enabled) {
3458                 u32 next_rptr = ring->wptr + 4;
3459                 while ((next_rptr & 7) != 5)
3460                         next_rptr++;
3461                 next_rptr += 3;
3462                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
3463                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3464                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3465                 radeon_ring_write(ring, next_rptr);
3466         }
3467
3468         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3469          * Pad as necessary with NOPs.
3470          */
3471         while ((ring->wptr & 7) != 5)
3472                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3473         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
3474         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3475         radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3476
3477 }
3478
3479 /**
3480  * evergreen_copy_dma - copy pages using the DMA engine
3481  *
3482  * @rdev: radeon_device pointer
3483  * @src_offset: src GPU address
3484  * @dst_offset: dst GPU address
3485  * @num_gpu_pages: number of GPU pages to xfer
3486  * @fence: radeon fence object
3487  *
3488  * Copy GPU paging using the DMA engine (evergreen-cayman).
3489  * Used by the radeon ttm implementation to move pages if
3490  * registered as the asic copy callback.
3491  */
3492 int evergreen_copy_dma(struct radeon_device *rdev,
3493                        uint64_t src_offset, uint64_t dst_offset,
3494                        unsigned num_gpu_pages,
3495                        struct radeon_fence **fence)
3496 {
3497         struct radeon_semaphore *sem = NULL;
3498         int ring_index = rdev->asic->copy.dma_ring_index;
3499         struct radeon_ring *ring = &rdev->ring[ring_index];
3500         u32 size_in_dw, cur_size_in_dw;
3501         int i, num_loops;
3502         int r = 0;
3503
3504         r = radeon_semaphore_create(rdev, &sem);
3505         if (r) {
3506                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3507                 return r;
3508         }
3509
3510         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3511         num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3512         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3513         if (r) {
3514                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3515                 radeon_semaphore_free(rdev, &sem, NULL);
3516                 return r;
3517         }
3518
3519         if (radeon_fence_need_sync(*fence, ring->idx)) {
3520                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3521                                             ring->idx);
3522                 radeon_fence_note_sync(*fence, ring->idx);
3523         } else {
3524                 radeon_semaphore_free(rdev, &sem, NULL);
3525         }
3526
3527         for (i = 0; i < num_loops; i++) {
3528                 cur_size_in_dw = size_in_dw;
3529                 if (cur_size_in_dw > 0xFFFFF)
3530                         cur_size_in_dw = 0xFFFFF;
3531                 size_in_dw -= cur_size_in_dw;
3532                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
3533                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3534                 radeon_ring_write(ring, src_offset & 0xfffffffc);
3535                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3536                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3537                 src_offset += cur_size_in_dw * 4;
3538                 dst_offset += cur_size_in_dw * 4;
3539         }
3540
3541         r = radeon_fence_emit(rdev, fence, ring->idx);
3542         if (r) {
3543                 radeon_ring_unlock_undo(rdev, ring);
3544                 return r;
3545         }
3546
3547         radeon_ring_unlock_commit(rdev, ring);
3548         radeon_semaphore_free(rdev, &sem, *fence);
3549
3550         return r;
3551 }
3552
3553 static int evergreen_startup(struct radeon_device *rdev)
3554 {
3555         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3556         int r;
3557
3558         /* enable pcie gen2 link */
3559         evergreen_pcie_gen2_enable(rdev);
3560
3561         if (ASIC_IS_DCE5(rdev)) {
3562                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3563                         r = ni_init_microcode(rdev);
3564                         if (r) {
3565                                 DRM_ERROR("Failed to load firmware!\n");
3566                                 return r;
3567                         }
3568                 }
3569                 r = ni_mc_load_microcode(rdev);
3570                 if (r) {
3571                         DRM_ERROR("Failed to load MC firmware!\n");
3572                         return r;
3573                 }
3574         } else {
3575                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3576                         r = r600_init_microcode(rdev);
3577                         if (r) {
3578                                 DRM_ERROR("Failed to load firmware!\n");
3579                                 return r;
3580                         }
3581                 }
3582         }
3583
3584         r = r600_vram_scratch_init(rdev);
3585         if (r)
3586                 return r;
3587
3588         evergreen_mc_program(rdev);
3589         if (rdev->flags & RADEON_IS_AGP) {
3590                 evergreen_agp_enable(rdev);
3591         } else {
3592                 r = evergreen_pcie_gart_enable(rdev);
3593                 if (r)
3594                         return r;
3595         }
3596         evergreen_gpu_init(rdev);
3597
3598         r = evergreen_blit_init(rdev);
3599         if (r) {
3600                 r600_blit_fini(rdev);
3601                 rdev->asic->copy.copy = NULL;
3602                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3603         }
3604
3605         /* allocate wb buffer */
3606         r = radeon_wb_init(rdev);
3607         if (r)
3608                 return r;
3609
3610         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3611         if (r) {
3612                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3613                 return r;
3614         }
3615
3616         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3617         if (r) {
3618                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3619                 return r;
3620         }
3621
3622         /* Enable IRQ */
3623         r = r600_irq_init(rdev);
3624         if (r) {
3625                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3626                 radeon_irq_kms_fini(rdev);
3627                 return r;
3628         }
3629         evergreen_irq_set(rdev);
3630
3631         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3632                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3633                              0, 0xfffff, RADEON_CP_PACKET2);
3634         if (r)
3635                 return r;
3636
3637         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3638         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3639                              DMA_RB_RPTR, DMA_RB_WPTR,
3640                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3641         if (r)
3642                 return r;
3643
3644         r = evergreen_cp_load_microcode(rdev);
3645         if (r)
3646                 return r;
3647         r = evergreen_cp_resume(rdev);
3648         if (r)
3649                 return r;
3650         r = r600_dma_resume(rdev);
3651         if (r)
3652                 return r;
3653
3654         r = radeon_ib_pool_init(rdev);
3655         if (r) {
3656                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3657                 return r;
3658         }
3659
3660         r = r600_audio_init(rdev);
3661         if (r) {
3662                 DRM_ERROR("radeon: audio init failed\n");
3663                 return r;
3664         }
3665
3666         return 0;
3667 }
3668
3669 int evergreen_resume(struct radeon_device *rdev)
3670 {
3671         int r;
3672
3673         /* reset the asic, the gfx blocks are often in a bad state
3674          * after the driver is unloaded or after a resume
3675          */
3676         if (radeon_asic_reset(rdev))
3677                 dev_warn(rdev->dev, "GPU reset failed !\n");
3678         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3679          * posting will perform necessary task to bring back GPU into good
3680          * shape.
3681          */
3682         /* post card */
3683         atom_asic_init(rdev->mode_info.atom_context);
3684
3685         rdev->accel_working = true;
3686         r = evergreen_startup(rdev);
3687         if (r) {
3688                 DRM_ERROR("evergreen startup failed on resume\n");
3689                 rdev->accel_working = false;
3690                 return r;
3691         }
3692
3693         return r;
3694
3695 }
3696
3697 int evergreen_suspend(struct radeon_device *rdev)
3698 {
3699         r600_audio_fini(rdev);
3700         r700_cp_stop(rdev);
3701         r600_dma_stop(rdev);
3702         evergreen_irq_suspend(rdev);
3703         radeon_wb_disable(rdev);
3704         evergreen_pcie_gart_disable(rdev);
3705
3706         return 0;
3707 }
3708
3709 /* Plan is to move initialization in that function and use
3710  * helper function so that radeon_device_init pretty much
3711  * do nothing more than calling asic specific function. This
3712  * should also allow to remove a bunch of callback function
3713  * like vram_info.
3714  */
3715 int evergreen_init(struct radeon_device *rdev)
3716 {
3717         int r;
3718
3719         /* Read BIOS */
3720         if (!radeon_get_bios(rdev)) {
3721                 if (ASIC_IS_AVIVO(rdev))
3722                         return -EINVAL;
3723         }
3724         /* Must be an ATOMBIOS */
3725         if (!rdev->is_atom_bios) {
3726                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3727                 return -EINVAL;
3728         }
3729         r = radeon_atombios_init(rdev);
3730         if (r)
3731                 return r;
3732         /* reset the asic, the gfx blocks are often in a bad state
3733          * after the driver is unloaded or after a resume
3734          */
3735         if (radeon_asic_reset(rdev))
3736                 dev_warn(rdev->dev, "GPU reset failed !\n");
3737         /* Post card if necessary */
3738         if (!radeon_card_posted(rdev)) {
3739                 if (!rdev->bios) {
3740                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3741                         return -EINVAL;
3742                 }
3743                 DRM_INFO("GPU not posted. posting now...\n");
3744                 atom_asic_init(rdev->mode_info.atom_context);
3745         }
3746         /* Initialize scratch registers */
3747         r600_scratch_init(rdev);
3748         /* Initialize surface registers */
3749         radeon_surface_init(rdev);
3750         /* Initialize clocks */
3751         radeon_get_clock_info(rdev->ddev);
3752         /* Fence driver */
3753         r = radeon_fence_driver_init(rdev);
3754         if (r)
3755                 return r;
3756         /* initialize AGP */
3757         if (rdev->flags & RADEON_IS_AGP) {
3758                 r = radeon_agp_init(rdev);
3759                 if (r)
3760                         radeon_agp_disable(rdev);
3761         }
3762         /* initialize memory controller */
3763         r = evergreen_mc_init(rdev);
3764         if (r)
3765                 return r;
3766         /* Memory manager */
3767         r = radeon_bo_init(rdev);
3768         if (r)
3769                 return r;
3770
3771         r = radeon_irq_kms_init(rdev);
3772         if (r)
3773                 return r;
3774
3775         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3776         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3777
3778         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3779         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3780
3781         rdev->ih.ring_obj = NULL;
3782         r600_ih_ring_init(rdev, 64 * 1024);
3783
3784         r = r600_pcie_gart_init(rdev);
3785         if (r)
3786                 return r;
3787
3788         rdev->accel_working = true;
3789         r = evergreen_startup(rdev);
3790         if (r) {
3791                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3792                 r700_cp_fini(rdev);
3793                 r600_dma_fini(rdev);
3794                 r600_irq_fini(rdev);
3795                 radeon_wb_fini(rdev);
3796                 radeon_ib_pool_fini(rdev);
3797                 radeon_irq_kms_fini(rdev);
3798                 evergreen_pcie_gart_fini(rdev);
3799                 rdev->accel_working = false;
3800         }
3801
3802         /* Don't start up if the MC ucode is missing on BTC parts.
3803          * The default clocks and voltages before the MC ucode
3804          * is loaded are not suffient for advanced operations.
3805          */
3806         if (ASIC_IS_DCE5(rdev)) {
3807                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3808                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3809                         return -EINVAL;
3810                 }
3811         }
3812
3813         return 0;
3814 }
3815
3816 void evergreen_fini(struct radeon_device *rdev)
3817 {
3818         r600_audio_fini(rdev);
3819         r600_blit_fini(rdev);
3820         r700_cp_fini(rdev);
3821         r600_dma_fini(rdev);
3822         r600_irq_fini(rdev);
3823         radeon_wb_fini(rdev);
3824         radeon_ib_pool_fini(rdev);
3825         radeon_irq_kms_fini(rdev);
3826         evergreen_pcie_gart_fini(rdev);
3827         r600_vram_scratch_fini(rdev);
3828         radeon_gem_fini(rdev);
3829         radeon_fence_driver_fini(rdev);
3830         radeon_agp_fini(rdev);
3831         radeon_bo_fini(rdev);
3832         radeon_atombios_fini(rdev);
3833         kfree(rdev->bios);
3834         rdev->bios = NULL;
3835 }
3836
3837 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3838 {
3839         u32 link_width_cntl, speed_cntl, mask;
3840         int ret;
3841
3842         if (radeon_pcie_gen2 == 0)
3843                 return;
3844
3845         if (rdev->flags & RADEON_IS_IGP)
3846                 return;
3847
3848         if (!(rdev->flags & RADEON_IS_PCIE))
3849                 return;
3850
3851         /* x2 cards have a special sequence */
3852         if (ASIC_IS_X2(rdev))
3853                 return;
3854
3855         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3856         if (ret != 0)
3857                 return;
3858
3859         if (!(mask & DRM_PCIE_SPEED_50))
3860                 return;
3861
3862         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3863         if (speed_cntl & LC_CURRENT_DATA_RATE) {
3864                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3865                 return;
3866         }
3867
3868         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3869
3870         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3871             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3872
3873                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3874                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3875                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3876
3877                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3878                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3879                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3880
3881                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3882                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3883                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3884
3885                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3886                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3887                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3888
3889                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3890                 speed_cntl |= LC_GEN2_EN_STRAP;
3891                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3892
3893         } else {
3894                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3895                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3896                 if (1)
3897                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3898                 else
3899                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3900                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3901         }
3902 }