drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43
  44 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
  45 {
  46         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  47         u32 tmp;
  48
  49         /* make sure flip is at vb rather than hb */
  50         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
  51         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
  52         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
  53
  54         /* set pageflip to happen anywhere in vblank interval */
  55         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
  56
  57         /* enable the pflip int */
  58         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  59 }
  60
  61 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
  62 {
  63         /* disable the pflip int */
  64         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  65 }
  66
  67 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  68 {
  69         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  70         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
  71
  72         /* Lock the graphics update lock */
  73         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
  74         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  75
  76         /* update the scanout addresses */
  77         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  78                upper_32_bits(crtc_base));
  79         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  80                (u32)crtc_base);
  81
  82         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
  83                upper_32_bits(crtc_base));
  84         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
  85                (u32)crtc_base);
  86
  87         /* Wait for update_pending to go high. */
  88         while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
  89         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  90
  91         /* Unlock the lock, so double-buffering can take place inside vblank */
  92         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
  93         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
  94
  95         /* Return current update_pending status: */
  96         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
  97 }
  98
  99 /* get temperature in millidegrees */
 100 u32 evergreen_get_temp(struct radeon_device *rdev)
 101 {
 102         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 103                 ASIC_T_SHIFT;
 104         u32 actual_temp = 0;
 105
 106         if ((temp >> 10) & 1)
 107                 actual_temp = 0;
 108         else if ((temp >> 9) & 1)
 109                 actual_temp = 255;
 110         else
 111                 actual_temp = (temp >> 1) & 0xff;
 112
 113         return actual_temp * 1000;
 114 }
 115
 116 u32 sumo_get_temp(struct radeon_device *rdev)
 117 {
 118         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 119         u32 actual_temp = (temp >> 1) & 0xff;
 120
 121         return actual_temp * 1000;
 122 }
 123
 124 void evergreen_pm_misc(struct radeon_device *rdev)
 125 {
 126         int req_ps_idx = rdev->pm.requested_power_state_index;
 127         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 128         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 129         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 130
 131         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 132                 if (voltage->voltage != rdev->pm.current_vddc) {
 133                         radeon_atom_set_voltage(rdev, voltage->voltage);
 134                         rdev->pm.current_vddc = voltage->voltage;
 135                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 136                 }
 137         }
 138 }
 139
 140 void evergreen_pm_prepare(struct radeon_device *rdev)
 141 {
 142         struct drm_device *ddev = rdev->ddev;
 143         struct drm_crtc *crtc;
 144         struct radeon_crtc *radeon_crtc;
 145         u32 tmp;
 146
 147         /* disable any active CRTCs */
 148         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 149                 radeon_crtc = to_radeon_crtc(crtc);
 150                 if (radeon_crtc->enabled) {
 151                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 152                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 153                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 154                 }
 155         }
 156 }
 157
 158 void evergreen_pm_finish(struct radeon_device *rdev)
 159 {
 160         struct drm_device *ddev = rdev->ddev;
 161         struct drm_crtc *crtc;
 162         struct radeon_crtc *radeon_crtc;
 163         u32 tmp;
 164
 165         /* enable any active CRTCs */
 166         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 167                 radeon_crtc = to_radeon_crtc(crtc);
 168                 if (radeon_crtc->enabled) {
 169                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 170                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 171                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 172                 }
 173         }
 174 }
 175
 176 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 177 {
 178         bool connected = false;
 179
 180         switch (hpd) {
 181         case RADEON_HPD_1:
 182                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 183                         connected = true;
 184                 break;
 185         case RADEON_HPD_2:
 186                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 187                         connected = true;
 188                 break;
 189         case RADEON_HPD_3:
 190                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 191                         connected = true;
 192                 break;
 193         case RADEON_HPD_4:
 194                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 195                         connected = true;
 196                 break;
 197         case RADEON_HPD_5:
 198                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 199                         connected = true;
 200                 break;
 201         case RADEON_HPD_6:
 202                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 203                         connected = true;
 204                         break;
 205         default:
 206                 break;
 207         }
 208
 209         return connected;
 210 }
 211
 212 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 213                                 enum radeon_hpd_id hpd)
 214 {
 215         u32 tmp;
 216         bool connected = evergreen_hpd_sense(rdev, hpd);
 217
 218         switch (hpd) {
 219         case RADEON_HPD_1:
 220                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 221                 if (connected)
 222                         tmp &= ~DC_HPDx_INT_POLARITY;
 223                 else
 224                         tmp |= DC_HPDx_INT_POLARITY;
 225                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 226                 break;
 227         case RADEON_HPD_2:
 228                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 229                 if (connected)
 230                         tmp &= ~DC_HPDx_INT_POLARITY;
 231                 else
 232                         tmp |= DC_HPDx_INT_POLARITY;
 233                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 234                 break;
 235         case RADEON_HPD_3:
 236                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 237                 if (connected)
 238                         tmp &= ~DC_HPDx_INT_POLARITY;
 239                 else
 240                         tmp |= DC_HPDx_INT_POLARITY;
 241                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 242                 break;
 243         case RADEON_HPD_4:
 244                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 245                 if (connected)
 246                         tmp &= ~DC_HPDx_INT_POLARITY;
 247                 else
 248                         tmp |= DC_HPDx_INT_POLARITY;
 249                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 250                 break;
 251         case RADEON_HPD_5:
 252                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 253                 if (connected)
 254                         tmp &= ~DC_HPDx_INT_POLARITY;
 255                 else
 256                         tmp |= DC_HPDx_INT_POLARITY;
 257                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 258                         break;
 259         case RADEON_HPD_6:
 260                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 261                 if (connected)
 262                         tmp &= ~DC_HPDx_INT_POLARITY;
 263                 else
 264                         tmp |= DC_HPDx_INT_POLARITY;
 265                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 266                 break;
 267         default:
 268                 break;
 269         }
 270 }
 271
 272 void evergreen_hpd_init(struct radeon_device *rdev)
 273 {
 274         struct drm_device *dev = rdev->ddev;
 275         struct drm_connector *connector;
 276         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 277                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 278
 279         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 280                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 281                 switch (radeon_connector->hpd.hpd) {
 282                 case RADEON_HPD_1:
 283                         WREG32(DC_HPD1_CONTROL, tmp);
 284                         rdev->irq.hpd[0] = true;
 285                         break;
 286                 case RADEON_HPD_2:
 287                         WREG32(DC_HPD2_CONTROL, tmp);
 288                         rdev->irq.hpd[1] = true;
 289                         break;
 290                 case RADEON_HPD_3:
 291                         WREG32(DC_HPD3_CONTROL, tmp);
 292                         rdev->irq.hpd[2] = true;
 293                         break;
 294                 case RADEON_HPD_4:
 295                         WREG32(DC_HPD4_CONTROL, tmp);
 296                         rdev->irq.hpd[3] = true;
 297                         break;
 298                 case RADEON_HPD_5:
 299                         WREG32(DC_HPD5_CONTROL, tmp);
 300                         rdev->irq.hpd[4] = true;
 301                         break;
 302                 case RADEON_HPD_6:
 303                         WREG32(DC_HPD6_CONTROL, tmp);
 304                         rdev->irq.hpd[5] = true;
 305                         break;
 306                 default:
 307                         break;
 308                 }
 309         }
 310         if (rdev->irq.installed)
 311                 evergreen_irq_set(rdev);
 312 }
 313
 314 void evergreen_hpd_fini(struct radeon_device *rdev)
 315 {
 316         struct drm_device *dev = rdev->ddev;
 317         struct drm_connector *connector;
 318
 319         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 320                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 321                 switch (radeon_connector->hpd.hpd) {
 322                 case RADEON_HPD_1:
 323                         WREG32(DC_HPD1_CONTROL, 0);
 324                         rdev->irq.hpd[0] = false;
 325                         break;
 326                 case RADEON_HPD_2:
 327                         WREG32(DC_HPD2_CONTROL, 0);
 328                         rdev->irq.hpd[1] = false;
 329                         break;
 330                 case RADEON_HPD_3:
 331                         WREG32(DC_HPD3_CONTROL, 0);
 332                         rdev->irq.hpd[2] = false;
 333                         break;
 334                 case RADEON_HPD_4:
 335                         WREG32(DC_HPD4_CONTROL, 0);
 336                         rdev->irq.hpd[3] = false;
 337                         break;
 338                 case RADEON_HPD_5:
 339                         WREG32(DC_HPD5_CONTROL, 0);
 340                         rdev->irq.hpd[4] = false;
 341                         break;
 342                 case RADEON_HPD_6:
 343                         WREG32(DC_HPD6_CONTROL, 0);
 344                         rdev->irq.hpd[5] = false;
 345                         break;
 346                 default:
 347                         break;
 348                 }
 349         }
 350 }
 351
 352 /* watermark setup */
 353
 354 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 355                                         struct radeon_crtc *radeon_crtc,
 356                                         struct drm_display_mode *mode,
 357                                         struct drm_display_mode *other_mode)
 358 {
 359         u32 tmp = 0;
 360         /*
 361          * Line Buffer Setup
 362          * There are 3 line buffers, each one shared by 2 display controllers.
 363          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 364          * the display controllers.  The paritioning is done via one of four
 365          * preset allocations specified in bits 2:0:
 366          * first display controller
 367          *  0 - first half of lb (3840 * 2)
 368          *  1 - first 3/4 of lb (5760 * 2)
 369          *  2 - whole lb (7680 * 2)
 370          *  3 - first 1/4 of lb (1920 * 2)
 371          * second display controller
 372          *  4 - second half of lb (3840 * 2)
 373          *  5 - second 3/4 of lb (5760 * 2)
 374          *  6 - whole lb (7680 * 2)
 375          *  7 - last 1/4 of lb (1920 * 2)
 376          */
 377         if (mode && other_mode) {
 378                 if (mode->hdisplay > other_mode->hdisplay) {
 379                         if (mode->hdisplay > 2560)
 380                                 tmp = 1; /* 3/4 */
 381                         else
 382                                 tmp = 0; /* 1/2 */
 383                 } else if (other_mode->hdisplay > mode->hdisplay) {
 384                         if (other_mode->hdisplay > 2560)
 385                                 tmp = 3; /* 1/4 */
 386                         else
 387                                 tmp = 0; /* 1/2 */
 388                 } else
 389                         tmp = 0; /* 1/2 */
 390         } else if (mode)
 391                 tmp = 2; /* whole */
 392         else if (other_mode)
 393                 tmp = 3; /* 1/4 */
 394
 395         /* second controller of the pair uses second half of the lb */
 396         if (radeon_crtc->crtc_id % 2)
 397                 tmp += 4;
 398         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 399
 400         switch (tmp) {
 401         case 0:
 402         case 4:
 403         default:
 404                 if (ASIC_IS_DCE5(rdev))
 405                         return 4096 * 2;
 406                 else
 407                         return 3840 * 2;
 408         case 1:
 409         case 5:
 410                 if (ASIC_IS_DCE5(rdev))
 411                         return 6144 * 2;
 412                 else
 413                         return 5760 * 2;
 414         case 2:
 415         case 6:
 416                 if (ASIC_IS_DCE5(rdev))
 417                         return 8192 * 2;
 418                 else
 419                         return 7680 * 2;
 420         case 3:
 421         case 7:
 422                 if (ASIC_IS_DCE5(rdev))
 423                         return 2048 * 2;
 424                 else
 425                         return 1920 * 2;
 426         }
 427 }
 428
 429 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 430 {
 431         u32 tmp = RREG32(MC_SHARED_CHMAP);
 432
 433         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 434         case 0:
 435         default:
 436                 return 1;
 437         case 1:
 438                 return 2;
 439         case 2:
 440                 return 4;
 441         case 3:
 442                 return 8;
 443         }
 444 }
 445
 446 struct evergreen_wm_params {
 447         u32 dram_channels; /* number of dram channels */
 448         u32 yclk;          /* bandwidth per dram data pin in kHz */
 449         u32 sclk;          /* engine clock in kHz */
 450         u32 disp_clk;      /* display clock in kHz */
 451         u32 src_width;     /* viewport width */
 452         u32 active_time;   /* active display time in ns */
 453         u32 blank_time;    /* blank time in ns */
 454         bool interlaced;    /* mode is interlaced */
 455         fixed20_12 vsc;    /* vertical scale ratio */
 456         u32 num_heads;     /* number of active crtcs */
 457         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 458         u32 lb_size;       /* line buffer allocated to pipe */
 459         u32 vtaps;         /* vertical scaler taps */
 460 };
 461
 462 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 463 {
 464         /* Calculate DRAM Bandwidth and the part allocated to display. */
 465         fixed20_12 dram_efficiency; /* 0.7 */
 466         fixed20_12 yclk, dram_channels, bandwidth;
 467         fixed20_12 a;
 468
 469         a.full = dfixed_const(1000);
 470         yclk.full = dfixed_const(wm->yclk);
 471         yclk.full = dfixed_div(yclk, a);
 472         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 473         a.full = dfixed_const(10);
 474         dram_efficiency.full = dfixed_const(7);
 475         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 476         bandwidth.full = dfixed_mul(dram_channels, yclk);
 477         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 478
 479         return dfixed_trunc(bandwidth);
 480 }
 481
 482 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 483 {
 484         /* Calculate DRAM Bandwidth and the part allocated to display. */
 485         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 486         fixed20_12 yclk, dram_channels, bandwidth;
 487         fixed20_12 a;
 488
 489         a.full = dfixed_const(1000);
 490         yclk.full = dfixed_const(wm->yclk);
 491         yclk.full = dfixed_div(yclk, a);
 492         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 493         a.full = dfixed_const(10);
 494         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 495         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 496         bandwidth.full = dfixed_mul(dram_channels, yclk);
 497         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 498
 499         return dfixed_trunc(bandwidth);
 500 }
 501
 502 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 503 {
 504         /* Calculate the display Data return Bandwidth */
 505         fixed20_12 return_efficiency; /* 0.8 */
 506         fixed20_12 sclk, bandwidth;
 507         fixed20_12 a;
 508
 509         a.full = dfixed_const(1000);
 510         sclk.full = dfixed_const(wm->sclk);
 511         sclk.full = dfixed_div(sclk, a);
 512         a.full = dfixed_const(10);
 513         return_efficiency.full = dfixed_const(8);
 514         return_efficiency.full = dfixed_div(return_efficiency, a);
 515         a.full = dfixed_const(32);
 516         bandwidth.full = dfixed_mul(a, sclk);
 517         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 518
 519         return dfixed_trunc(bandwidth);
 520 }
 521
 522 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 523 {
 524         /* Calculate the DMIF Request Bandwidth */
 525         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 526         fixed20_12 disp_clk, bandwidth;
 527         fixed20_12 a;
 528
 529         a.full = dfixed_const(1000);
 530         disp_clk.full = dfixed_const(wm->disp_clk);
 531         disp_clk.full = dfixed_div(disp_clk, a);
 532         a.full = dfixed_const(10);
 533         disp_clk_request_efficiency.full = dfixed_const(8);
 534         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 535         a.full = dfixed_const(32);
 536         bandwidth.full = dfixed_mul(a, disp_clk);
 537         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 538
 539         return dfixed_trunc(bandwidth);
 540 }
 541
 542 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 543 {
 544         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 545         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 546         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 547         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 548
 549         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 550 }
 551
 552 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 553 {
 554         /* Calculate the display mode Average Bandwidth
 555          * DisplayMode should contain the source and destination dimensions,
 556          * timing, etc.
 557          */
 558         fixed20_12 bpp;
 559         fixed20_12 line_time;
 560         fixed20_12 src_width;
 561         fixed20_12 bandwidth;
 562         fixed20_12 a;
 563
 564         a.full = dfixed_const(1000);
 565         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 566         line_time.full = dfixed_div(line_time, a);
 567         bpp.full = dfixed_const(wm->bytes_per_pixel);
 568         src_width.full = dfixed_const(wm->src_width);
 569         bandwidth.full = dfixed_mul(src_width, bpp);
 570         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 571         bandwidth.full = dfixed_div(bandwidth, line_time);
 572
 573         return dfixed_trunc(bandwidth);
 574 }
 575
 576 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 577 {
 578         /* First calcualte the latency in ns */
 579         u32 mc_latency = 2000; /* 2000 ns. */
 580         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 581         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 582         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 583         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 584         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 585                 (wm->num_heads * cursor_line_pair_return_time);
 586         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 587         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 588         fixed20_12 a, b, c;
 589
 590         if (wm->num_heads == 0)
 591                 return 0;
 592
 593         a.full = dfixed_const(2);
 594         b.full = dfixed_const(1);
 595         if ((wm->vsc.full > a.full) ||
 596             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 597             (wm->vtaps >= 5) ||
 598             ((wm->vsc.full >= a.full) && wm->interlaced))
 599                 max_src_lines_per_dst_line = 4;
 600         else
 601                 max_src_lines_per_dst_line = 2;
 602
 603         a.full = dfixed_const(available_bandwidth);
 604         b.full = dfixed_const(wm->num_heads);
 605         a.full = dfixed_div(a, b);
 606
 607         b.full = dfixed_const(1000);
 608         c.full = dfixed_const(wm->disp_clk);
 609         b.full = dfixed_div(c, b);
 610         c.full = dfixed_const(wm->bytes_per_pixel);
 611         b.full = dfixed_mul(b, c);
 612
 613         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 614
 615         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 616         b.full = dfixed_const(1000);
 617         c.full = dfixed_const(lb_fill_bw);
 618         b.full = dfixed_div(c, b);
 619         a.full = dfixed_div(a, b);
 620         line_fill_time = dfixed_trunc(a);
 621
 622         if (line_fill_time < wm->active_time)
 623                 return latency;
 624         else
 625                 return latency + (line_fill_time - wm->active_time);
 626
 627 }
 628
 629 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 630 {
 631         if (evergreen_average_bandwidth(wm) <=
 632             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 633                 return true;
 634         else
 635                 return false;
 636 };
 637
 638 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 639 {
 640         if (evergreen_average_bandwidth(wm) <=
 641             (evergreen_available_bandwidth(wm) / wm->num_heads))
 642                 return true;
 643         else
 644                 return false;
 645 };
 646
 647 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 648 {
 649         u32 lb_partitions = wm->lb_size / wm->src_width;
 650         u32 line_time = wm->active_time + wm->blank_time;
 651         u32 latency_tolerant_lines;
 652         u32 latency_hiding;
 653         fixed20_12 a;
 654
 655         a.full = dfixed_const(1);
 656         if (wm->vsc.full > a.full)
 657                 latency_tolerant_lines = 1;
 658         else {
 659                 if (lb_partitions <= (wm->vtaps + 1))
 660                         latency_tolerant_lines = 1;
 661                 else
 662                         latency_tolerant_lines = 2;
 663         }
 664
 665         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 666
 667         if (evergreen_latency_watermark(wm) <= latency_hiding)
 668                 return true;
 669         else
 670                 return false;
 671 }
 672
 673 static void evergreen_program_watermarks(struct radeon_device *rdev,
 674                                          struct radeon_crtc *radeon_crtc,
 675                                          u32 lb_size, u32 num_heads)
 676 {
 677         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 678         struct evergreen_wm_params wm;
 679         u32 pixel_period;
 680         u32 line_time = 0;
 681         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 682         u32 priority_a_mark = 0, priority_b_mark = 0;
 683         u32 priority_a_cnt = PRIORITY_OFF;
 684         u32 priority_b_cnt = PRIORITY_OFF;
 685         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 686         u32 tmp, arb_control3;
 687         fixed20_12 a, b, c;
 688
 689         if (radeon_crtc->base.enabled && num_heads && mode) {
 690                 pixel_period = 1000000 / (u32)mode->clock;
 691                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 692                 priority_a_cnt = 0;
 693                 priority_b_cnt = 0;
 694
 695                 wm.yclk = rdev->pm.current_mclk * 10;
 696                 wm.sclk = rdev->pm.current_sclk * 10;
 697                 wm.disp_clk = mode->clock;
 698                 wm.src_width = mode->crtc_hdisplay;
 699                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 700                 wm.blank_time = line_time - wm.active_time;
 701                 wm.interlaced = false;
 702                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 703                         wm.interlaced = true;
 704                 wm.vsc = radeon_crtc->vsc;
 705                 wm.vtaps = 1;
 706                 if (radeon_crtc->rmx_type != RMX_OFF)
 707                         wm.vtaps = 2;
 708                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 709                 wm.lb_size = lb_size;
 710                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 711                 wm.num_heads = num_heads;
 712
 713                 /* set for high clocks */
 714                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 715                 /* set for low clocks */
 716                 /* wm.yclk = low clk; wm.sclk = low clk */
 717                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 718
 719                 /* possibly force display priority to high */
 720                 /* should really do this at mode validation time... */
 721                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 722                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 723                     !evergreen_check_latency_hiding(&wm) ||
 724                     (rdev->disp_priority == 2)) {
 725                         DRM_INFO("force priority to high\n");
 726                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 727                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 728                 }
 729
 730                 a.full = dfixed_const(1000);
 731                 b.full = dfixed_const(mode->clock);
 732                 b.full = dfixed_div(b, a);
 733                 c.full = dfixed_const(latency_watermark_a);
 734                 c.full = dfixed_mul(c, b);
 735                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 736                 c.full = dfixed_div(c, a);
 737                 a.full = dfixed_const(16);
 738                 c.full = dfixed_div(c, a);
 739                 priority_a_mark = dfixed_trunc(c);
 740                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 741
 742                 a.full = dfixed_const(1000);
 743                 b.full = dfixed_const(mode->clock);
 744                 b.full = dfixed_div(b, a);
 745                 c.full = dfixed_const(latency_watermark_b);
 746                 c.full = dfixed_mul(c, b);
 747                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 748                 c.full = dfixed_div(c, a);
 749                 a.full = dfixed_const(16);
 750                 c.full = dfixed_div(c, a);
 751                 priority_b_mark = dfixed_trunc(c);
 752                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 753         }
 754
 755         /* select wm A */
 756         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 757         tmp = arb_control3;
 758         tmp &= ~LATENCY_WATERMARK_MASK(3);
 759         tmp |= LATENCY_WATERMARK_MASK(1);
 760         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 761         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 762                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
 763                 LATENCY_HIGH_WATERMARK(line_time)));
 764         /* select wm B */
 765         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
 766         tmp &= ~LATENCY_WATERMARK_MASK(3);
 767         tmp |= LATENCY_WATERMARK_MASK(2);
 768         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
 769         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
 770                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
 771                 LATENCY_HIGH_WATERMARK(line_time)));
 772         /* restore original selection */
 773         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
 774
 775         /* write the priority marks */
 776         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
 777         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
 778
 779 }
 780
 781 void evergreen_bandwidth_update(struct radeon_device *rdev)
 782 {
 783         struct drm_display_mode *mode0 = NULL;
 784         struct drm_display_mode *mode1 = NULL;
 785         u32 num_heads = 0, lb_size;
 786         int i;
 787
 788         radeon_update_display_priority(rdev);
 789
 790         for (i = 0; i < rdev->num_crtc; i++) {
 791                 if (rdev->mode_info.crtcs[i]->base.enabled)
 792                         num_heads++;
 793         }
 794         for (i = 0; i < rdev->num_crtc; i += 2) {
 795                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
 796                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
 797                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
 798                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
 799                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
 800                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
 801         }
 802 }
 803
 804 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 805 {
 806         unsigned i;
 807         u32 tmp;
 808
 809         for (i = 0; i < rdev->usec_timeout; i++) {
 810                 /* read MC_STATUS */
 811                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 812                 if (!tmp)
 813                         return 0;
 814                 udelay(1);
 815         }
 816         return -1;
 817 }
 818
 819 /*
 820  * GART
 821  */
 822 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 823 {
 824         unsigned i;
 825         u32 tmp;
 826
 827         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 828
 829         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 830         for (i = 0; i < rdev->usec_timeout; i++) {
 831                 /* read MC_STATUS */
 832                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 833                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 834                 if (tmp == 2) {
 835                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 836                         return;
 837                 }
 838                 if (tmp) {
 839                         return;
 840                 }
 841                 udelay(1);
 842         }
 843 }
 844
 845 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 846 {
 847         u32 tmp;
 848         int r;
 849
 850         if (rdev->gart.table.vram.robj == NULL) {
 851                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 852                 return -EINVAL;
 853         }
 854         r = radeon_gart_table_vram_pin(rdev);
 855         if (r)
 856                 return r;
 857         radeon_gart_restore(rdev);
 858         /* Setup L2 cache */
 859         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 860                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 861                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 862         WREG32(VM_L2_CNTL2, 0);
 863         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 864         /* Setup TLB control */
 865         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 866                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 867                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 868                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 869         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 870         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 871         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 872         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 873         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 874         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 875         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 876         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 877         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 878         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 879         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 880                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 881         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 882                         (u32)(rdev->dummy_page.addr >> 12));
 883         WREG32(VM_CONTEXT1_CNTL, 0);
 884
 885         evergreen_pcie_gart_tlb_flush(rdev);
 886         rdev->gart.ready = true;
 887         return 0;
 888 }
 889
 890 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 891 {
 892         u32 tmp;
 893         int r;
 894
 895         /* Disable all tables */
 896         WREG32(VM_CONTEXT0_CNTL, 0);
 897         WREG32(VM_CONTEXT1_CNTL, 0);
 898
 899         /* Setup L2 cache */
 900         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 901                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 902         WREG32(VM_L2_CNTL2, 0);
 903         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 904         /* Setup TLB control */
 905         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 906         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 907         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 908         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 909         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 910         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 911         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 912         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 913         if (rdev->gart.table.vram.robj) {
 914                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 915                 if (likely(r == 0)) {
 916                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 917                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 918                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 919                 }
 920         }
 921 }
 922
 923 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 924 {
 925         evergreen_pcie_gart_disable(rdev);
 926         radeon_gart_table_vram_free(rdev);
 927         radeon_gart_fini(rdev);
 928 }
 929
 930
 931 void evergreen_agp_enable(struct radeon_device *rdev)
 932 {
 933         u32 tmp;
 934
 935         /* Setup L2 cache */
 936         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 937                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 938                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 939         WREG32(VM_L2_CNTL2, 0);
 940         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 941         /* Setup TLB control */
 942         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 943                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 944                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 945                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 946         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 947         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 948         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 949         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 950         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 951         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 952         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 953         WREG32(VM_CONTEXT0_CNTL, 0);
 954         WREG32(VM_CONTEXT1_CNTL, 0);
 955 }
 956
 957 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 958 {
 959         save->vga_control[0] = RREG32(D1VGA_CONTROL);
 960         save->vga_control[1] = RREG32(D2VGA_CONTROL);
 961         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 962         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 963         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 964         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 965         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 966         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 967         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 968         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 969         if (!(rdev->flags & RADEON_IS_IGP)) {
 970                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 971                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 972                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 973                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 974         }
 975
 976         /* Stop all video */
 977         WREG32(VGA_RENDER_CONTROL, 0);
 978         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 979         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 980         if (!(rdev->flags & RADEON_IS_IGP)) {
 981                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 982                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 983                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 984                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 985         }
 986         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 987         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 988         if (!(rdev->flags & RADEON_IS_IGP)) {
 989                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 990                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 991                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 992                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 993         }
 994         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 995         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 996         if (!(rdev->flags & RADEON_IS_IGP)) {
 997                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 998                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 999                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1000                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1001         }
1002
1003         WREG32(D1VGA_CONTROL, 0);
1004         WREG32(D2VGA_CONTROL, 0);
1005         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1006         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1007         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1008         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1009 }
1010
1011 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1012 {
1013         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1014                upper_32_bits(rdev->mc.vram_start));
1015         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1016                upper_32_bits(rdev->mc.vram_start));
1017         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1018                (u32)rdev->mc.vram_start);
1019         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1020                (u32)rdev->mc.vram_start);
1021
1022         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1023                upper_32_bits(rdev->mc.vram_start));
1024         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1025                upper_32_bits(rdev->mc.vram_start));
1026         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1027                (u32)rdev->mc.vram_start);
1028         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1029                (u32)rdev->mc.vram_start);
1030
1031         if (!(rdev->flags & RADEON_IS_IGP)) {
1032                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1033                        upper_32_bits(rdev->mc.vram_start));
1034                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1035                        upper_32_bits(rdev->mc.vram_start));
1036                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1037                        (u32)rdev->mc.vram_start);
1038                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1039                        (u32)rdev->mc.vram_start);
1040
1041                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1042                        upper_32_bits(rdev->mc.vram_start));
1043                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1044                        upper_32_bits(rdev->mc.vram_start));
1045                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1046                        (u32)rdev->mc.vram_start);
1047                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1048                        (u32)rdev->mc.vram_start);
1049
1050                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1051                        upper_32_bits(rdev->mc.vram_start));
1052                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1053                        upper_32_bits(rdev->mc.vram_start));
1054                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1055                        (u32)rdev->mc.vram_start);
1056                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1057                        (u32)rdev->mc.vram_start);
1058
1059                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1060                        upper_32_bits(rdev->mc.vram_start));
1061                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1062                        upper_32_bits(rdev->mc.vram_start));
1063                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1064                        (u32)rdev->mc.vram_start);
1065                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1066                        (u32)rdev->mc.vram_start);
1067         }
1068
1069         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1070         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1071         /* Unlock host access */
1072         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1073         mdelay(1);
1074         /* Restore video state */
1075         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1076         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1077         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1078         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1079         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1080         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1081         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1082         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1083         if (!(rdev->flags & RADEON_IS_IGP)) {
1084                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1085                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1086                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1087                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1088         }
1089         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1090         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1091         if (!(rdev->flags & RADEON_IS_IGP)) {
1092                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1093                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1094                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1095                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1096         }
1097         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1098         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1099         if (!(rdev->flags & RADEON_IS_IGP)) {
1100                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1101                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1102                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1103                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1104         }
1105         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1106 }
1107
1108 static void evergreen_mc_program(struct radeon_device *rdev)
1109 {
1110         struct evergreen_mc_save save;
1111         u32 tmp;
1112         int i, j;
1113
1114         /* Initialize HDP */
1115         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1116                 WREG32((0x2c14 + j), 0x00000000);
1117                 WREG32((0x2c18 + j), 0x00000000);
1118                 WREG32((0x2c1c + j), 0x00000000);
1119                 WREG32((0x2c20 + j), 0x00000000);
1120                 WREG32((0x2c24 + j), 0x00000000);
1121         }
1122         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1123
1124         evergreen_mc_stop(rdev, &save);
1125         if (evergreen_mc_wait_for_idle(rdev)) {
1126                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1127         }
1128         /* Lockout access through VGA aperture*/
1129         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1130         /* Update configuration */
1131         if (rdev->flags & RADEON_IS_AGP) {
1132                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1133                         /* VRAM before AGP */
1134                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1135                                 rdev->mc.vram_start >> 12);
1136                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1137                                 rdev->mc.gtt_end >> 12);
1138                 } else {
1139                         /* VRAM after AGP */
1140                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1141                                 rdev->mc.gtt_start >> 12);
1142                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1143                                 rdev->mc.vram_end >> 12);
1144                 }
1145         } else {
1146                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1147                         rdev->mc.vram_start >> 12);
1148                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1149                         rdev->mc.vram_end >> 12);
1150         }
1151         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1152         if (rdev->flags & RADEON_IS_IGP) {
1153                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1154                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1155                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1156                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1157         }
1158         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1159         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1160         WREG32(MC_VM_FB_LOCATION, tmp);
1161         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1162         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1163         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1164         if (rdev->flags & RADEON_IS_AGP) {
1165                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1166                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1167                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1168         } else {
1169                 WREG32(MC_VM_AGP_BASE, 0);
1170                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1171                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1172         }
1173         if (evergreen_mc_wait_for_idle(rdev)) {
1174                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1175         }
1176         evergreen_mc_resume(rdev, &save);
1177         /* we need to own VRAM, so turn off the VGA renderer here
1178          * to stop it overwriting our objects */
1179         rv515_vga_render_disable(rdev);
1180 }
1181
1182 /*
1183  * CP.
1184  */
1185
1186 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1187 {
1188         const __be32 *fw_data;
1189         int i;
1190
1191         if (!rdev->me_fw || !rdev->pfp_fw)
1192                 return -EINVAL;
1193
1194         r700_cp_stop(rdev);
1195         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1196
1197         fw_data = (const __be32 *)rdev->pfp_fw->data;
1198         WREG32(CP_PFP_UCODE_ADDR, 0);
1199         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1200                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1201         WREG32(CP_PFP_UCODE_ADDR, 0);
1202
1203         fw_data = (const __be32 *)rdev->me_fw->data;
1204         WREG32(CP_ME_RAM_WADDR, 0);
1205         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1206                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1207
1208         WREG32(CP_PFP_UCODE_ADDR, 0);
1209         WREG32(CP_ME_RAM_WADDR, 0);
1210         WREG32(CP_ME_RAM_RADDR, 0);
1211         return 0;
1212 }
1213
1214 static int evergreen_cp_start(struct radeon_device *rdev)
1215 {
1216         int r, i;
1217         uint32_t cp_me;
1218
1219         r = radeon_ring_lock(rdev, 7);
1220         if (r) {
1221                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1222                 return r;
1223         }
1224         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1225         radeon_ring_write(rdev, 0x1);
1226         radeon_ring_write(rdev, 0x0);
1227         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1228         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1229         radeon_ring_write(rdev, 0);
1230         radeon_ring_write(rdev, 0);
1231         radeon_ring_unlock_commit(rdev);
1232
1233         cp_me = 0xff;
1234         WREG32(CP_ME_CNTL, cp_me);
1235
1236         r = radeon_ring_lock(rdev, evergreen_default_size + 15);
1237         if (r) {
1238                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1239                 return r;
1240         }
1241
1242         /* setup clear context state */
1243         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1244         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1245
1246         for (i = 0; i < evergreen_default_size; i++)
1247                 radeon_ring_write(rdev, evergreen_default_state[i]);
1248
1249         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1250         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1251
1252         /* set clear context state */
1253         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1254         radeon_ring_write(rdev, 0);
1255
1256         /* SQ_VTX_BASE_VTX_LOC */
1257         radeon_ring_write(rdev, 0xc0026f00);
1258         radeon_ring_write(rdev, 0x00000000);
1259         radeon_ring_write(rdev, 0x00000000);
1260         radeon_ring_write(rdev, 0x00000000);
1261
1262         /* Clear consts */
1263         radeon_ring_write(rdev, 0xc0036f00);
1264         radeon_ring_write(rdev, 0x00000bc4);
1265         radeon_ring_write(rdev, 0xffffffff);
1266         radeon_ring_write(rdev, 0xffffffff);
1267         radeon_ring_write(rdev, 0xffffffff);
1268
1269         radeon_ring_unlock_commit(rdev);
1270
1271         return 0;
1272 }
1273
1274 int evergreen_cp_resume(struct radeon_device *rdev)
1275 {
1276         u32 tmp;
1277         u32 rb_bufsz;
1278         int r;
1279
1280         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1281         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1282                                  SOFT_RESET_PA |
1283                                  SOFT_RESET_SH |
1284                                  SOFT_RESET_VGT |
1285                                  SOFT_RESET_SX));
1286         RREG32(GRBM_SOFT_RESET);
1287         mdelay(15);
1288         WREG32(GRBM_SOFT_RESET, 0);
1289         RREG32(GRBM_SOFT_RESET);
1290
1291         /* Set ring buffer size */
1292         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1293         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1294 #ifdef __BIG_ENDIAN
1295         tmp |= BUF_SWAP_32BIT;
1296 #endif
1297         WREG32(CP_RB_CNTL, tmp);
1298         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1299
1300         /* Set the write pointer delay */
1301         WREG32(CP_RB_WPTR_DELAY, 0);
1302
1303         /* Initialize the ring buffer's read and write pointers */
1304         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1305         WREG32(CP_RB_RPTR_WR, 0);
1306         WREG32(CP_RB_WPTR, 0);
1307
1308         /* set the wb address wether it's enabled or not */
1309         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1310         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1311         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1312
1313         if (rdev->wb.enabled)
1314                 WREG32(SCRATCH_UMSK, 0xff);
1315         else {
1316                 tmp |= RB_NO_UPDATE;
1317                 WREG32(SCRATCH_UMSK, 0);
1318         }
1319
1320         mdelay(1);
1321         WREG32(CP_RB_CNTL, tmp);
1322
1323         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1324         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1325
1326         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1327         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1328
1329         evergreen_cp_start(rdev);
1330         rdev->cp.ready = true;
1331         r = radeon_ring_test(rdev);
1332         if (r) {
1333                 rdev->cp.ready = false;
1334                 return r;
1335         }
1336         return 0;
1337 }
1338
1339 /*
1340  * Core functions
1341  */
1342 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1343                                                   u32 num_tile_pipes,
1344                                                   u32 num_backends,
1345                                                   u32 backend_disable_mask)
1346 {
1347         u32 backend_map = 0;
1348         u32 enabled_backends_mask = 0;
1349         u32 enabled_backends_count = 0;
1350         u32 cur_pipe;
1351         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1352         u32 cur_backend = 0;
1353         u32 i;
1354         bool force_no_swizzle;
1355
1356         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1357                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1358         if (num_tile_pipes < 1)
1359                 num_tile_pipes = 1;
1360         if (num_backends > EVERGREEN_MAX_BACKENDS)
1361                 num_backends = EVERGREEN_MAX_BACKENDS;
1362         if (num_backends < 1)
1363                 num_backends = 1;
1364
1365         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1366                 if (((backend_disable_mask >> i) & 1) == 0) {
1367                         enabled_backends_mask |= (1 << i);
1368                         ++enabled_backends_count;
1369                 }
1370                 if (enabled_backends_count == num_backends)
1371                         break;
1372         }
1373
1374         if (enabled_backends_count == 0) {
1375                 enabled_backends_mask = 1;
1376                 enabled_backends_count = 1;
1377         }
1378
1379         if (enabled_backends_count != num_backends)
1380                 num_backends = enabled_backends_count;
1381
1382         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1383         switch (rdev->family) {
1384         case CHIP_CEDAR:
1385         case CHIP_REDWOOD:
1386         case CHIP_PALM:
1387                 force_no_swizzle = false;
1388                 break;
1389         case CHIP_CYPRESS:
1390         case CHIP_HEMLOCK:
1391         case CHIP_JUNIPER:
1392         default:
1393                 force_no_swizzle = true;
1394                 break;
1395         }
1396         if (force_no_swizzle) {
1397                 bool last_backend_enabled = false;
1398
1399                 force_no_swizzle = false;
1400                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1401                         if (((enabled_backends_mask >> i) & 1) == 1) {
1402                                 if (last_backend_enabled)
1403                                         force_no_swizzle = true;
1404                                 last_backend_enabled = true;
1405                         } else
1406                                 last_backend_enabled = false;
1407                 }
1408         }
1409
1410         switch (num_tile_pipes) {
1411         case 1:
1412         case 3:
1413         case 5:
1414         case 7:
1415                 DRM_ERROR("odd number of pipes!\n");
1416                 break;
1417         case 2:
1418                 swizzle_pipe[0] = 0;
1419                 swizzle_pipe[1] = 1;
1420                 break;
1421         case 4:
1422                 if (force_no_swizzle) {
1423                         swizzle_pipe[0] = 0;
1424                         swizzle_pipe[1] = 1;
1425                         swizzle_pipe[2] = 2;
1426                         swizzle_pipe[3] = 3;
1427                 } else {
1428                         swizzle_pipe[0] = 0;
1429                         swizzle_pipe[1] = 2;
1430                         swizzle_pipe[2] = 1;
1431                         swizzle_pipe[3] = 3;
1432                 }
1433                 break;
1434         case 6:
1435                 if (force_no_swizzle) {
1436                         swizzle_pipe[0] = 0;
1437                         swizzle_pipe[1] = 1;
1438                         swizzle_pipe[2] = 2;
1439                         swizzle_pipe[3] = 3;
1440                         swizzle_pipe[4] = 4;
1441                         swizzle_pipe[5] = 5;
1442                 } else {
1443                         swizzle_pipe[0] = 0;
1444                         swizzle_pipe[1] = 2;
1445                         swizzle_pipe[2] = 4;
1446                         swizzle_pipe[3] = 1;
1447                         swizzle_pipe[4] = 3;
1448                         swizzle_pipe[5] = 5;
1449                 }
1450                 break;
1451         case 8:
1452                 if (force_no_swizzle) {
1453                         swizzle_pipe[0] = 0;
1454                         swizzle_pipe[1] = 1;
1455                         swizzle_pipe[2] = 2;
1456                         swizzle_pipe[3] = 3;
1457                         swizzle_pipe[4] = 4;
1458                         swizzle_pipe[5] = 5;
1459                         swizzle_pipe[6] = 6;
1460                         swizzle_pipe[7] = 7;
1461                 } else {
1462                         swizzle_pipe[0] = 0;
1463                         swizzle_pipe[1] = 2;
1464                         swizzle_pipe[2] = 4;
1465                         swizzle_pipe[3] = 6;
1466                         swizzle_pipe[4] = 1;
1467                         swizzle_pipe[5] = 3;
1468                         swizzle_pipe[6] = 5;
1469                         swizzle_pipe[7] = 7;
1470                 }
1471                 break;
1472         }
1473
1474         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1475                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1476                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1477
1478                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1479
1480                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1481         }
1482
1483         return backend_map;
1484 }
1485
1486 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1487 {
1488         u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1489
1490         tmp = RREG32(MC_SHARED_CHMAP);
1491         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1492         case 0:
1493         case 1:
1494         case 2:
1495         case 3:
1496         default:
1497                 /* default mapping */
1498                 mc_shared_chremap = 0x00fac688;
1499                 break;
1500         }
1501
1502         switch (rdev->family) {
1503         case CHIP_HEMLOCK:
1504         case CHIP_CYPRESS:
1505                 tcp_chan_steer_lo = 0x54763210;
1506                 tcp_chan_steer_hi = 0x0000ba98;
1507                 break;
1508         case CHIP_JUNIPER:
1509         case CHIP_REDWOOD:
1510         case CHIP_CEDAR:
1511         case CHIP_PALM:
1512         default:
1513                 tcp_chan_steer_lo = 0x76543210;
1514                 tcp_chan_steer_hi = 0x0000ba98;
1515                 break;
1516         }
1517
1518         WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1519         WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1520         WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1521 }
1522
1523 static void evergreen_gpu_init(struct radeon_device *rdev)
1524 {
1525         u32 cc_rb_backend_disable = 0;
1526         u32 cc_gc_shader_pipe_config;
1527         u32 gb_addr_config = 0;
1528         u32 mc_shared_chmap, mc_arb_ramcfg;
1529         u32 gb_backend_map;
1530         u32 grbm_gfx_index;
1531         u32 sx_debug_1;
1532         u32 smx_dc_ctl0;
1533         u32 sq_config;
1534         u32 sq_lds_resource_mgmt;
1535         u32 sq_gpr_resource_mgmt_1;
1536         u32 sq_gpr_resource_mgmt_2;
1537         u32 sq_gpr_resource_mgmt_3;
1538         u32 sq_thread_resource_mgmt;
1539         u32 sq_thread_resource_mgmt_2;
1540         u32 sq_stack_resource_mgmt_1;
1541         u32 sq_stack_resource_mgmt_2;
1542         u32 sq_stack_resource_mgmt_3;
1543         u32 vgt_cache_invalidation;
1544         u32 hdp_host_path_cntl;
1545         int i, j, num_shader_engines, ps_thread_count;
1546
1547         switch (rdev->family) {
1548         case CHIP_CYPRESS:
1549         case CHIP_HEMLOCK:
1550                 rdev->config.evergreen.num_ses = 2;
1551                 rdev->config.evergreen.max_pipes = 4;
1552                 rdev->config.evergreen.max_tile_pipes = 8;
1553                 rdev->config.evergreen.max_simds = 10;
1554                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1555                 rdev->config.evergreen.max_gprs = 256;
1556                 rdev->config.evergreen.max_threads = 248;
1557                 rdev->config.evergreen.max_gs_threads = 32;
1558                 rdev->config.evergreen.max_stack_entries = 512;
1559                 rdev->config.evergreen.sx_num_of_sets = 4;
1560                 rdev->config.evergreen.sx_max_export_size = 256;
1561                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1562                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1563                 rdev->config.evergreen.max_hw_contexts = 8;
1564                 rdev->config.evergreen.sq_num_cf_insts = 2;
1565
1566                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1567                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1568                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1569                 break;
1570         case CHIP_JUNIPER:
1571                 rdev->config.evergreen.num_ses = 1;
1572                 rdev->config.evergreen.max_pipes = 4;
1573                 rdev->config.evergreen.max_tile_pipes = 4;
1574                 rdev->config.evergreen.max_simds = 10;
1575                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1576                 rdev->config.evergreen.max_gprs = 256;
1577                 rdev->config.evergreen.max_threads = 248;
1578                 rdev->config.evergreen.max_gs_threads = 32;
1579                 rdev->config.evergreen.max_stack_entries = 512;
1580                 rdev->config.evergreen.sx_num_of_sets = 4;
1581                 rdev->config.evergreen.sx_max_export_size = 256;
1582                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1583                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1584                 rdev->config.evergreen.max_hw_contexts = 8;
1585                 rdev->config.evergreen.sq_num_cf_insts = 2;
1586
1587                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1588                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1589                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1590                 break;
1591         case CHIP_REDWOOD:
1592                 rdev->config.evergreen.num_ses = 1;
1593                 rdev->config.evergreen.max_pipes = 4;
1594                 rdev->config.evergreen.max_tile_pipes = 4;
1595                 rdev->config.evergreen.max_simds = 5;
1596                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1597                 rdev->config.evergreen.max_gprs = 256;
1598                 rdev->config.evergreen.max_threads = 248;
1599                 rdev->config.evergreen.max_gs_threads = 32;
1600                 rdev->config.evergreen.max_stack_entries = 256;
1601                 rdev->config.evergreen.sx_num_of_sets = 4;
1602                 rdev->config.evergreen.sx_max_export_size = 256;
1603                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1604                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1605                 rdev->config.evergreen.max_hw_contexts = 8;
1606                 rdev->config.evergreen.sq_num_cf_insts = 2;
1607
1608                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1609                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1610                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1611                 break;
1612         case CHIP_CEDAR:
1613         default:
1614                 rdev->config.evergreen.num_ses = 1;
1615                 rdev->config.evergreen.max_pipes = 2;
1616                 rdev->config.evergreen.max_tile_pipes = 2;
1617                 rdev->config.evergreen.max_simds = 2;
1618                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1619                 rdev->config.evergreen.max_gprs = 256;
1620                 rdev->config.evergreen.max_threads = 192;
1621                 rdev->config.evergreen.max_gs_threads = 16;
1622                 rdev->config.evergreen.max_stack_entries = 256;
1623                 rdev->config.evergreen.sx_num_of_sets = 4;
1624                 rdev->config.evergreen.sx_max_export_size = 128;
1625                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1626                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1627                 rdev->config.evergreen.max_hw_contexts = 4;
1628                 rdev->config.evergreen.sq_num_cf_insts = 1;
1629
1630                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1631                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1632                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1633                 break;
1634         case CHIP_PALM:
1635                 rdev->config.evergreen.num_ses = 1;
1636                 rdev->config.evergreen.max_pipes = 2;
1637                 rdev->config.evergreen.max_tile_pipes = 2;
1638                 rdev->config.evergreen.max_simds = 2;
1639                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1640                 rdev->config.evergreen.max_gprs = 256;
1641                 rdev->config.evergreen.max_threads = 192;
1642                 rdev->config.evergreen.max_gs_threads = 16;
1643                 rdev->config.evergreen.max_stack_entries = 256;
1644                 rdev->config.evergreen.sx_num_of_sets = 4;
1645                 rdev->config.evergreen.sx_max_export_size = 128;
1646                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1647                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1648                 rdev->config.evergreen.max_hw_contexts = 4;
1649                 rdev->config.evergreen.sq_num_cf_insts = 1;
1650
1651                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1652                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1653                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1654                 break;
1655         }
1656
1657         /* Initialize HDP */
1658         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1659                 WREG32((0x2c14 + j), 0x00000000);
1660                 WREG32((0x2c18 + j), 0x00000000);
1661                 WREG32((0x2c1c + j), 0x00000000);
1662                 WREG32((0x2c20 + j), 0x00000000);
1663                 WREG32((0x2c24 + j), 0x00000000);
1664         }
1665
1666         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1667
1668         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1669
1670         cc_gc_shader_pipe_config |=
1671                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1672                                   & EVERGREEN_MAX_PIPES_MASK);
1673         cc_gc_shader_pipe_config |=
1674                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1675                                & EVERGREEN_MAX_SIMDS_MASK);
1676
1677         cc_rb_backend_disable =
1678                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1679                                 & EVERGREEN_MAX_BACKENDS_MASK);
1680
1681
1682         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1683         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1684
1685         switch (rdev->config.evergreen.max_tile_pipes) {
1686         case 1:
1687         default:
1688                 gb_addr_config |= NUM_PIPES(0);
1689                 break;
1690         case 2:
1691                 gb_addr_config |= NUM_PIPES(1);
1692                 break;
1693         case 4:
1694                 gb_addr_config |= NUM_PIPES(2);
1695                 break;
1696         case 8:
1697                 gb_addr_config |= NUM_PIPES(3);
1698                 break;
1699         }
1700
1701         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1702         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1703         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1704         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1705         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1706         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1707
1708         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1709                 gb_addr_config |= ROW_SIZE(2);
1710         else
1711                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1712
1713         if (rdev->ddev->pdev->device == 0x689e) {
1714                 u32 efuse_straps_4;
1715                 u32 efuse_straps_3;
1716                 u8 efuse_box_bit_131_124;
1717
1718                 WREG32(RCU_IND_INDEX, 0x204);
1719                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1720                 WREG32(RCU_IND_INDEX, 0x203);
1721                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1722                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1723
1724                 switch(efuse_box_bit_131_124) {
1725                 case 0x00:
1726                         gb_backend_map = 0x76543210;
1727                         break;
1728                 case 0x55:
1729                         gb_backend_map = 0x77553311;
1730                         break;
1731                 case 0x56:
1732                         gb_backend_map = 0x77553300;
1733                         break;
1734                 case 0x59:
1735                         gb_backend_map = 0x77552211;
1736                         break;
1737                 case 0x66:
1738                         gb_backend_map = 0x77443300;
1739                         break;
1740                 case 0x99:
1741                         gb_backend_map = 0x66552211;
1742                         break;
1743                 case 0x5a:
1744                         gb_backend_map = 0x77552200;
1745                         break;
1746                 case 0xaa:
1747                         gb_backend_map = 0x66442200;
1748                         break;
1749                 case 0x95:
1750                         gb_backend_map = 0x66553311;
1751                         break;
1752                 default:
1753                         DRM_ERROR("bad backend map, using default\n");
1754                         gb_backend_map =
1755                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1756                                                                        rdev->config.evergreen.max_tile_pipes,
1757                                                                        rdev->config.evergreen.max_backends,
1758                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1759                                                                    rdev->config.evergreen.max_backends) &
1760                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1761                         break;
1762                 }
1763         } else if (rdev->ddev->pdev->device == 0x68b9) {
1764                 u32 efuse_straps_3;
1765                 u8 efuse_box_bit_127_124;
1766
1767                 WREG32(RCU_IND_INDEX, 0x203);
1768                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1769                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1770
1771                 switch(efuse_box_bit_127_124) {
1772                 case 0x0:
1773                         gb_backend_map = 0x00003210;
1774                         break;
1775                 case 0x5:
1776                 case 0x6:
1777                 case 0x9:
1778                 case 0xa:
1779                         gb_backend_map = 0x00003311;
1780                         break;
1781                 default:
1782                         DRM_ERROR("bad backend map, using default\n");
1783                         gb_backend_map =
1784                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1785                                                                        rdev->config.evergreen.max_tile_pipes,
1786                                                                        rdev->config.evergreen.max_backends,
1787                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1788                                                                    rdev->config.evergreen.max_backends) &
1789                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1790                         break;
1791                 }
1792         } else {
1793                 switch (rdev->family) {
1794                 case CHIP_CYPRESS:
1795                 case CHIP_HEMLOCK:
1796                         gb_backend_map = 0x66442200;
1797                         break;
1798                 case CHIP_JUNIPER:
1799                         gb_backend_map = 0x00006420;
1800                         break;
1801                 default:
1802                         gb_backend_map =
1803                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1804                                                                        rdev->config.evergreen.max_tile_pipes,
1805                                                                        rdev->config.evergreen.max_backends,
1806                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1807                                                                          rdev->config.evergreen.max_backends) &
1808                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1809                 }
1810         }
1811
1812         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1813          * not have bank info, so create a custom tiling dword.
1814          * bits 3:0   num_pipes
1815          * bits 7:4   num_banks
1816          * bits 11:8  group_size
1817          * bits 15:12 row_size
1818          */
1819         rdev->config.evergreen.tile_config = 0;
1820         switch (rdev->config.evergreen.max_tile_pipes) {
1821         case 1:
1822         default:
1823                 rdev->config.evergreen.tile_config |= (0 << 0);
1824                 break;
1825         case 2:
1826                 rdev->config.evergreen.tile_config |= (1 << 0);
1827                 break;
1828         case 4:
1829                 rdev->config.evergreen.tile_config |= (2 << 0);
1830                 break;
1831         case 8:
1832                 rdev->config.evergreen.tile_config |= (3 << 0);
1833                 break;
1834         }
1835         rdev->config.evergreen.tile_config |=
1836                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1837         rdev->config.evergreen.tile_config |=
1838                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1839         rdev->config.evergreen.tile_config |=
1840                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1841
1842         WREG32(GB_BACKEND_MAP, gb_backend_map);
1843         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1844         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1845         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1846
1847         evergreen_program_channel_remap(rdev);
1848
1849         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1850         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1851
1852         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1853                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1854                 u32 sp = cc_gc_shader_pipe_config;
1855                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1856
1857                 if (i == num_shader_engines) {
1858                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1859                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1860                 }
1861
1862                 WREG32(GRBM_GFX_INDEX, gfx);
1863                 WREG32(RLC_GFX_INDEX, gfx);
1864
1865                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1866                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1867                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1868                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1869         }
1870
1871         grbm_gfx_index |= SE_BROADCAST_WRITES;
1872         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1873         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1874
1875         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1876         WREG32(CGTS_TCC_DISABLE, 0);
1877         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1878         WREG32(CGTS_USER_TCC_DISABLE, 0);
1879
1880         /* set HW defaults for 3D engine */
1881         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1882                                      ROQ_IB2_START(0x2b)));
1883
1884         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1885
1886         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1887                              SYNC_GRADIENT |
1888                              SYNC_WALKER |
1889                              SYNC_ALIGNER));
1890
1891         sx_debug_1 = RREG32(SX_DEBUG_1);
1892         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1893         WREG32(SX_DEBUG_1, sx_debug_1);
1894
1895
1896         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1897         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1898         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1899         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1900
1901         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1902                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1903                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1904
1905         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1906                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1907                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1908
1909         WREG32(VGT_NUM_INSTANCES, 1);
1910         WREG32(SPI_CONFIG_CNTL, 0);
1911         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1912         WREG32(CP_PERFMON_CNTL, 0);
1913
1914         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1915                                   FETCH_FIFO_HIWATER(0x4) |
1916                                   DONE_FIFO_HIWATER(0xe0) |
1917                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
1918
1919         sq_config = RREG32(SQ_CONFIG);
1920         sq_config &= ~(PS_PRIO(3) |
1921                        VS_PRIO(3) |
1922                        GS_PRIO(3) |
1923                        ES_PRIO(3));
1924         sq_config |= (VC_ENABLE |
1925                       EXPORT_SRC_C |
1926                       PS_PRIO(0) |
1927                       VS_PRIO(1) |
1928                       GS_PRIO(2) |
1929                       ES_PRIO(3));
1930
1931         switch (rdev->family) {
1932         case CHIP_CEDAR:
1933         case CHIP_PALM:
1934                 /* no vertex cache */
1935                 sq_config &= ~VC_ENABLE;
1936                 break;
1937         default:
1938                 break;
1939         }
1940
1941         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1942
1943         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1944         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1945         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1946         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1947         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1948         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1949         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1950
1951         switch (rdev->family) {
1952         case CHIP_CEDAR:
1953         case CHIP_PALM:
1954                 ps_thread_count = 96;
1955                 break;
1956         default:
1957                 ps_thread_count = 128;
1958                 break;
1959         }
1960
1961         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1962         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1963         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1964         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1965         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1966         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1967
1968         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1969         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1970         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1971         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1972         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1973         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1974
1975         WREG32(SQ_CONFIG, sq_config);
1976         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1977         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1978         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1979         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1980         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1981         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1982         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1983         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1984         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1985         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1986
1987         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1988                                           FORCE_EOV_MAX_REZ_CNT(255)));
1989
1990         switch (rdev->family) {
1991         case CHIP_CEDAR:
1992         case CHIP_PALM:
1993                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1994                 break;
1995         default:
1996                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1997                 break;
1998         }
1999         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2000         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2001
2002         WREG32(VGT_GS_VERTEX_REUSE, 16);
2003         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2004
2005         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2006         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2007
2008         WREG32(CB_PERF_CTR0_SEL_0, 0);
2009         WREG32(CB_PERF_CTR0_SEL_1, 0);
2010         WREG32(CB_PERF_CTR1_SEL_0, 0);
2011         WREG32(CB_PERF_CTR1_SEL_1, 0);
2012         WREG32(CB_PERF_CTR2_SEL_0, 0);
2013         WREG32(CB_PERF_CTR2_SEL_1, 0);
2014         WREG32(CB_PERF_CTR3_SEL_0, 0);
2015         WREG32(CB_PERF_CTR3_SEL_1, 0);
2016
2017         /* clear render buffer base addresses */
2018         WREG32(CB_COLOR0_BASE, 0);
2019         WREG32(CB_COLOR1_BASE, 0);
2020         WREG32(CB_COLOR2_BASE, 0);
2021         WREG32(CB_COLOR3_BASE, 0);
2022         WREG32(CB_COLOR4_BASE, 0);
2023         WREG32(CB_COLOR5_BASE, 0);
2024         WREG32(CB_COLOR6_BASE, 0);
2025         WREG32(CB_COLOR7_BASE, 0);
2026         WREG32(CB_COLOR8_BASE, 0);
2027         WREG32(CB_COLOR9_BASE, 0);
2028         WREG32(CB_COLOR10_BASE, 0);
2029         WREG32(CB_COLOR11_BASE, 0);
2030
2031         /* set the shader const cache sizes to 0 */
2032         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2033                 WREG32(i, 0);
2034         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2035                 WREG32(i, 0);
2036
2037         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2038         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2039
2040         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2041
2042         udelay(50);
2043
2044 }
2045
2046 int evergreen_mc_init(struct radeon_device *rdev)
2047 {
2048         u32 tmp;
2049         int chansize, numchan;
2050
2051         /* Get VRAM informations */
2052         rdev->mc.vram_is_ddr = true;
2053         tmp = RREG32(MC_ARB_RAMCFG);
2054         if (tmp & CHANSIZE_OVERRIDE) {
2055                 chansize = 16;
2056         } else if (tmp & CHANSIZE_MASK) {
2057                 chansize = 64;
2058         } else {
2059                 chansize = 32;
2060         }
2061         tmp = RREG32(MC_SHARED_CHMAP);
2062         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2063         case 0:
2064         default:
2065                 numchan = 1;
2066                 break;
2067         case 1:
2068                 numchan = 2;
2069                 break;
2070         case 2:
2071                 numchan = 4;
2072                 break;
2073         case 3:
2074                 numchan = 8;
2075                 break;
2076         }
2077         rdev->mc.vram_width = numchan * chansize;
2078         /* Could aper size report 0 ? */
2079         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2080         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2081         /* Setup GPU memory space */
2082         if (rdev->flags & RADEON_IS_IGP) {
2083                 /* size in bytes on fusion */
2084                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2085                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2086         } else {
2087                 /* size in MB on evergreen */
2088                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2089                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2090         }
2091         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2092         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2093         r700_vram_gtt_location(rdev, &rdev->mc);
2094         radeon_update_bandwidth_info(rdev);
2095
2096         return 0;
2097 }
2098
2099 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2100 {
2101         u32 srbm_status;
2102         u32 grbm_status;
2103         u32 grbm_status_se0, grbm_status_se1;
2104         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2105         int r;
2106
2107         srbm_status = RREG32(SRBM_STATUS);
2108         grbm_status = RREG32(GRBM_STATUS);
2109         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2110         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2111         if (!(grbm_status & GUI_ACTIVE)) {
2112                 r100_gpu_lockup_update(lockup, &rdev->cp);
2113                 return false;
2114         }
2115         /* force CP activities */
2116         r = radeon_ring_lock(rdev, 2);
2117         if (!r) {
2118                 /* PACKET2 NOP */
2119                 radeon_ring_write(rdev, 0x80000000);
2120                 radeon_ring_write(rdev, 0x80000000);
2121                 radeon_ring_unlock_commit(rdev);
2122         }
2123         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2124         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2125 }
2126
2127 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2128 {
2129         struct evergreen_mc_save save;
2130         u32 grbm_reset = 0;
2131
2132         dev_info(rdev->dev, "GPU softreset \n");
2133         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2134                 RREG32(GRBM_STATUS));
2135         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2136                 RREG32(GRBM_STATUS_SE0));
2137         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2138                 RREG32(GRBM_STATUS_SE1));
2139         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2140                 RREG32(SRBM_STATUS));
2141         evergreen_mc_stop(rdev, &save);
2142         if (evergreen_mc_wait_for_idle(rdev)) {
2143                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2144         }
2145         /* Disable CP parsing/prefetching */
2146         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2147
2148         /* reset all the gfx blocks */
2149         grbm_reset = (SOFT_RESET_CP |
2150                       SOFT_RESET_CB |
2151                       SOFT_RESET_DB |
2152                       SOFT_RESET_PA |
2153                       SOFT_RESET_SC |
2154                       SOFT_RESET_SPI |
2155                       SOFT_RESET_SH |
2156                       SOFT_RESET_SX |
2157                       SOFT_RESET_TC |
2158                       SOFT_RESET_TA |
2159                       SOFT_RESET_VC |
2160                       SOFT_RESET_VGT);
2161
2162         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2163         WREG32(GRBM_SOFT_RESET, grbm_reset);
2164         (void)RREG32(GRBM_SOFT_RESET);
2165         udelay(50);
2166         WREG32(GRBM_SOFT_RESET, 0);
2167         (void)RREG32(GRBM_SOFT_RESET);
2168         /* Wait a little for things to settle down */
2169         udelay(50);
2170         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2171                 RREG32(GRBM_STATUS));
2172         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2173                 RREG32(GRBM_STATUS_SE0));
2174         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2175                 RREG32(GRBM_STATUS_SE1));
2176         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2177                 RREG32(SRBM_STATUS));
2178         evergreen_mc_resume(rdev, &save);
2179         return 0;
2180 }
2181
2182 int evergreen_asic_reset(struct radeon_device *rdev)
2183 {
2184         return evergreen_gpu_soft_reset(rdev);
2185 }
2186
2187 /* Interrupts */
2188
2189 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2190 {
2191         switch (crtc) {
2192         case 0:
2193                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2194         case 1:
2195                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2196         case 2:
2197                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2198         case 3:
2199                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2200         case 4:
2201                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2202         case 5:
2203                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2204         default:
2205                 return 0;
2206         }
2207 }
2208
2209 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2210 {
2211         u32 tmp;
2212
2213         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2214         WREG32(GRBM_INT_CNTL, 0);
2215         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2216         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2217         if (!(rdev->flags & RADEON_IS_IGP)) {
2218                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2219                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2220                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2221                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2222         }
2223
2224         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2225         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2226         if (!(rdev->flags & RADEON_IS_IGP)) {
2227                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2228                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2229                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2230                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2231         }
2232
2233         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2234         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2235
2236         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2237         WREG32(DC_HPD1_INT_CONTROL, tmp);
2238         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2239         WREG32(DC_HPD2_INT_CONTROL, tmp);
2240         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2241         WREG32(DC_HPD3_INT_CONTROL, tmp);
2242         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2243         WREG32(DC_HPD4_INT_CONTROL, tmp);
2244         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2245         WREG32(DC_HPD5_INT_CONTROL, tmp);
2246         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2247         WREG32(DC_HPD6_INT_CONTROL, tmp);
2248
2249 }
2250
2251 int evergreen_irq_set(struct radeon_device *rdev)
2252 {
2253         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2254         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2255         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2256         u32 grbm_int_cntl = 0;
2257         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2258
2259         if (!rdev->irq.installed) {
2260                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2261                 return -EINVAL;
2262         }
2263         /* don't enable anything if the ih is disabled */
2264         if (!rdev->ih.enabled) {
2265                 r600_disable_interrupts(rdev);
2266                 /* force the active interrupt state to all disabled */
2267                 evergreen_disable_interrupt_state(rdev);
2268                 return 0;
2269         }
2270
2271         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2272         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2273         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2274         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2275         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2276         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2277
2278         if (rdev->irq.sw_int) {
2279                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2280                 cp_int_cntl |= RB_INT_ENABLE;
2281                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2282         }
2283         if (rdev->irq.crtc_vblank_int[0] ||
2284             rdev->irq.pflip[0]) {
2285                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2286                 crtc1 |= VBLANK_INT_MASK;
2287         }
2288         if (rdev->irq.crtc_vblank_int[1] ||
2289             rdev->irq.pflip[1]) {
2290                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2291                 crtc2 |= VBLANK_INT_MASK;
2292         }
2293         if (rdev->irq.crtc_vblank_int[2] ||
2294             rdev->irq.pflip[2]) {
2295                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2296                 crtc3 |= VBLANK_INT_MASK;
2297         }
2298         if (rdev->irq.crtc_vblank_int[3] ||
2299             rdev->irq.pflip[3]) {
2300                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2301                 crtc4 |= VBLANK_INT_MASK;
2302         }
2303         if (rdev->irq.crtc_vblank_int[4] ||
2304             rdev->irq.pflip[4]) {
2305                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2306                 crtc5 |= VBLANK_INT_MASK;
2307         }
2308         if (rdev->irq.crtc_vblank_int[5] ||
2309             rdev->irq.pflip[5]) {
2310                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2311                 crtc6 |= VBLANK_INT_MASK;
2312         }
2313         if (rdev->irq.hpd[0]) {
2314                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2315                 hpd1 |= DC_HPDx_INT_EN;
2316         }
2317         if (rdev->irq.hpd[1]) {
2318                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2319                 hpd2 |= DC_HPDx_INT_EN;
2320         }
2321         if (rdev->irq.hpd[2]) {
2322                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2323                 hpd3 |= DC_HPDx_INT_EN;
2324         }
2325         if (rdev->irq.hpd[3]) {
2326                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2327                 hpd4 |= DC_HPDx_INT_EN;
2328         }
2329         if (rdev->irq.hpd[4]) {
2330                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2331                 hpd5 |= DC_HPDx_INT_EN;
2332         }
2333         if (rdev->irq.hpd[5]) {
2334                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2335                 hpd6 |= DC_HPDx_INT_EN;
2336         }
2337         if (rdev->irq.gui_idle) {
2338                 DRM_DEBUG("gui idle\n");
2339                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2340         }
2341
2342         WREG32(CP_INT_CNTL, cp_int_cntl);
2343         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2344
2345         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2346         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2347         if (!(rdev->flags & RADEON_IS_IGP)) {
2348                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2349                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2350                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2351                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2352         }
2353
2354         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2355         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2356         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2357         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2358         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2359         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2360
2361         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2362         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2363         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2364         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2365         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2366         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2367
2368         return 0;
2369 }
2370
2371 static inline void evergreen_irq_ack(struct radeon_device *rdev)
2372 {
2373         u32 tmp;
2374
2375         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2376         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2377         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2378         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2379         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2380         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2381         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2382         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2383         rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2384         rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2385         rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2386         rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2387
2388         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2389                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2390         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2391                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2392         if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2393                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2394         if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2395                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2396         if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2397                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2398         if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2399                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2400
2401         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2402                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2403         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2404                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2405
2406         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2407                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2408         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2409                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2410
2411         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2412                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2413         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2414                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2415
2416         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2417                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2418         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2419                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2420
2421         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2422                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2423         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2424                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2425
2426         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2427                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2428         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2429                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2430
2431         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2432                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2433                 tmp |= DC_HPDx_INT_ACK;
2434                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2435         }
2436         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2437                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2438                 tmp |= DC_HPDx_INT_ACK;
2439                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2440         }
2441         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2442                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2443                 tmp |= DC_HPDx_INT_ACK;
2444                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2445         }
2446         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2447                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2448                 tmp |= DC_HPDx_INT_ACK;
2449                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2450         }
2451         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2452                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2453                 tmp |= DC_HPDx_INT_ACK;
2454                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2455         }
2456         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2457                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2458                 tmp |= DC_HPDx_INT_ACK;
2459                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2460         }
2461 }
2462
2463 void evergreen_irq_disable(struct radeon_device *rdev)
2464 {
2465         r600_disable_interrupts(rdev);
2466         /* Wait and acknowledge irq */
2467         mdelay(1);
2468         evergreen_irq_ack(rdev);
2469         evergreen_disable_interrupt_state(rdev);
2470 }
2471
2472 static void evergreen_irq_suspend(struct radeon_device *rdev)
2473 {
2474         evergreen_irq_disable(rdev);
2475         r600_rlc_stop(rdev);
2476 }
2477
2478 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2479 {
2480         u32 wptr, tmp;
2481
2482         if (rdev->wb.enabled)
2483                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2484         else
2485                 wptr = RREG32(IH_RB_WPTR);
2486
2487         if (wptr & RB_OVERFLOW) {
2488                 /* When a ring buffer overflow happen start parsing interrupt
2489                  * from the last not overwritten vector (wptr + 16). Hopefully
2490                  * this should allow us to catchup.
2491                  */
2492                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2493                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2494                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2495                 tmp = RREG32(IH_RB_CNTL);
2496                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2497                 WREG32(IH_RB_CNTL, tmp);
2498         }
2499         return (wptr & rdev->ih.ptr_mask);
2500 }
2501
2502 int evergreen_irq_process(struct radeon_device *rdev)
2503 {
2504         u32 wptr = evergreen_get_ih_wptr(rdev);
2505         u32 rptr = rdev->ih.rptr;
2506         u32 src_id, src_data;
2507         u32 ring_index;
2508         unsigned long flags;
2509         bool queue_hotplug = false;
2510
2511         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2512         if (!rdev->ih.enabled)
2513                 return IRQ_NONE;
2514
2515         spin_lock_irqsave(&rdev->ih.lock, flags);
2516
2517         if (rptr == wptr) {
2518                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2519                 return IRQ_NONE;
2520         }
2521         if (rdev->shutdown) {
2522                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2523                 return IRQ_NONE;
2524         }
2525
2526 restart_ih:
2527         /* display interrupts */
2528         evergreen_irq_ack(rdev);
2529
2530         rdev->ih.wptr = wptr;
2531         while (rptr != wptr) {
2532                 /* wptr/rptr are in bytes! */
2533                 ring_index = rptr / 4;
2534                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2535                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2536
2537                 switch (src_id) {
2538                 case 1: /* D1 vblank/vline */
2539                         switch (src_data) {
2540                         case 0: /* D1 vblank */
2541                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2542                                         if (rdev->irq.crtc_vblank_int[0]) {
2543                                                 drm_handle_vblank(rdev->ddev, 0);
2544                                                 rdev->pm.vblank_sync = true;
2545                                                 wake_up(&rdev->irq.vblank_queue);
2546                                         }
2547                                         if (rdev->irq.pflip[0])
2548                                                 radeon_crtc_handle_flip(rdev, 0);
2549                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2550                                         DRM_DEBUG("IH: D1 vblank\n");
2551                                 }
2552                                 break;
2553                         case 1: /* D1 vline */
2554                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2555                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2556                                         DRM_DEBUG("IH: D1 vline\n");
2557                                 }
2558                                 break;
2559                         default:
2560                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2561                                 break;
2562                         }
2563                         break;
2564                 case 2: /* D2 vblank/vline */
2565                         switch (src_data) {
2566                         case 0: /* D2 vblank */
2567                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2568                                         if (rdev->irq.crtc_vblank_int[1]) {
2569                                                 drm_handle_vblank(rdev->ddev, 1);
2570                                                 rdev->pm.vblank_sync = true;
2571                                                 wake_up(&rdev->irq.vblank_queue);
2572                                         }
2573                                         if (rdev->irq.pflip[1])
2574                                                 radeon_crtc_handle_flip(rdev, 1);
2575                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2576                                         DRM_DEBUG("IH: D2 vblank\n");
2577                                 }
2578                                 break;
2579                         case 1: /* D2 vline */
2580                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2581                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2582                                         DRM_DEBUG("IH: D2 vline\n");
2583                                 }
2584                                 break;
2585                         default:
2586                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2587                                 break;
2588                         }
2589                         break;
2590                 case 3: /* D3 vblank/vline */
2591                         switch (src_data) {
2592                         case 0: /* D3 vblank */
2593                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2594                                         if (rdev->irq.crtc_vblank_int[2]) {
2595                                                 drm_handle_vblank(rdev->ddev, 2);
2596                                                 rdev->pm.vblank_sync = true;
2597                                                 wake_up(&rdev->irq.vblank_queue);
2598                                         }
2599                                         if (rdev->irq.pflip[2])
2600                                                 radeon_crtc_handle_flip(rdev, 2);
2601                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2602                                         DRM_DEBUG("IH: D3 vblank\n");
2603                                 }
2604                                 break;
2605                         case 1: /* D3 vline */
2606                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2607                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2608                                         DRM_DEBUG("IH: D3 vline\n");
2609                                 }
2610                                 break;
2611                         default:
2612                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2613                                 break;
2614                         }
2615                         break;
2616                 case 4: /* D4 vblank/vline */
2617                         switch (src_data) {
2618                         case 0: /* D4 vblank */
2619                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2620                                         if (rdev->irq.crtc_vblank_int[3]) {
2621                                                 drm_handle_vblank(rdev->ddev, 3);
2622                                                 rdev->pm.vblank_sync = true;
2623                                                 wake_up(&rdev->irq.vblank_queue);
2624                                         }
2625                                         if (rdev->irq.pflip[3])
2626                                                 radeon_crtc_handle_flip(rdev, 3);
2627                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2628                                         DRM_DEBUG("IH: D4 vblank\n");
2629                                 }
2630                                 break;
2631                         case 1: /* D4 vline */
2632                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2633                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2634                                         DRM_DEBUG("IH: D4 vline\n");
2635                                 }
2636                                 break;
2637                         default:
2638                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2639                                 break;
2640                         }
2641                         break;
2642                 case 5: /* D5 vblank/vline */
2643                         switch (src_data) {
2644                         case 0: /* D5 vblank */
2645                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2646                                         if (rdev->irq.crtc_vblank_int[4]) {
2647                                                 drm_handle_vblank(rdev->ddev, 4);
2648                                                 rdev->pm.vblank_sync = true;
2649                                                 wake_up(&rdev->irq.vblank_queue);
2650                                         }
2651                                         if (rdev->irq.pflip[4])
2652                                                 radeon_crtc_handle_flip(rdev, 4);
2653                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2654                                         DRM_DEBUG("IH: D5 vblank\n");
2655                                 }
2656                                 break;
2657                         case 1: /* D5 vline */
2658                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2659                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2660                                         DRM_DEBUG("IH: D5 vline\n");
2661                                 }
2662                                 break;
2663                         default:
2664                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2665                                 break;
2666                         }
2667                         break;
2668                 case 6: /* D6 vblank/vline */
2669                         switch (src_data) {
2670                         case 0: /* D6 vblank */
2671                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2672                                         if (rdev->irq.crtc_vblank_int[5]) {
2673                                                 drm_handle_vblank(rdev->ddev, 5);
2674                                                 rdev->pm.vblank_sync = true;
2675                                                 wake_up(&rdev->irq.vblank_queue);
2676                                         }
2677                                         if (rdev->irq.pflip[5])
2678                                                 radeon_crtc_handle_flip(rdev, 5);
2679                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2680                                         DRM_DEBUG("IH: D6 vblank\n");
2681                                 }
2682                                 break;
2683                         case 1: /* D6 vline */
2684                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2685                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2686                                         DRM_DEBUG("IH: D6 vline\n");
2687                                 }
2688                                 break;
2689                         default:
2690                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2691                                 break;
2692                         }
2693                         break;
2694                 case 42: /* HPD hotplug */
2695                         switch (src_data) {
2696                         case 0:
2697                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2698                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2699                                         queue_hotplug = true;
2700                                         DRM_DEBUG("IH: HPD1\n");
2701                                 }
2702                                 break;
2703                         case 1:
2704                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2705                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2706                                         queue_hotplug = true;
2707                                         DRM_DEBUG("IH: HPD2\n");
2708                                 }
2709                                 break;
2710                         case 2:
2711                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2712                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2713                                         queue_hotplug = true;
2714                                         DRM_DEBUG("IH: HPD3\n");
2715                                 }
2716                                 break;
2717                         case 3:
2718                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2719                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2720                                         queue_hotplug = true;
2721                                         DRM_DEBUG("IH: HPD4\n");
2722                                 }
2723                                 break;
2724                         case 4:
2725                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2726                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2727                                         queue_hotplug = true;
2728                                         DRM_DEBUG("IH: HPD5\n");
2729                                 }
2730                                 break;
2731                         case 5:
2732                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2733                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2734                                         queue_hotplug = true;
2735                                         DRM_DEBUG("IH: HPD6\n");
2736                                 }
2737                                 break;
2738                         default:
2739                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2740                                 break;
2741                         }
2742                         break;
2743                 case 176: /* CP_INT in ring buffer */
2744                 case 177: /* CP_INT in IB1 */
2745                 case 178: /* CP_INT in IB2 */
2746                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2747                         radeon_fence_process(rdev);
2748                         break;
2749                 case 181: /* CP EOP event */
2750                         DRM_DEBUG("IH: CP EOP\n");
2751                         radeon_fence_process(rdev);
2752                         break;
2753                 case 233: /* GUI IDLE */
2754                         DRM_DEBUG("IH: CP EOP\n");
2755                         rdev->pm.gui_idle = true;
2756                         wake_up(&rdev->irq.idle_queue);
2757                         break;
2758                 default:
2759                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2760                         break;
2761                 }
2762
2763                 /* wptr/rptr are in bytes! */
2764                 rptr += 16;
2765                 rptr &= rdev->ih.ptr_mask;
2766         }
2767         /* make sure wptr hasn't changed while processing */
2768         wptr = evergreen_get_ih_wptr(rdev);
2769         if (wptr != rdev->ih.wptr)
2770                 goto restart_ih;
2771         if (queue_hotplug)
2772                 schedule_work(&rdev->hotplug_work);
2773         rdev->ih.rptr = rptr;
2774         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2775         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2776         return IRQ_HANDLED;
2777 }
2778
2779 static int evergreen_startup(struct radeon_device *rdev)
2780 {
2781         int r;
2782
2783         /* enable pcie gen2 link */
2784         evergreen_pcie_gen2_enable(rdev);
2785
2786         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2787                 r = r600_init_microcode(rdev);
2788                 if (r) {
2789                         DRM_ERROR("Failed to load firmware!\n");
2790                         return r;
2791                 }
2792         }
2793
2794         evergreen_mc_program(rdev);
2795         if (rdev->flags & RADEON_IS_AGP) {
2796                 evergreen_agp_enable(rdev);
2797         } else {
2798                 r = evergreen_pcie_gart_enable(rdev);
2799                 if (r)
2800                         return r;
2801         }
2802         evergreen_gpu_init(rdev);
2803
2804         r = evergreen_blit_init(rdev);
2805         if (r) {
2806                 evergreen_blit_fini(rdev);
2807                 rdev->asic->copy = NULL;
2808                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2809         }
2810         /* XXX: ontario has problems blitting to gart at the moment */
2811         if (rdev->family == CHIP_PALM) {
2812                 rdev->asic->copy = NULL;
2813                 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2814         }
2815
2816         /* allocate wb buffer */
2817         r = radeon_wb_init(rdev);
2818         if (r)
2819                 return r;
2820
2821         /* Enable IRQ */
2822         r = r600_irq_init(rdev);
2823         if (r) {
2824                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2825                 radeon_irq_kms_fini(rdev);
2826                 return r;
2827         }
2828         evergreen_irq_set(rdev);
2829
2830         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2831         if (r)
2832                 return r;
2833         r = evergreen_cp_load_microcode(rdev);
2834         if (r)
2835                 return r;
2836         r = evergreen_cp_resume(rdev);
2837         if (r)
2838                 return r;
2839
2840         return 0;
2841 }
2842
2843 int evergreen_resume(struct radeon_device *rdev)
2844 {
2845         int r;
2846
2847         /* reset the asic, the gfx blocks are often in a bad state
2848          * after the driver is unloaded or after a resume
2849          */
2850         if (radeon_asic_reset(rdev))
2851                 dev_warn(rdev->dev, "GPU reset failed !\n");
2852         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2853          * posting will perform necessary task to bring back GPU into good
2854          * shape.
2855          */
2856         /* post card */
2857         atom_asic_init(rdev->mode_info.atom_context);
2858
2859         r = evergreen_startup(rdev);
2860         if (r) {
2861                 DRM_ERROR("r600 startup failed on resume\n");
2862                 return r;
2863         }
2864
2865         r = r600_ib_test(rdev);
2866         if (r) {
2867                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2868                 return r;
2869         }
2870
2871         return r;
2872
2873 }
2874
2875 int evergreen_suspend(struct radeon_device *rdev)
2876 {
2877         int r;
2878
2879         /* FIXME: we should wait for ring to be empty */
2880         r700_cp_stop(rdev);
2881         rdev->cp.ready = false;
2882         evergreen_irq_suspend(rdev);
2883         radeon_wb_disable(rdev);
2884         evergreen_pcie_gart_disable(rdev);
2885
2886         /* unpin shaders bo */
2887         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2888         if (likely(r == 0)) {
2889                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2890                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2891         }
2892
2893         return 0;
2894 }
2895
2896 int evergreen_copy_blit(struct radeon_device *rdev,
2897                         uint64_t src_offset, uint64_t dst_offset,
2898                         unsigned num_pages, struct radeon_fence *fence)
2899 {
2900         int r;
2901
2902         mutex_lock(&rdev->r600_blit.mutex);
2903         rdev->r600_blit.vb_ib = NULL;
2904         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2905         if (r) {
2906                 if (rdev->r600_blit.vb_ib)
2907                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2908                 mutex_unlock(&rdev->r600_blit.mutex);
2909                 return r;
2910         }
2911         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2912         evergreen_blit_done_copy(rdev, fence);
2913         mutex_unlock(&rdev->r600_blit.mutex);
2914         return 0;
2915 }
2916
2917 static bool evergreen_card_posted(struct radeon_device *rdev)
2918 {
2919         u32 reg;
2920
2921         /* first check CRTCs */
2922         if (rdev->flags & RADEON_IS_IGP)
2923                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2924                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2925         else
2926                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2927                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2928                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2929                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2930                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2931                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2932         if (reg & EVERGREEN_CRTC_MASTER_EN)
2933                 return true;
2934
2935         /* then check MEM_SIZE, in case the crtcs are off */
2936         if (RREG32(CONFIG_MEMSIZE))
2937                 return true;
2938
2939         return false;
2940 }
2941
2942 /* Plan is to move initialization in that function and use
2943  * helper function so that radeon_device_init pretty much
2944  * do nothing more than calling asic specific function. This
2945  * should also allow to remove a bunch of callback function
2946  * like vram_info.
2947  */
2948 int evergreen_init(struct radeon_device *rdev)
2949 {
2950         int r;
2951
2952         r = radeon_dummy_page_init(rdev);
2953         if (r)
2954                 return r;
2955         /* This don't do much */
2956         r = radeon_gem_init(rdev);
2957         if (r)
2958                 return r;
2959         /* Read BIOS */
2960         if (!radeon_get_bios(rdev)) {
2961                 if (ASIC_IS_AVIVO(rdev))
2962                         return -EINVAL;
2963         }
2964         /* Must be an ATOMBIOS */
2965         if (!rdev->is_atom_bios) {
2966                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2967                 return -EINVAL;
2968         }
2969         r = radeon_atombios_init(rdev);
2970         if (r)
2971                 return r;
2972         /* reset the asic, the gfx blocks are often in a bad state
2973          * after the driver is unloaded or after a resume
2974          */
2975         if (radeon_asic_reset(rdev))
2976                 dev_warn(rdev->dev, "GPU reset failed !\n");
2977         /* Post card if necessary */
2978         if (!evergreen_card_posted(rdev)) {
2979                 if (!rdev->bios) {
2980                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2981                         return -EINVAL;
2982                 }
2983                 DRM_INFO("GPU not posted. posting now...\n");
2984                 atom_asic_init(rdev->mode_info.atom_context);
2985         }
2986         /* Initialize scratch registers */
2987         r600_scratch_init(rdev);
2988         /* Initialize surface registers */
2989         radeon_surface_init(rdev);
2990         /* Initialize clocks */
2991         radeon_get_clock_info(rdev->ddev);
2992         /* Fence driver */
2993         r = radeon_fence_driver_init(rdev);
2994         if (r)
2995                 return r;
2996         /* initialize AGP */
2997         if (rdev->flags & RADEON_IS_AGP) {
2998                 r = radeon_agp_init(rdev);
2999                 if (r)
3000                         radeon_agp_disable(rdev);
3001         }
3002         /* initialize memory controller */
3003         r = evergreen_mc_init(rdev);
3004         if (r)
3005                 return r;
3006         /* Memory manager */
3007         r = radeon_bo_init(rdev);
3008         if (r)
3009                 return r;
3010
3011         r = radeon_irq_kms_init(rdev);
3012         if (r)
3013                 return r;
3014
3015         rdev->cp.ring_obj = NULL;
3016         r600_ring_init(rdev, 1024 * 1024);
3017
3018         rdev->ih.ring_obj = NULL;
3019         r600_ih_ring_init(rdev, 64 * 1024);
3020
3021         r = r600_pcie_gart_init(rdev);
3022         if (r)
3023                 return r;
3024
3025         rdev->accel_working = true;
3026         r = evergreen_startup(rdev);
3027         if (r) {
3028                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3029                 r700_cp_fini(rdev);
3030                 r600_irq_fini(rdev);
3031                 radeon_wb_fini(rdev);
3032                 radeon_irq_kms_fini(rdev);
3033                 evergreen_pcie_gart_fini(rdev);
3034                 rdev->accel_working = false;
3035         }
3036         if (rdev->accel_working) {
3037                 r = radeon_ib_pool_init(rdev);
3038                 if (r) {
3039                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3040                         rdev->accel_working = false;
3041                 }
3042                 r = r600_ib_test(rdev);
3043                 if (r) {
3044                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3045                         rdev->accel_working = false;
3046                 }
3047         }
3048         return 0;
3049 }
3050
3051 void evergreen_fini(struct radeon_device *rdev)
3052 {
3053         evergreen_blit_fini(rdev);
3054         r700_cp_fini(rdev);
3055         r600_irq_fini(rdev);
3056         radeon_wb_fini(rdev);
3057         radeon_irq_kms_fini(rdev);
3058         evergreen_pcie_gart_fini(rdev);
3059         radeon_gem_fini(rdev);
3060         radeon_fence_driver_fini(rdev);
3061         radeon_agp_fini(rdev);
3062         radeon_bo_fini(rdev);
3063         radeon_atombios_fini(rdev);
3064         kfree(rdev->bios);
3065         rdev->bios = NULL;
3066         radeon_dummy_page_fini(rdev);
3067 }
3068
3069 static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3070 {
3071         u32 link_width_cntl, speed_cntl;
3072
3073         if (rdev->flags & RADEON_IS_IGP)
3074                 return;
3075
3076         if (!(rdev->flags & RADEON_IS_PCIE))
3077                 return;
3078
3079         /* x2 cards have a special sequence */
3080         if (ASIC_IS_X2(rdev))
3081                 return;
3082
3083         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3084         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3085             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3086
3087                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3088                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3089                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3090
3091                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3092                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3093                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3094
3095                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3096                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3097                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3098
3099                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3100                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3101                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3102
3103                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3104                 speed_cntl |= LC_GEN2_EN_STRAP;
3105                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3106
3107         } else {
3108                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3109                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3110                 if (1)
3111                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3112                 else
3113                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3114                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3115         }
3116 }