drivers/gpu/drm/radeon/evergreen_cs.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include "evergreend.h"
  31 #include "evergreen_reg_safe.h"
  32 #include "cayman_reg_safe.h"
  33
  34 #define MAX(a,b)                   (((a)>(b))?(a):(b))
  35 #define MIN(a,b)                   (((a)<(b))?(a):(b))
  36
  37 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
  38                                           struct radeon_cs_reloc **cs_reloc);
  39
  40 struct evergreen_cs_track {
  41         u32                     group_size;
  42         u32                     nbanks;
  43         u32                     npipes;
  44         u32                     row_size;
  45         /* value we track */
  46         u32                     nsamples;               /* unused */
  47         struct radeon_bo        *cb_color_bo[12];
  48         u32                     cb_color_bo_offset[12];
  49         struct radeon_bo        *cb_color_fmask_bo[8];  /* unused */
  50         struct radeon_bo        *cb_color_cmask_bo[8];  /* unused */
  51         u32                     cb_color_info[12];
  52         u32                     cb_color_view[12];
  53         u32                     cb_color_pitch[12];
  54         u32                     cb_color_slice[12];
  55         u32                     cb_color_slice_idx[12];
  56         u32                     cb_color_attrib[12];
  57         u32                     cb_color_cmask_slice[8];/* unused */
  58         u32                     cb_color_fmask_slice[8];/* unused */
  59         u32                     cb_target_mask;
  60         u32                     cb_shader_mask; /* unused */
  61         u32                     vgt_strmout_config;
  62         u32                     vgt_strmout_buffer_config;
  63         struct radeon_bo        *vgt_strmout_bo[4];
  64         u32                     vgt_strmout_bo_offset[4];
  65         u32                     vgt_strmout_size[4];
  66         u32                     db_depth_control;
  67         u32                     db_depth_view;
  68         u32                     db_depth_slice;
  69         u32                     db_depth_size;
  70         u32                     db_z_info;
  71         u32                     db_z_read_offset;
  72         u32                     db_z_write_offset;
  73         struct radeon_bo        *db_z_read_bo;
  74         struct radeon_bo        *db_z_write_bo;
  75         u32                     db_s_info;
  76         u32                     db_s_read_offset;
  77         u32                     db_s_write_offset;
  78         struct radeon_bo        *db_s_read_bo;
  79         struct radeon_bo        *db_s_write_bo;
  80         bool                    sx_misc_kill_all_prims;
  81         bool                    cb_dirty;
  82         bool                    db_dirty;
  83         bool                    streamout_dirty;
  84         u32                     htile_offset;
  85         u32                     htile_surface;
  86         struct radeon_bo        *htile_bo;
  87 };
  88
  89 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
  90 {
  91         if (tiling_flags & RADEON_TILING_MACRO)
  92                 return ARRAY_2D_TILED_THIN1;
  93         else if (tiling_flags & RADEON_TILING_MICRO)
  94                 return ARRAY_1D_TILED_THIN1;
  95         else
  96                 return ARRAY_LINEAR_GENERAL;
  97 }
  98
  99 static u32 evergreen_cs_get_num_banks(u32 nbanks)
 100 {
 101         switch (nbanks) {
 102         case 2:
 103                 return ADDR_SURF_2_BANK;
 104         case 4:
 105                 return ADDR_SURF_4_BANK;
 106         case 8:
 107         default:
 108                 return ADDR_SURF_8_BANK;
 109         case 16:
 110                 return ADDR_SURF_16_BANK;
 111         }
 112 }
 113
 114 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
 115 {
 116         int i;
 117
 118         for (i = 0; i < 8; i++) {
 119                 track->cb_color_fmask_bo[i] = NULL;
 120                 track->cb_color_cmask_bo[i] = NULL;
 121                 track->cb_color_cmask_slice[i] = 0;
 122                 track->cb_color_fmask_slice[i] = 0;
 123         }
 124
 125         for (i = 0; i < 12; i++) {
 126                 track->cb_color_bo[i] = NULL;
 127                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 128                 track->cb_color_info[i] = 0;
 129                 track->cb_color_view[i] = 0xFFFFFFFF;
 130                 track->cb_color_pitch[i] = 0;
 131                 track->cb_color_slice[i] = 0xfffffff;
 132                 track->cb_color_slice_idx[i] = 0;
 133         }
 134         track->cb_target_mask = 0xFFFFFFFF;
 135         track->cb_shader_mask = 0xFFFFFFFF;
 136         track->cb_dirty = true;
 137
 138         track->db_depth_slice = 0xffffffff;
 139         track->db_depth_view = 0xFFFFC000;
 140         track->db_depth_size = 0xFFFFFFFF;
 141         track->db_depth_control = 0xFFFFFFFF;
 142         track->db_z_info = 0xFFFFFFFF;
 143         track->db_z_read_offset = 0xFFFFFFFF;
 144         track->db_z_write_offset = 0xFFFFFFFF;
 145         track->db_z_read_bo = NULL;
 146         track->db_z_write_bo = NULL;
 147         track->db_s_info = 0xFFFFFFFF;
 148         track->db_s_read_offset = 0xFFFFFFFF;
 149         track->db_s_write_offset = 0xFFFFFFFF;
 150         track->db_s_read_bo = NULL;
 151         track->db_s_write_bo = NULL;
 152         track->db_dirty = true;
 153         track->htile_bo = NULL;
 154         track->htile_offset = 0xFFFFFFFF;
 155         track->htile_surface = 0;
 156
 157         for (i = 0; i < 4; i++) {
 158                 track->vgt_strmout_size[i] = 0;
 159                 track->vgt_strmout_bo[i] = NULL;
 160                 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
 161         }
 162         track->streamout_dirty = true;
 163         track->sx_misc_kill_all_prims = false;
 164 }
 165
 166 struct eg_surface {
 167         /* value gathered from cs */
 168         unsigned        nbx;
 169         unsigned        nby;
 170         unsigned        format;
 171         unsigned        mode;
 172         unsigned        nbanks;
 173         unsigned        bankw;
 174         unsigned        bankh;
 175         unsigned        tsplit;
 176         unsigned        mtilea;
 177         unsigned        nsamples;
 178         /* output value */
 179         unsigned        bpe;
 180         unsigned        layer_size;
 181         unsigned        palign;
 182         unsigned        halign;
 183         unsigned long   base_align;
 184 };
 185
 186 static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
 187                                           struct eg_surface *surf,
 188                                           const char *prefix)
 189 {
 190         surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
 191         surf->base_align = surf->bpe;
 192         surf->palign = 1;
 193         surf->halign = 1;
 194         return 0;
 195 }
 196
 197 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
 198                                                   struct eg_surface *surf,
 199                                                   const char *prefix)
 200 {
 201         struct evergreen_cs_track *track = p->track;
 202         unsigned palign;
 203
 204         palign = MAX(64, track->group_size / surf->bpe);
 205         surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
 206         surf->base_align = track->group_size;
 207         surf->palign = palign;
 208         surf->halign = 1;
 209         if (surf->nbx & (palign - 1)) {
 210                 if (prefix) {
 211                         dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
 212                                  __func__, __LINE__, prefix, surf->nbx, palign);
 213                 }
 214                 return -EINVAL;
 215         }
 216         return 0;
 217 }
 218
 219 static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
 220                                       struct eg_surface *surf,
 221                                       const char *prefix)
 222 {
 223         struct evergreen_cs_track *track = p->track;
 224         unsigned palign;
 225
 226         palign = track->group_size / (8 * surf->bpe * surf->nsamples);
 227         palign = MAX(8, palign);
 228         surf->layer_size = surf->nbx * surf->nby * surf->bpe;
 229         surf->base_align = track->group_size;
 230         surf->palign = palign;
 231         surf->halign = 8;
 232         if ((surf->nbx & (palign - 1))) {
 233                 if (prefix) {
 234                         dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
 235                                  __func__, __LINE__, prefix, surf->nbx, palign,
 236                                  track->group_size, surf->bpe, surf->nsamples);
 237                 }
 238                 return -EINVAL;
 239         }
 240         if ((surf->nby & (8 - 1))) {
 241                 if (prefix) {
 242                         dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
 243                                  __func__, __LINE__, prefix, surf->nby);
 244                 }
 245                 return -EINVAL;
 246         }
 247         return 0;
 248 }
 249
 250 static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
 251                                       struct eg_surface *surf,
 252                                       const char *prefix)
 253 {
 254         struct evergreen_cs_track *track = p->track;
 255         unsigned palign, halign, tileb, slice_pt;
 256         unsigned mtile_pr, mtile_ps, mtileb;
 257
 258         tileb = 64 * surf->bpe * surf->nsamples;
 259         slice_pt = 1;
 260         if (tileb > surf->tsplit) {
 261                 slice_pt = tileb / surf->tsplit;
 262         }
 263         tileb = tileb / slice_pt;
 264         /* macro tile width & height */
 265         palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
 266         halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
 267         mtileb = (palign / 8) * (halign / 8) * tileb;
 268         mtile_pr = surf->nbx / palign;
 269         mtile_ps = (mtile_pr * surf->nby) / halign;
 270         surf->layer_size = mtile_ps * mtileb * slice_pt;
 271         surf->base_align = (palign / 8) * (halign / 8) * tileb;
 272         surf->palign = palign;
 273         surf->halign = halign;
 274
 275         if ((surf->nbx & (palign - 1))) {
 276                 if (prefix) {
 277                         dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
 278                                  __func__, __LINE__, prefix, surf->nbx, palign);
 279                 }
 280                 return -EINVAL;
 281         }
 282         if ((surf->nby & (halign - 1))) {
 283                 if (prefix) {
 284                         dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
 285                                  __func__, __LINE__, prefix, surf->nby, halign);
 286                 }
 287                 return -EINVAL;
 288         }
 289
 290         return 0;
 291 }
 292
 293 static int evergreen_surface_check(struct radeon_cs_parser *p,
 294                                    struct eg_surface *surf,
 295                                    const char *prefix)
 296 {
 297         /* some common value computed here */
 298         surf->bpe = r600_fmt_get_blocksize(surf->format);
 299
 300         switch (surf->mode) {
 301         case ARRAY_LINEAR_GENERAL:
 302                 return evergreen_surface_check_linear(p, surf, prefix);
 303         case ARRAY_LINEAR_ALIGNED:
 304                 return evergreen_surface_check_linear_aligned(p, surf, prefix);
 305         case ARRAY_1D_TILED_THIN1:
 306                 return evergreen_surface_check_1d(p, surf, prefix);
 307         case ARRAY_2D_TILED_THIN1:
 308                 return evergreen_surface_check_2d(p, surf, prefix);
 309         default:
 310                 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
 311                                 __func__, __LINE__, prefix, surf->mode);
 312                 return -EINVAL;
 313         }
 314         return -EINVAL;
 315 }
 316
 317 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
 318                                               struct eg_surface *surf,
 319                                               const char *prefix)
 320 {
 321         switch (surf->mode) {
 322         case ARRAY_2D_TILED_THIN1:
 323                 break;
 324         case ARRAY_LINEAR_GENERAL:
 325         case ARRAY_LINEAR_ALIGNED:
 326         case ARRAY_1D_TILED_THIN1:
 327                 return 0;
 328         default:
 329                 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
 330                                 __func__, __LINE__, prefix, surf->mode);
 331                 return -EINVAL;
 332         }
 333
 334         switch (surf->nbanks) {
 335         case 0: surf->nbanks = 2; break;
 336         case 1: surf->nbanks = 4; break;
 337         case 2: surf->nbanks = 8; break;
 338         case 3: surf->nbanks = 16; break;
 339         default:
 340                 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
 341                          __func__, __LINE__, prefix, surf->nbanks);
 342                 return -EINVAL;
 343         }
 344         switch (surf->bankw) {
 345         case 0: surf->bankw = 1; break;
 346         case 1: surf->bankw = 2; break;
 347         case 2: surf->bankw = 4; break;
 348         case 3: surf->bankw = 8; break;
 349         default:
 350                 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
 351                          __func__, __LINE__, prefix, surf->bankw);
 352                 return -EINVAL;
 353         }
 354         switch (surf->bankh) {
 355         case 0: surf->bankh = 1; break;
 356         case 1: surf->bankh = 2; break;
 357         case 2: surf->bankh = 4; break;
 358         case 3: surf->bankh = 8; break;
 359         default:
 360                 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
 361                          __func__, __LINE__, prefix, surf->bankh);
 362                 return -EINVAL;
 363         }
 364         switch (surf->mtilea) {
 365         case 0: surf->mtilea = 1; break;
 366         case 1: surf->mtilea = 2; break;
 367         case 2: surf->mtilea = 4; break;
 368         case 3: surf->mtilea = 8; break;
 369         default:
 370                 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
 371                          __func__, __LINE__, prefix, surf->mtilea);
 372                 return -EINVAL;
 373         }
 374         switch (surf->tsplit) {
 375         case 0: surf->tsplit = 64; break;
 376         case 1: surf->tsplit = 128; break;
 377         case 2: surf->tsplit = 256; break;
 378         case 3: surf->tsplit = 512; break;
 379         case 4: surf->tsplit = 1024; break;
 380         case 5: surf->tsplit = 2048; break;
 381         case 6: surf->tsplit = 4096; break;
 382         default:
 383                 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
 384                          __func__, __LINE__, prefix, surf->tsplit);
 385                 return -EINVAL;
 386         }
 387         return 0;
 388 }
 389
 390 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
 391 {
 392         struct evergreen_cs_track *track = p->track;
 393         struct eg_surface surf;
 394         unsigned pitch, slice, mslice;
 395         unsigned long offset;
 396         int r;
 397
 398         mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
 399         pitch = track->cb_color_pitch[id];
 400         slice = track->cb_color_slice[id];
 401         surf.nbx = (pitch + 1) * 8;
 402         surf.nby = ((slice + 1) * 64) / surf.nbx;
 403         surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
 404         surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
 405         surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
 406         surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
 407         surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
 408         surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
 409         surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
 410         surf.nsamples = 1;
 411
 412         if (!r600_fmt_is_valid_color(surf.format)) {
 413                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
 414                          __func__, __LINE__, surf.format,
 415                         id, track->cb_color_info[id]);
 416                 return -EINVAL;
 417         }
 418
 419         r = evergreen_surface_value_conv_check(p, &surf, "cb");
 420         if (r) {
 421                 return r;
 422         }
 423
 424         r = evergreen_surface_check(p, &surf, "cb");
 425         if (r) {
 426                 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 427                          __func__, __LINE__, id, track->cb_color_pitch[id],
 428                          track->cb_color_slice[id], track->cb_color_attrib[id],
 429                          track->cb_color_info[id]);
 430                 return r;
 431         }
 432
 433         offset = track->cb_color_bo_offset[id] << 8;
 434         if (offset & (surf.base_align - 1)) {
 435                 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
 436                          __func__, __LINE__, id, offset, surf.base_align);
 437                 return -EINVAL;
 438         }
 439
 440         offset += surf.layer_size * mslice;
 441         if (offset > radeon_bo_size(track->cb_color_bo[id])) {
 442                 /* old ddx are broken they allocate bo with w*h*bpp but
 443                  * program slice with ALIGN(h, 8), catch this and patch
 444                  * command stream.
 445                  */
 446                 if (!surf.mode) {
 447                         volatile u32 *ib = p->ib.ptr;
 448                         unsigned long tmp, nby, bsize, size, min = 0;
 449
 450                         /* find the height the ddx wants */
 451                         if (surf.nby > 8) {
 452                                 min = surf.nby - 8;
 453                         }
 454                         bsize = radeon_bo_size(track->cb_color_bo[id]);
 455                         tmp = track->cb_color_bo_offset[id] << 8;
 456                         for (nby = surf.nby; nby > min; nby--) {
 457                                 size = nby * surf.nbx * surf.bpe * surf.nsamples;
 458                                 if ((tmp + size * mslice) <= bsize) {
 459                                         break;
 460                                 }
 461                         }
 462                         if (nby > min) {
 463                                 surf.nby = nby;
 464                                 slice = ((nby * surf.nbx) / 64) - 1;
 465                                 if (!evergreen_surface_check(p, &surf, "cb")) {
 466                                         /* check if this one works */
 467                                         tmp += surf.layer_size * mslice;
 468                                         if (tmp <= bsize) {
 469                                                 ib[track->cb_color_slice_idx[id]] = slice;
 470                                                 goto old_ddx_ok;
 471                                         }
 472                                 }
 473                         }
 474                 }
 475                 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
 476                          "offset %d, max layer %d, bo size %ld, slice %d)\n",
 477                          __func__, __LINE__, id, surf.layer_size,
 478                         track->cb_color_bo_offset[id] << 8, mslice,
 479                         radeon_bo_size(track->cb_color_bo[id]), slice);
 480                 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
 481                          __func__, __LINE__, surf.nbx, surf.nby,
 482                         surf.mode, surf.bpe, surf.nsamples,
 483                         surf.bankw, surf.bankh,
 484                         surf.tsplit, surf.mtilea);
 485                 return -EINVAL;
 486         }
 487 old_ddx_ok:
 488
 489         return 0;
 490 }
 491
 492 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
 493                                                 unsigned nbx, unsigned nby)
 494 {
 495         struct evergreen_cs_track *track = p->track;
 496         unsigned long size;
 497
 498         if (track->htile_bo == NULL) {
 499                 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
 500                                 __func__, __LINE__, track->db_z_info);
 501                 return -EINVAL;
 502         }
 503
 504         if (G_028ABC_LINEAR(track->htile_surface)) {
 505                 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
 506                 nbx = round_up(nbx, 16 * 8);
 507                 /* height is npipes htiles aligned == npipes * 8 pixel aligned */
 508                 nby = round_up(nby, track->npipes * 8);
 509         } else {
 510                 /* always assume 8x8 htile */
 511                 /* align is htile align * 8, htile align vary according to
 512                  * number of pipe and tile width and nby
 513                  */
 514                 switch (track->npipes) {
 515                 case 8:
 516                         /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 517                         nbx = round_up(nbx, 64 * 8);
 518                         nby = round_up(nby, 64 * 8);
 519                         break;
 520                 case 4:
 521                         /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 522                         nbx = round_up(nbx, 64 * 8);
 523                         nby = round_up(nby, 32 * 8);
 524                         break;
 525                 case 2:
 526                         /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 527                         nbx = round_up(nbx, 32 * 8);
 528                         nby = round_up(nby, 32 * 8);
 529                         break;
 530                 case 1:
 531                         /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
 532                         nbx = round_up(nbx, 32 * 8);
 533                         nby = round_up(nby, 16 * 8);
 534                         break;
 535                 default:
 536                         dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
 537                                         __func__, __LINE__, track->npipes);
 538                         return -EINVAL;
 539                 }
 540         }
 541         /* compute number of htile */
 542         nbx = nbx >> 3;
 543         nby = nby >> 3;
 544         /* size must be aligned on npipes * 2K boundary */
 545         size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
 546         size += track->htile_offset;
 547
 548         if (size > radeon_bo_size(track->htile_bo)) {
 549                 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
 550                                 __func__, __LINE__, radeon_bo_size(track->htile_bo),
 551                                 size, nbx, nby);
 552                 return -EINVAL;
 553         }
 554         return 0;
 555 }
 556
 557 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
 558 {
 559         struct evergreen_cs_track *track = p->track;
 560         struct eg_surface surf;
 561         unsigned pitch, slice, mslice;
 562         unsigned long offset;
 563         int r;
 564
 565         mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
 566         pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
 567         slice = track->db_depth_slice;
 568         surf.nbx = (pitch + 1) * 8;
 569         surf.nby = ((slice + 1) * 64) / surf.nbx;
 570         surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
 571         surf.format = G_028044_FORMAT(track->db_s_info);
 572         surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
 573         surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
 574         surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
 575         surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
 576         surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
 577         surf.nsamples = 1;
 578
 579         if (surf.format != 1) {
 580                 dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
 581                          __func__, __LINE__, surf.format);
 582                 return -EINVAL;
 583         }
 584         /* replace by color format so we can use same code */
 585         surf.format = V_028C70_COLOR_8;
 586
 587         r = evergreen_surface_value_conv_check(p, &surf, "stencil");
 588         if (r) {
 589                 return r;
 590         }
 591
 592         r = evergreen_surface_check(p, &surf, NULL);
 593         if (r) {
 594                 /* old userspace doesn't compute proper depth/stencil alignment
 595                  * check that alignment against a bigger byte per elements and
 596                  * only report if that alignment is wrong too.
 597                  */
 598                 surf.format = V_028C70_COLOR_8_8_8_8;
 599                 r = evergreen_surface_check(p, &surf, "stencil");
 600                 if (r) {
 601                         dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 602                                  __func__, __LINE__, track->db_depth_size,
 603                                  track->db_depth_slice, track->db_s_info, track->db_z_info);
 604                 }
 605                 return r;
 606         }
 607
 608         offset = track->db_s_read_offset << 8;
 609         if (offset & (surf.base_align - 1)) {
 610                 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
 611                          __func__, __LINE__, offset, surf.base_align);
 612                 return -EINVAL;
 613         }
 614         offset += surf.layer_size * mslice;
 615         if (offset > radeon_bo_size(track->db_s_read_bo)) {
 616                 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
 617                          "offset %ld, max layer %d, bo size %ld)\n",
 618                          __func__, __LINE__, surf.layer_size,
 619                         (unsigned long)track->db_s_read_offset << 8, mslice,
 620                         radeon_bo_size(track->db_s_read_bo));
 621                 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 622                          __func__, __LINE__, track->db_depth_size,
 623                          track->db_depth_slice, track->db_s_info, track->db_z_info);
 624                 return -EINVAL;
 625         }
 626
 627         offset = track->db_s_write_offset << 8;
 628         if (offset & (surf.base_align - 1)) {
 629                 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
 630                          __func__, __LINE__, offset, surf.base_align);
 631                 return -EINVAL;
 632         }
 633         offset += surf.layer_size * mslice;
 634         if (offset > radeon_bo_size(track->db_s_write_bo)) {
 635                 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
 636                          "offset %ld, max layer %d, bo size %ld)\n",
 637                          __func__, __LINE__, surf.layer_size,
 638                         (unsigned long)track->db_s_write_offset << 8, mslice,
 639                         radeon_bo_size(track->db_s_write_bo));
 640                 return -EINVAL;
 641         }
 642
 643         /* hyperz */
 644         if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
 645                 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
 646                 if (r) {
 647                         return r;
 648                 }
 649         }
 650
 651         return 0;
 652 }
 653
 654 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
 655 {
 656         struct evergreen_cs_track *track = p->track;
 657         struct eg_surface surf;
 658         unsigned pitch, slice, mslice;
 659         unsigned long offset;
 660         int r;
 661
 662         mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
 663         pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
 664         slice = track->db_depth_slice;
 665         surf.nbx = (pitch + 1) * 8;
 666         surf.nby = ((slice + 1) * 64) / surf.nbx;
 667         surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
 668         surf.format = G_028040_FORMAT(track->db_z_info);
 669         surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
 670         surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
 671         surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
 672         surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
 673         surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
 674         surf.nsamples = 1;
 675
 676         switch (surf.format) {
 677         case V_028040_Z_16:
 678                 surf.format = V_028C70_COLOR_16;
 679                 break;
 680         case V_028040_Z_24:
 681         case V_028040_Z_32_FLOAT:
 682                 surf.format = V_028C70_COLOR_8_8_8_8;
 683                 break;
 684         default:
 685                 dev_warn(p->dev, "%s:%d depth invalid format %d\n",
 686                          __func__, __LINE__, surf.format);
 687                 return -EINVAL;
 688         }
 689
 690         r = evergreen_surface_value_conv_check(p, &surf, "depth");
 691         if (r) {
 692                 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
 693                          __func__, __LINE__, track->db_depth_size,
 694                          track->db_depth_slice, track->db_z_info);
 695                 return r;
 696         }
 697
 698         r = evergreen_surface_check(p, &surf, "depth");
 699         if (r) {
 700                 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
 701                          __func__, __LINE__, track->db_depth_size,
 702                          track->db_depth_slice, track->db_z_info);
 703                 return r;
 704         }
 705
 706         offset = track->db_z_read_offset << 8;
 707         if (offset & (surf.base_align - 1)) {
 708                 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
 709                          __func__, __LINE__, offset, surf.base_align);
 710                 return -EINVAL;
 711         }
 712         offset += surf.layer_size * mslice;
 713         if (offset > radeon_bo_size(track->db_z_read_bo)) {
 714                 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
 715                          "offset %ld, max layer %d, bo size %ld)\n",
 716                          __func__, __LINE__, surf.layer_size,
 717                         (unsigned long)track->db_z_read_offset << 8, mslice,
 718                         radeon_bo_size(track->db_z_read_bo));
 719                 return -EINVAL;
 720         }
 721
 722         offset = track->db_z_write_offset << 8;
 723         if (offset & (surf.base_align - 1)) {
 724                 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
 725                          __func__, __LINE__, offset, surf.base_align);
 726                 return -EINVAL;
 727         }
 728         offset += surf.layer_size * mslice;
 729         if (offset > radeon_bo_size(track->db_z_write_bo)) {
 730                 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
 731                          "offset %ld, max layer %d, bo size %ld)\n",
 732                          __func__, __LINE__, surf.layer_size,
 733                         (unsigned long)track->db_z_write_offset << 8, mslice,
 734                         radeon_bo_size(track->db_z_write_bo));
 735                 return -EINVAL;
 736         }
 737
 738         /* hyperz */
 739         if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) {
 740                 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby);
 741                 if (r) {
 742                         return r;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
 750                                                struct radeon_bo *texture,
 751                                                struct radeon_bo *mipmap,
 752                                                unsigned idx)
 753 {
 754         struct eg_surface surf;
 755         unsigned long toffset, moffset;
 756         unsigned dim, llevel, mslice, width, height, depth, i;
 757         u32 texdw[8];
 758         int r;
 759
 760         texdw[0] = radeon_get_ib_value(p, idx + 0);
 761         texdw[1] = radeon_get_ib_value(p, idx + 1);
 762         texdw[2] = radeon_get_ib_value(p, idx + 2);
 763         texdw[3] = radeon_get_ib_value(p, idx + 3);
 764         texdw[4] = radeon_get_ib_value(p, idx + 4);
 765         texdw[5] = radeon_get_ib_value(p, idx + 5);
 766         texdw[6] = radeon_get_ib_value(p, idx + 6);
 767         texdw[7] = radeon_get_ib_value(p, idx + 7);
 768         dim = G_030000_DIM(texdw[0]);
 769         llevel = G_030014_LAST_LEVEL(texdw[5]);
 770         mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
 771         width = G_030000_TEX_WIDTH(texdw[0]) + 1;
 772         height =  G_030004_TEX_HEIGHT(texdw[1]) + 1;
 773         depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
 774         surf.format = G_03001C_DATA_FORMAT(texdw[7]);
 775         surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
 776         surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
 777         surf.nby = r600_fmt_get_nblocksy(surf.format, height);
 778         surf.mode = G_030004_ARRAY_MODE(texdw[1]);
 779         surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
 780         surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
 781         surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
 782         surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
 783         surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
 784         surf.nsamples = 1;
 785         toffset = texdw[2] << 8;
 786         moffset = texdw[3] << 8;
 787
 788         if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
 789                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
 790                          __func__, __LINE__, surf.format);
 791                 return -EINVAL;
 792         }
 793         switch (dim) {
 794         case V_030000_SQ_TEX_DIM_1D:
 795         case V_030000_SQ_TEX_DIM_2D:
 796         case V_030000_SQ_TEX_DIM_CUBEMAP:
 797         case V_030000_SQ_TEX_DIM_1D_ARRAY:
 798         case V_030000_SQ_TEX_DIM_2D_ARRAY:
 799                 depth = 1;
 800                 break;
 801         case V_030000_SQ_TEX_DIM_2D_MSAA:
 802         case V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA:
 803                 surf.nsamples = 1 << llevel;
 804                 llevel = 0;
 805                 depth = 1;
 806                 break;
 807         case V_030000_SQ_TEX_DIM_3D:
 808                 break;
 809         default:
 810                 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
 811                          __func__, __LINE__, dim);
 812                 return -EINVAL;
 813         }
 814
 815         r = evergreen_surface_value_conv_check(p, &surf, "texture");
 816         if (r) {
 817                 return r;
 818         }
 819
 820         /* align height */
 821         evergreen_surface_check(p, &surf, NULL);
 822         surf.nby = ALIGN(surf.nby, surf.halign);
 823
 824         r = evergreen_surface_check(p, &surf, "texture");
 825         if (r) {
 826                 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 827                          __func__, __LINE__, texdw[0], texdw[1], texdw[4],
 828                          texdw[5], texdw[6], texdw[7]);
 829                 return r;
 830         }
 831
 832         /* check texture size */
 833         if (toffset & (surf.base_align - 1)) {
 834                 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
 835                          __func__, __LINE__, toffset, surf.base_align);
 836                 return -EINVAL;
 837         }
 838         if (moffset & (surf.base_align - 1)) {
 839                 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
 840                          __func__, __LINE__, moffset, surf.base_align);
 841                 return -EINVAL;
 842         }
 843         if (dim == SQ_TEX_DIM_3D) {
 844                 toffset += surf.layer_size * depth;
 845         } else {
 846                 toffset += surf.layer_size * mslice;
 847         }
 848         if (toffset > radeon_bo_size(texture)) {
 849                 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
 850                          "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
 851                          __func__, __LINE__, surf.layer_size,
 852                         (unsigned long)texdw[2] << 8, mslice,
 853                         depth, radeon_bo_size(texture),
 854                         surf.nbx, surf.nby);
 855                 return -EINVAL;
 856         }
 857
 858         if (!mipmap) {
 859                 if (llevel) {
 860                         dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n",
 861                                  __func__, __LINE__);
 862                         return -EINVAL;
 863                 } else {
 864                         return 0; /* everything's ok */
 865                 }
 866         }
 867
 868         /* check mipmap size */
 869         for (i = 1; i <= llevel; i++) {
 870                 unsigned w, h, d;
 871
 872                 w = r600_mip_minify(width, i);
 873                 h = r600_mip_minify(height, i);
 874                 d = r600_mip_minify(depth, i);
 875                 surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
 876                 surf.nby = r600_fmt_get_nblocksy(surf.format, h);
 877
 878                 switch (surf.mode) {
 879                 case ARRAY_2D_TILED_THIN1:
 880                         if (surf.nbx < surf.palign || surf.nby < surf.halign) {
 881                                 surf.mode = ARRAY_1D_TILED_THIN1;
 882                         }
 883                         /* recompute alignment */
 884                         evergreen_surface_check(p, &surf, NULL);
 885                         break;
 886                 case ARRAY_LINEAR_GENERAL:
 887                 case ARRAY_LINEAR_ALIGNED:
 888                 case ARRAY_1D_TILED_THIN1:
 889                         break;
 890                 default:
 891                         dev_warn(p->dev, "%s:%d invalid array mode %d\n",
 892                                  __func__, __LINE__, surf.mode);
 893                         return -EINVAL;
 894                 }
 895                 surf.nbx = ALIGN(surf.nbx, surf.palign);
 896                 surf.nby = ALIGN(surf.nby, surf.halign);
 897
 898                 r = evergreen_surface_check(p, &surf, "mipmap");
 899                 if (r) {
 900                         return r;
 901                 }
 902
 903                 if (dim == SQ_TEX_DIM_3D) {
 904                         moffset += surf.layer_size * d;
 905                 } else {
 906                         moffset += surf.layer_size * mslice;
 907                 }
 908                 if (moffset > radeon_bo_size(mipmap)) {
 909                         dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
 910                                         "offset %ld, coffset %ld, max layer %d, depth %d, "
 911                                         "bo size %ld) level0 (%d %d %d)\n",
 912                                         __func__, __LINE__, i, surf.layer_size,
 913                                         (unsigned long)texdw[3] << 8, moffset, mslice,
 914                                         d, radeon_bo_size(mipmap),
 915                                         width, height, depth);
 916                         dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
 917                                  __func__, __LINE__, surf.nbx, surf.nby,
 918                                 surf.mode, surf.bpe, surf.nsamples,
 919                                 surf.bankw, surf.bankh,
 920                                 surf.tsplit, surf.mtilea);
 921                         return -EINVAL;
 922                 }
 923         }
 924
 925         return 0;
 926 }
 927
 928 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
 929 {
 930         struct evergreen_cs_track *track = p->track;
 931         unsigned tmp, i;
 932         int r;
 933         unsigned buffer_mask = 0;
 934
 935         /* check streamout */
 936         if (track->streamout_dirty && track->vgt_strmout_config) {
 937                 for (i = 0; i < 4; i++) {
 938                         if (track->vgt_strmout_config & (1 << i)) {
 939                                 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
 940                         }
 941                 }
 942
 943                 for (i = 0; i < 4; i++) {
 944                         if (buffer_mask & (1 << i)) {
 945                                 if (track->vgt_strmout_bo[i]) {
 946                                         u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
 947                                                         (u64)track->vgt_strmout_size[i];
 948                                         if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
 949                                                 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
 950                                                           i, offset,
 951                                                           radeon_bo_size(track->vgt_strmout_bo[i]));
 952                                                 return -EINVAL;
 953                                         }
 954                                 } else {
 955                                         dev_warn(p->dev, "No buffer for streamout %d\n", i);
 956                                         return -EINVAL;
 957                                 }
 958                         }
 959                 }
 960                 track->streamout_dirty = false;
 961         }
 962
 963         if (track->sx_misc_kill_all_prims)
 964                 return 0;
 965
 966         /* check that we have a cb for each enabled target
 967          */
 968         if (track->cb_dirty) {
 969                 tmp = track->cb_target_mask;
 970                 for (i = 0; i < 8; i++) {
 971                         if ((tmp >> (i * 4)) & 0xF) {
 972                                 /* at least one component is enabled */
 973                                 if (track->cb_color_bo[i] == NULL) {
 974                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 975                                                 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 976                                         return -EINVAL;
 977                                 }
 978                                 /* check cb */
 979                                 r = evergreen_cs_track_validate_cb(p, i);
 980                                 if (r) {
 981                                         return r;
 982                                 }
 983                         }
 984                 }
 985                 track->cb_dirty = false;
 986         }
 987
 988         if (track->db_dirty) {
 989                 /* Check stencil buffer */
 990                 if (G_028044_FORMAT(track->db_s_info) != V_028044_STENCIL_INVALID &&
 991                     G_028800_STENCIL_ENABLE(track->db_depth_control)) {
 992                         r = evergreen_cs_track_validate_stencil(p);
 993                         if (r)
 994                                 return r;
 995                 }
 996                 /* Check depth buffer */
 997                 if (G_028040_FORMAT(track->db_z_info) != V_028040_Z_INVALID &&
 998                     G_028800_Z_ENABLE(track->db_depth_control)) {
 999                         r = evergreen_cs_track_validate_depth(p);
1000                         if (r)
1001                                 return r;
1002                 }
1003                 track->db_dirty = false;
1004         }
1005
1006         return 0;
1007 }
1008
1009 /**
1010  * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
1011  * @parser:     parser structure holding parsing context.
1012  * @pkt:        where to store packet informations
1013  *
1014  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1015  * if packet is bigger than remaining ib size. or if packets is unknown.
1016  **/
1017 static int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
1018                               struct radeon_cs_packet *pkt,
1019                               unsigned idx)
1020 {
1021         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1022         uint32_t header;
1023
1024         if (idx >= ib_chunk->length_dw) {
1025                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1026                           idx, ib_chunk->length_dw);
1027                 return -EINVAL;
1028         }
1029         header = radeon_get_ib_value(p, idx);
1030         pkt->idx = idx;
1031         pkt->type = CP_PACKET_GET_TYPE(header);
1032         pkt->count = CP_PACKET_GET_COUNT(header);
1033         pkt->one_reg_wr = 0;
1034         switch (pkt->type) {
1035         case PACKET_TYPE0:
1036                 pkt->reg = CP_PACKET0_GET_REG(header);
1037                 break;
1038         case PACKET_TYPE3:
1039                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1040                 break;
1041         case PACKET_TYPE2:
1042                 pkt->count = -1;
1043                 break;
1044         default:
1045                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1046                 return -EINVAL;
1047         }
1048         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1049                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1050                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1051                 return -EINVAL;
1052         }
1053         return 0;
1054 }
1055
1056 /**
1057  * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1058  * @parser:             parser structure holding parsing context.
1059  * @data:               pointer to relocation data
1060  * @offset_start:       starting offset
1061  * @offset_mask:        offset mask (to align start offset on)
1062  * @reloc:              reloc informations
1063  *
1064  * Check next packet is relocation packet3, do bo validation and compute
1065  * GPU offset using the provided start.
1066  **/
1067 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
1068                                           struct radeon_cs_reloc **cs_reloc)
1069 {
1070         struct radeon_cs_chunk *relocs_chunk;
1071         struct radeon_cs_packet p3reloc;
1072         unsigned idx;
1073         int r;
1074
1075         if (p->chunk_relocs_idx == -1) {
1076                 DRM_ERROR("No relocation chunk !\n");
1077                 return -EINVAL;
1078         }
1079         *cs_reloc = NULL;
1080         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1081         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1082         if (r) {
1083                 return r;
1084         }
1085         p->idx += p3reloc.count + 2;
1086         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1087                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1088                           p3reloc.idx);
1089                 return -EINVAL;
1090         }
1091         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1092         if (idx >= relocs_chunk->length_dw) {
1093                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1094                           idx, relocs_chunk->length_dw);
1095                 return -EINVAL;
1096         }
1097         /* FIXME: we assume reloc size is 4 dwords */
1098         *cs_reloc = p->relocs_ptr[(idx / 4)];
1099         return 0;
1100 }
1101
1102 /**
1103  * evergreen_cs_packet_next_is_pkt3_nop() - test if the next packet is NOP
1104  * @p:          structure holding the parser context.
1105  *
1106  * Check if the next packet is a relocation packet3.
1107  **/
1108 static bool evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
1109 {
1110         struct radeon_cs_packet p3reloc;
1111         int r;
1112
1113         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1114         if (r) {
1115                 return false;
1116         }
1117         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1118                 return false;
1119         }
1120         return true;
1121 }
1122
1123 /**
1124  * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
1125  * @parser:             parser structure holding parsing context.
1126  *
1127  * Userspace sends a special sequence for VLINE waits.
1128  * PACKET0 - VLINE_START_END + value
1129  * PACKET3 - WAIT_REG_MEM poll vline status reg
1130  * RELOC (P3) - crtc_id in reloc.
1131  *
1132  * This function parses this and relocates the VLINE START END
1133  * and WAIT_REG_MEM packets to the correct crtc.
1134  * It also detects a switched off crtc and nulls out the
1135  * wait in that case.
1136  */
1137 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1138 {
1139         struct drm_mode_object *obj;
1140         struct drm_crtc *crtc;
1141         struct radeon_crtc *radeon_crtc;
1142         struct radeon_cs_packet p3reloc, wait_reg_mem;
1143         int crtc_id;
1144         int r;
1145         uint32_t header, h_idx, reg, wait_reg_mem_info;
1146         volatile uint32_t *ib;
1147
1148         ib = p->ib.ptr;
1149
1150         /* parse the WAIT_REG_MEM */
1151         r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
1152         if (r)
1153                 return r;
1154
1155         /* check its a WAIT_REG_MEM */
1156         if (wait_reg_mem.type != PACKET_TYPE3 ||
1157             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1158                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1159                 return -EINVAL;
1160         }
1161
1162         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1163         /* bit 4 is reg (0) or mem (1) */
1164         if (wait_reg_mem_info & 0x10) {
1165                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1166                 return -EINVAL;
1167         }
1168         /* waiting for value to be equal */
1169         if ((wait_reg_mem_info & 0x7) != 0x3) {
1170                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1171                 return -EINVAL;
1172         }
1173         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
1174                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1175                 return -EINVAL;
1176         }
1177
1178         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
1179                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1180                 return -EINVAL;
1181         }
1182
1183         /* jump over the NOP */
1184         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1185         if (r)
1186                 return r;
1187
1188         h_idx = p->idx - 2;
1189         p->idx += wait_reg_mem.count + 2;
1190         p->idx += p3reloc.count + 2;
1191
1192         header = radeon_get_ib_value(p, h_idx);
1193         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1194         reg = CP_PACKET0_GET_REG(header);
1195         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1196         if (!obj) {
1197                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1198                 return -EINVAL;
1199         }
1200         crtc = obj_to_crtc(obj);
1201         radeon_crtc = to_radeon_crtc(crtc);
1202         crtc_id = radeon_crtc->crtc_id;
1203
1204         if (!crtc->enabled) {
1205                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1206                 ib[h_idx + 2] = PACKET2(0);
1207                 ib[h_idx + 3] = PACKET2(0);
1208                 ib[h_idx + 4] = PACKET2(0);
1209                 ib[h_idx + 5] = PACKET2(0);
1210                 ib[h_idx + 6] = PACKET2(0);
1211                 ib[h_idx + 7] = PACKET2(0);
1212                 ib[h_idx + 8] = PACKET2(0);
1213         } else {
1214                 switch (reg) {
1215                 case EVERGREEN_VLINE_START_END:
1216                         header &= ~R600_CP_PACKET0_REG_MASK;
1217                         header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1218                         ib[h_idx] = header;
1219                         ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1220                         break;
1221                 default:
1222                         DRM_ERROR("unknown crtc reloc\n");
1223                         return -EINVAL;
1224                 }
1225         }
1226         return 0;
1227 }
1228
1229 static int evergreen_packet0_check(struct radeon_cs_parser *p,
1230                                    struct radeon_cs_packet *pkt,
1231                                    unsigned idx, unsigned reg)
1232 {
1233         int r;
1234
1235         switch (reg) {
1236         case EVERGREEN_VLINE_START_END:
1237                 r = evergreen_cs_packet_parse_vline(p);
1238                 if (r) {
1239                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1240                                         idx, reg);
1241                         return r;
1242                 }
1243                 break;
1244         default:
1245                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1246                        reg, idx);
1247                 return -EINVAL;
1248         }
1249         return 0;
1250 }
1251
1252 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1253                                       struct radeon_cs_packet *pkt)
1254 {
1255         unsigned reg, i;
1256         unsigned idx;
1257         int r;
1258
1259         idx = pkt->idx + 1;
1260         reg = pkt->reg;
1261         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1262                 r = evergreen_packet0_check(p, pkt, idx, reg);
1263                 if (r) {
1264                         return r;
1265                 }
1266         }
1267         return 0;
1268 }
1269
1270 /**
1271  * evergreen_cs_check_reg() - check if register is authorized or not
1272  * @parser: parser structure holding parsing context
1273  * @reg: register we are testing
1274  * @idx: index into the cs buffer
1275  *
1276  * This function will test against evergreen_reg_safe_bm and return 0
1277  * if register is safe. If register is not flag as safe this function
1278  * will test it against a list of register needind special handling.
1279  */
1280 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1281 {
1282         struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1283         struct radeon_cs_reloc *reloc;
1284         u32 last_reg;
1285         u32 m, i, tmp, *ib;
1286         int r;
1287
1288         if (p->rdev->family >= CHIP_CAYMAN)
1289                 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1290         else
1291                 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1292
1293         i = (reg >> 7);
1294         if (i >= last_reg) {
1295                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1296                 return -EINVAL;
1297         }
1298         m = 1 << ((reg >> 2) & 31);
1299         if (p->rdev->family >= CHIP_CAYMAN) {
1300                 if (!(cayman_reg_safe_bm[i] & m))
1301                         return 0;
1302         } else {
1303                 if (!(evergreen_reg_safe_bm[i] & m))
1304                         return 0;
1305         }
1306         ib = p->ib.ptr;
1307         switch (reg) {
1308         /* force following reg to 0 in an attempt to disable out buffer
1309          * which will need us to better understand how it works to perform
1310          * security check on it (Jerome)
1311          */
1312         case SQ_ESGS_RING_SIZE:
1313         case SQ_GSVS_RING_SIZE:
1314         case SQ_ESTMP_RING_SIZE:
1315         case SQ_GSTMP_RING_SIZE:
1316         case SQ_HSTMP_RING_SIZE:
1317         case SQ_LSTMP_RING_SIZE:
1318         case SQ_PSTMP_RING_SIZE:
1319         case SQ_VSTMP_RING_SIZE:
1320         case SQ_ESGS_RING_ITEMSIZE:
1321         case SQ_ESTMP_RING_ITEMSIZE:
1322         case SQ_GSTMP_RING_ITEMSIZE:
1323         case SQ_GSVS_RING_ITEMSIZE:
1324         case SQ_GS_VERT_ITEMSIZE:
1325         case SQ_GS_VERT_ITEMSIZE_1:
1326         case SQ_GS_VERT_ITEMSIZE_2:
1327         case SQ_GS_VERT_ITEMSIZE_3:
1328         case SQ_GSVS_RING_OFFSET_1:
1329         case SQ_GSVS_RING_OFFSET_2:
1330         case SQ_GSVS_RING_OFFSET_3:
1331         case SQ_HSTMP_RING_ITEMSIZE:
1332         case SQ_LSTMP_RING_ITEMSIZE:
1333         case SQ_PSTMP_RING_ITEMSIZE:
1334         case SQ_VSTMP_RING_ITEMSIZE:
1335         case VGT_TF_RING_SIZE:
1336                 /* get value to populate the IB don't remove */
1337                 /*tmp =radeon_get_ib_value(p, idx);
1338                   ib[idx] = 0;*/
1339                 break;
1340         case SQ_ESGS_RING_BASE:
1341         case SQ_GSVS_RING_BASE:
1342         case SQ_ESTMP_RING_BASE:
1343         case SQ_GSTMP_RING_BASE:
1344         case SQ_HSTMP_RING_BASE:
1345         case SQ_LSTMP_RING_BASE:
1346         case SQ_PSTMP_RING_BASE:
1347         case SQ_VSTMP_RING_BASE:
1348                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1349                 if (r) {
1350                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1351                                         "0x%04X\n", reg);
1352                         return -EINVAL;
1353                 }
1354                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1355                 break;
1356         case DB_DEPTH_CONTROL:
1357                 track->db_depth_control = radeon_get_ib_value(p, idx);
1358                 track->db_dirty = true;
1359                 break;
1360         case CAYMAN_DB_EQAA:
1361                 if (p->rdev->family < CHIP_CAYMAN) {
1362                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1363                                  "0x%04X\n", reg);
1364                         return -EINVAL;
1365                 }
1366                 break;
1367         case CAYMAN_DB_DEPTH_INFO:
1368                 if (p->rdev->family < CHIP_CAYMAN) {
1369                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1370                                  "0x%04X\n", reg);
1371                         return -EINVAL;
1372                 }
1373                 break;
1374         case DB_Z_INFO:
1375                 track->db_z_info = radeon_get_ib_value(p, idx);
1376                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1377                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1378                         if (r) {
1379                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1380                                                 "0x%04X\n", reg);
1381                                 return -EINVAL;
1382                         }
1383                         ib[idx] &= ~Z_ARRAY_MODE(0xf);
1384                         track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1385                         ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1386                         track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1387                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1388                                 unsigned bankw, bankh, mtaspect, tile_split;
1389
1390                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1391                                                         &bankw, &bankh, &mtaspect,
1392                                                         &tile_split);
1393                                 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1394                                 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1395                                                 DB_BANK_WIDTH(bankw) |
1396                                                 DB_BANK_HEIGHT(bankh) |
1397                                                 DB_MACRO_TILE_ASPECT(mtaspect);
1398                         }
1399                 }
1400                 track->db_dirty = true;
1401                 break;
1402         case DB_STENCIL_INFO:
1403                 track->db_s_info = radeon_get_ib_value(p, idx);
1404                 track->db_dirty = true;
1405                 break;
1406         case DB_DEPTH_VIEW:
1407                 track->db_depth_view = radeon_get_ib_value(p, idx);
1408                 track->db_dirty = true;
1409                 break;
1410         case DB_DEPTH_SIZE:
1411                 track->db_depth_size = radeon_get_ib_value(p, idx);
1412                 track->db_dirty = true;
1413                 break;
1414         case R_02805C_DB_DEPTH_SLICE:
1415                 track->db_depth_slice = radeon_get_ib_value(p, idx);
1416                 track->db_dirty = true;
1417                 break;
1418         case DB_Z_READ_BASE:
1419                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1420                 if (r) {
1421                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1422                                         "0x%04X\n", reg);
1423                         return -EINVAL;
1424                 }
1425                 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1426                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1427                 track->db_z_read_bo = reloc->robj;
1428                 track->db_dirty = true;
1429                 break;
1430         case DB_Z_WRITE_BASE:
1431                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1432                 if (r) {
1433                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1434                                         "0x%04X\n", reg);
1435                         return -EINVAL;
1436                 }
1437                 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1438                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1439                 track->db_z_write_bo = reloc->robj;
1440                 track->db_dirty = true;
1441                 break;
1442         case DB_STENCIL_READ_BASE:
1443                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1444                 if (r) {
1445                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1446                                         "0x%04X\n", reg);
1447                         return -EINVAL;
1448                 }
1449                 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1450                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1451                 track->db_s_read_bo = reloc->robj;
1452                 track->db_dirty = true;
1453                 break;
1454         case DB_STENCIL_WRITE_BASE:
1455                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1456                 if (r) {
1457                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1458                                         "0x%04X\n", reg);
1459                         return -EINVAL;
1460                 }
1461                 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1462                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1463                 track->db_s_write_bo = reloc->robj;
1464                 track->db_dirty = true;
1465                 break;
1466         case VGT_STRMOUT_CONFIG:
1467                 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1468                 track->streamout_dirty = true;
1469                 break;
1470         case VGT_STRMOUT_BUFFER_CONFIG:
1471                 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1472                 track->streamout_dirty = true;
1473                 break;
1474         case VGT_STRMOUT_BUFFER_BASE_0:
1475         case VGT_STRMOUT_BUFFER_BASE_1:
1476         case VGT_STRMOUT_BUFFER_BASE_2:
1477         case VGT_STRMOUT_BUFFER_BASE_3:
1478                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1479                 if (r) {
1480                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1481                                         "0x%04X\n", reg);
1482                         return -EINVAL;
1483                 }
1484                 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1485                 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1486                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1487                 track->vgt_strmout_bo[tmp] = reloc->robj;
1488                 track->streamout_dirty = true;
1489                 break;
1490         case VGT_STRMOUT_BUFFER_SIZE_0:
1491         case VGT_STRMOUT_BUFFER_SIZE_1:
1492         case VGT_STRMOUT_BUFFER_SIZE_2:
1493         case VGT_STRMOUT_BUFFER_SIZE_3:
1494                 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1495                 /* size in register is DWs, convert to bytes */
1496                 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1497                 track->streamout_dirty = true;
1498                 break;
1499         case CP_COHER_BASE:
1500                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1501                 if (r) {
1502                         dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1503                                         "0x%04X\n", reg);
1504                         return -EINVAL;
1505                 }
1506                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1507         case CB_TARGET_MASK:
1508                 track->cb_target_mask = radeon_get_ib_value(p, idx);
1509                 track->cb_dirty = true;
1510                 break;
1511         case CB_SHADER_MASK:
1512                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1513                 track->cb_dirty = true;
1514                 break;
1515         case PA_SC_AA_CONFIG:
1516                 if (p->rdev->family >= CHIP_CAYMAN) {
1517                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1518                                  "0x%04X\n", reg);
1519                         return -EINVAL;
1520                 }
1521                 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1522                 track->nsamples = 1 << tmp;
1523                 break;
1524         case CAYMAN_PA_SC_AA_CONFIG:
1525                 if (p->rdev->family < CHIP_CAYMAN) {
1526                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1527                                  "0x%04X\n", reg);
1528                         return -EINVAL;
1529                 }
1530                 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1531                 track->nsamples = 1 << tmp;
1532                 break;
1533         case CB_COLOR0_VIEW:
1534         case CB_COLOR1_VIEW:
1535         case CB_COLOR2_VIEW:
1536         case CB_COLOR3_VIEW:
1537         case CB_COLOR4_VIEW:
1538         case CB_COLOR5_VIEW:
1539         case CB_COLOR6_VIEW:
1540         case CB_COLOR7_VIEW:
1541                 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1542                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1543                 track->cb_dirty = true;
1544                 break;
1545         case CB_COLOR8_VIEW:
1546         case CB_COLOR9_VIEW:
1547         case CB_COLOR10_VIEW:
1548         case CB_COLOR11_VIEW:
1549                 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1550                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1551                 track->cb_dirty = true;
1552                 break;
1553         case CB_COLOR0_INFO:
1554         case CB_COLOR1_INFO:
1555         case CB_COLOR2_INFO:
1556         case CB_COLOR3_INFO:
1557         case CB_COLOR4_INFO:
1558         case CB_COLOR5_INFO:
1559         case CB_COLOR6_INFO:
1560         case CB_COLOR7_INFO:
1561                 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1562                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1563                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1564                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1565                         if (r) {
1566                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1567                                                 "0x%04X\n", reg);
1568                                 return -EINVAL;
1569                         }
1570                         ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1571                         track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1572                 }
1573                 track->cb_dirty = true;
1574                 break;
1575         case CB_COLOR8_INFO:
1576         case CB_COLOR9_INFO:
1577         case CB_COLOR10_INFO:
1578         case CB_COLOR11_INFO:
1579                 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1580                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1581                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1582                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1583                         if (r) {
1584                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1585                                                 "0x%04X\n", reg);
1586                                 return -EINVAL;
1587                         }
1588                         ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1589                         track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1590                 }
1591                 track->cb_dirty = true;
1592                 break;
1593         case CB_COLOR0_PITCH:
1594         case CB_COLOR1_PITCH:
1595         case CB_COLOR2_PITCH:
1596         case CB_COLOR3_PITCH:
1597         case CB_COLOR4_PITCH:
1598         case CB_COLOR5_PITCH:
1599         case CB_COLOR6_PITCH:
1600         case CB_COLOR7_PITCH:
1601                 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1602                 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1603                 track->cb_dirty = true;
1604                 break;
1605         case CB_COLOR8_PITCH:
1606         case CB_COLOR9_PITCH:
1607         case CB_COLOR10_PITCH:
1608         case CB_COLOR11_PITCH:
1609                 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1610                 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1611                 track->cb_dirty = true;
1612                 break;
1613         case CB_COLOR0_SLICE:
1614         case CB_COLOR1_SLICE:
1615         case CB_COLOR2_SLICE:
1616         case CB_COLOR3_SLICE:
1617         case CB_COLOR4_SLICE:
1618         case CB_COLOR5_SLICE:
1619         case CB_COLOR6_SLICE:
1620         case CB_COLOR7_SLICE:
1621                 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1622                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1623                 track->cb_color_slice_idx[tmp] = idx;
1624                 track->cb_dirty = true;
1625                 break;
1626         case CB_COLOR8_SLICE:
1627         case CB_COLOR9_SLICE:
1628         case CB_COLOR10_SLICE:
1629         case CB_COLOR11_SLICE:
1630                 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1631                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1632                 track->cb_color_slice_idx[tmp] = idx;
1633                 track->cb_dirty = true;
1634                 break;
1635         case CB_COLOR0_ATTRIB:
1636         case CB_COLOR1_ATTRIB:
1637         case CB_COLOR2_ATTRIB:
1638         case CB_COLOR3_ATTRIB:
1639         case CB_COLOR4_ATTRIB:
1640         case CB_COLOR5_ATTRIB:
1641         case CB_COLOR6_ATTRIB:
1642         case CB_COLOR7_ATTRIB:
1643                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1644                 if (r) {
1645                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1646                                         "0x%04X\n", reg);
1647                         return -EINVAL;
1648                 }
1649                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1650                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1651                                 unsigned bankw, bankh, mtaspect, tile_split;
1652
1653                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1654                                                         &bankw, &bankh, &mtaspect,
1655                                                         &tile_split);
1656                                 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1657                                 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1658                                            CB_BANK_WIDTH(bankw) |
1659                                            CB_BANK_HEIGHT(bankh) |
1660                                            CB_MACRO_TILE_ASPECT(mtaspect);
1661                         }
1662                 }
1663                 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1664                 track->cb_color_attrib[tmp] = ib[idx];
1665                 track->cb_dirty = true;
1666                 break;
1667         case CB_COLOR8_ATTRIB:
1668         case CB_COLOR9_ATTRIB:
1669         case CB_COLOR10_ATTRIB:
1670         case CB_COLOR11_ATTRIB:
1671                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1672                 if (r) {
1673                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1674                                         "0x%04X\n", reg);
1675                         return -EINVAL;
1676                 }
1677                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1678                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1679                                 unsigned bankw, bankh, mtaspect, tile_split;
1680
1681                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1682                                                         &bankw, &bankh, &mtaspect,
1683                                                         &tile_split);
1684                                 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1685                                 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1686                                            CB_BANK_WIDTH(bankw) |
1687                                            CB_BANK_HEIGHT(bankh) |
1688                                            CB_MACRO_TILE_ASPECT(mtaspect);
1689                         }
1690                 }
1691                 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1692                 track->cb_color_attrib[tmp] = ib[idx];
1693                 track->cb_dirty = true;
1694                 break;
1695         case CB_COLOR0_FMASK:
1696         case CB_COLOR1_FMASK:
1697         case CB_COLOR2_FMASK:
1698         case CB_COLOR3_FMASK:
1699         case CB_COLOR4_FMASK:
1700         case CB_COLOR5_FMASK:
1701         case CB_COLOR6_FMASK:
1702         case CB_COLOR7_FMASK:
1703                 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1704                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1705                 if (r) {
1706                         dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1707                         return -EINVAL;
1708                 }
1709                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1710                 track->cb_color_fmask_bo[tmp] = reloc->robj;
1711                 break;
1712         case CB_COLOR0_CMASK:
1713         case CB_COLOR1_CMASK:
1714         case CB_COLOR2_CMASK:
1715         case CB_COLOR3_CMASK:
1716         case CB_COLOR4_CMASK:
1717         case CB_COLOR5_CMASK:
1718         case CB_COLOR6_CMASK:
1719         case CB_COLOR7_CMASK:
1720                 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1721                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1722                 if (r) {
1723                         dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1724                         return -EINVAL;
1725                 }
1726                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1727                 track->cb_color_cmask_bo[tmp] = reloc->robj;
1728                 break;
1729         case CB_COLOR0_FMASK_SLICE:
1730         case CB_COLOR1_FMASK_SLICE:
1731         case CB_COLOR2_FMASK_SLICE:
1732         case CB_COLOR3_FMASK_SLICE:
1733         case CB_COLOR4_FMASK_SLICE:
1734         case CB_COLOR5_FMASK_SLICE:
1735         case CB_COLOR6_FMASK_SLICE:
1736         case CB_COLOR7_FMASK_SLICE:
1737                 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1738                 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1739                 break;
1740         case CB_COLOR0_CMASK_SLICE:
1741         case CB_COLOR1_CMASK_SLICE:
1742         case CB_COLOR2_CMASK_SLICE:
1743         case CB_COLOR3_CMASK_SLICE:
1744         case CB_COLOR4_CMASK_SLICE:
1745         case CB_COLOR5_CMASK_SLICE:
1746         case CB_COLOR6_CMASK_SLICE:
1747         case CB_COLOR7_CMASK_SLICE:
1748                 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1749                 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1750                 break;
1751         case CB_COLOR0_BASE:
1752         case CB_COLOR1_BASE:
1753         case CB_COLOR2_BASE:
1754         case CB_COLOR3_BASE:
1755         case CB_COLOR4_BASE:
1756         case CB_COLOR5_BASE:
1757         case CB_COLOR6_BASE:
1758         case CB_COLOR7_BASE:
1759                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1760                 if (r) {
1761                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1762                                         "0x%04X\n", reg);
1763                         return -EINVAL;
1764                 }
1765                 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1766                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1767                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1768                 track->cb_color_bo[tmp] = reloc->robj;
1769                 track->cb_dirty = true;
1770                 break;
1771         case CB_COLOR8_BASE:
1772         case CB_COLOR9_BASE:
1773         case CB_COLOR10_BASE:
1774         case CB_COLOR11_BASE:
1775                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1776                 if (r) {
1777                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1778                                         "0x%04X\n", reg);
1779                         return -EINVAL;
1780                 }
1781                 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1782                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1783                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1784                 track->cb_color_bo[tmp] = reloc->robj;
1785                 track->cb_dirty = true;
1786                 break;
1787         case DB_HTILE_DATA_BASE:
1788                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1789                 if (r) {
1790                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1791                                         "0x%04X\n", reg);
1792                         return -EINVAL;
1793                 }
1794                 track->htile_offset = radeon_get_ib_value(p, idx);
1795                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1796                 track->htile_bo = reloc->robj;
1797                 track->db_dirty = true;
1798                 break;
1799         case DB_HTILE_SURFACE:
1800                 /* 8x8 only */
1801                 track->htile_surface = radeon_get_ib_value(p, idx);
1802                 /* force 8x8 htile width and height */
1803                 ib[idx] |= 3;
1804                 track->db_dirty = true;
1805                 break;
1806         case CB_IMMED0_BASE:
1807         case CB_IMMED1_BASE:
1808         case CB_IMMED2_BASE:
1809         case CB_IMMED3_BASE:
1810         case CB_IMMED4_BASE:
1811         case CB_IMMED5_BASE:
1812         case CB_IMMED6_BASE:
1813         case CB_IMMED7_BASE:
1814         case CB_IMMED8_BASE:
1815         case CB_IMMED9_BASE:
1816         case CB_IMMED10_BASE:
1817         case CB_IMMED11_BASE:
1818         case SQ_PGM_START_FS:
1819         case SQ_PGM_START_ES:
1820         case SQ_PGM_START_VS:
1821         case SQ_PGM_START_GS:
1822         case SQ_PGM_START_PS:
1823         case SQ_PGM_START_HS:
1824         case SQ_PGM_START_LS:
1825         case SQ_CONST_MEM_BASE:
1826         case SQ_ALU_CONST_CACHE_GS_0:
1827         case SQ_ALU_CONST_CACHE_GS_1:
1828         case SQ_ALU_CONST_CACHE_GS_2:
1829         case SQ_ALU_CONST_CACHE_GS_3:
1830         case SQ_ALU_CONST_CACHE_GS_4:
1831         case SQ_ALU_CONST_CACHE_GS_5:
1832         case SQ_ALU_CONST_CACHE_GS_6:
1833         case SQ_ALU_CONST_CACHE_GS_7:
1834         case SQ_ALU_CONST_CACHE_GS_8:
1835         case SQ_ALU_CONST_CACHE_GS_9:
1836         case SQ_ALU_CONST_CACHE_GS_10:
1837         case SQ_ALU_CONST_CACHE_GS_11:
1838         case SQ_ALU_CONST_CACHE_GS_12:
1839         case SQ_ALU_CONST_CACHE_GS_13:
1840         case SQ_ALU_CONST_CACHE_GS_14:
1841         case SQ_ALU_CONST_CACHE_GS_15:
1842         case SQ_ALU_CONST_CACHE_PS_0:
1843         case SQ_ALU_CONST_CACHE_PS_1:
1844         case SQ_ALU_CONST_CACHE_PS_2:
1845         case SQ_ALU_CONST_CACHE_PS_3:
1846         case SQ_ALU_CONST_CACHE_PS_4:
1847         case SQ_ALU_CONST_CACHE_PS_5:
1848         case SQ_ALU_CONST_CACHE_PS_6:
1849         case SQ_ALU_CONST_CACHE_PS_7:
1850         case SQ_ALU_CONST_CACHE_PS_8:
1851         case SQ_ALU_CONST_CACHE_PS_9:
1852         case SQ_ALU_CONST_CACHE_PS_10:
1853         case SQ_ALU_CONST_CACHE_PS_11:
1854         case SQ_ALU_CONST_CACHE_PS_12:
1855         case SQ_ALU_CONST_CACHE_PS_13:
1856         case SQ_ALU_CONST_CACHE_PS_14:
1857         case SQ_ALU_CONST_CACHE_PS_15:
1858         case SQ_ALU_CONST_CACHE_VS_0:
1859         case SQ_ALU_CONST_CACHE_VS_1:
1860         case SQ_ALU_CONST_CACHE_VS_2:
1861         case SQ_ALU_CONST_CACHE_VS_3:
1862         case SQ_ALU_CONST_CACHE_VS_4:
1863         case SQ_ALU_CONST_CACHE_VS_5:
1864         case SQ_ALU_CONST_CACHE_VS_6:
1865         case SQ_ALU_CONST_CACHE_VS_7:
1866         case SQ_ALU_CONST_CACHE_VS_8:
1867         case SQ_ALU_CONST_CACHE_VS_9:
1868         case SQ_ALU_CONST_CACHE_VS_10:
1869         case SQ_ALU_CONST_CACHE_VS_11:
1870         case SQ_ALU_CONST_CACHE_VS_12:
1871         case SQ_ALU_CONST_CACHE_VS_13:
1872         case SQ_ALU_CONST_CACHE_VS_14:
1873         case SQ_ALU_CONST_CACHE_VS_15:
1874         case SQ_ALU_CONST_CACHE_HS_0:
1875         case SQ_ALU_CONST_CACHE_HS_1:
1876         case SQ_ALU_CONST_CACHE_HS_2:
1877         case SQ_ALU_CONST_CACHE_HS_3:
1878         case SQ_ALU_CONST_CACHE_HS_4:
1879         case SQ_ALU_CONST_CACHE_HS_5:
1880         case SQ_ALU_CONST_CACHE_HS_6:
1881         case SQ_ALU_CONST_CACHE_HS_7:
1882         case SQ_ALU_CONST_CACHE_HS_8:
1883         case SQ_ALU_CONST_CACHE_HS_9:
1884         case SQ_ALU_CONST_CACHE_HS_10:
1885         case SQ_ALU_CONST_CACHE_HS_11:
1886         case SQ_ALU_CONST_CACHE_HS_12:
1887         case SQ_ALU_CONST_CACHE_HS_13:
1888         case SQ_ALU_CONST_CACHE_HS_14:
1889         case SQ_ALU_CONST_CACHE_HS_15:
1890         case SQ_ALU_CONST_CACHE_LS_0:
1891         case SQ_ALU_CONST_CACHE_LS_1:
1892         case SQ_ALU_CONST_CACHE_LS_2:
1893         case SQ_ALU_CONST_CACHE_LS_3:
1894         case SQ_ALU_CONST_CACHE_LS_4:
1895         case SQ_ALU_CONST_CACHE_LS_5:
1896         case SQ_ALU_CONST_CACHE_LS_6:
1897         case SQ_ALU_CONST_CACHE_LS_7:
1898         case SQ_ALU_CONST_CACHE_LS_8:
1899         case SQ_ALU_CONST_CACHE_LS_9:
1900         case SQ_ALU_CONST_CACHE_LS_10:
1901         case SQ_ALU_CONST_CACHE_LS_11:
1902         case SQ_ALU_CONST_CACHE_LS_12:
1903         case SQ_ALU_CONST_CACHE_LS_13:
1904         case SQ_ALU_CONST_CACHE_LS_14:
1905         case SQ_ALU_CONST_CACHE_LS_15:
1906                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1907                 if (r) {
1908                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1909                                         "0x%04X\n", reg);
1910                         return -EINVAL;
1911                 }
1912                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1913                 break;
1914         case SX_MEMORY_EXPORT_BASE:
1915                 if (p->rdev->family >= CHIP_CAYMAN) {
1916                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1917                                  "0x%04X\n", reg);
1918                         return -EINVAL;
1919                 }
1920                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1921                 if (r) {
1922                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1923                                         "0x%04X\n", reg);
1924                         return -EINVAL;
1925                 }
1926                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1927                 break;
1928         case CAYMAN_SX_SCATTER_EXPORT_BASE:
1929                 if (p->rdev->family < CHIP_CAYMAN) {
1930                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1931                                  "0x%04X\n", reg);
1932                         return -EINVAL;
1933                 }
1934                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1935                 if (r) {
1936                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1937                                         "0x%04X\n", reg);
1938                         return -EINVAL;
1939                 }
1940                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1941                 break;
1942         case SX_MISC:
1943                 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1944                 break;
1945         default:
1946                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1947                 return -EINVAL;
1948         }
1949         return 0;
1950 }
1951
1952 static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1953 {
1954         u32 last_reg, m, i;
1955
1956         if (p->rdev->family >= CHIP_CAYMAN)
1957                 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1958         else
1959                 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1960
1961         i = (reg >> 7);
1962         if (i >= last_reg) {
1963                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1964                 return false;
1965         }
1966         m = 1 << ((reg >> 2) & 31);
1967         if (p->rdev->family >= CHIP_CAYMAN) {
1968                 if (!(cayman_reg_safe_bm[i] & m))
1969                         return true;
1970         } else {
1971                 if (!(evergreen_reg_safe_bm[i] & m))
1972                         return true;
1973         }
1974         dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1975         return false;
1976 }
1977
1978 static int evergreen_packet3_check(struct radeon_cs_parser *p,
1979                                    struct radeon_cs_packet *pkt)
1980 {
1981         struct radeon_cs_reloc *reloc;
1982         struct evergreen_cs_track *track;
1983         volatile u32 *ib;
1984         unsigned idx;
1985         unsigned i;
1986         unsigned start_reg, end_reg, reg;
1987         int r;
1988         u32 idx_value;
1989
1990         track = (struct evergreen_cs_track *)p->track;
1991         ib = p->ib.ptr;
1992         idx = pkt->idx + 1;
1993         idx_value = radeon_get_ib_value(p, idx);
1994
1995         switch (pkt->opcode) {
1996         case PACKET3_SET_PREDICATION:
1997         {
1998                 int pred_op;
1999                 int tmp;
2000                 uint64_t offset;
2001
2002                 if (pkt->count != 1) {
2003                         DRM_ERROR("bad SET PREDICATION\n");
2004                         return -EINVAL;
2005                 }
2006
2007                 tmp = radeon_get_ib_value(p, idx + 1);
2008                 pred_op = (tmp >> 16) & 0x7;
2009
2010                 /* for the clear predicate operation */
2011                 if (pred_op == 0)
2012                         return 0;
2013
2014                 if (pred_op > 2) {
2015                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
2016                         return -EINVAL;
2017                 }
2018
2019                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2020                 if (r) {
2021                         DRM_ERROR("bad SET PREDICATION\n");
2022                         return -EINVAL;
2023                 }
2024
2025                 offset = reloc->lobj.gpu_offset +
2026                          (idx_value & 0xfffffff0) +
2027                          ((u64)(tmp & 0xff) << 32);
2028
2029                 ib[idx + 0] = offset;
2030                 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2031         }
2032         break;
2033         case PACKET3_CONTEXT_CONTROL:
2034                 if (pkt->count != 1) {
2035                         DRM_ERROR("bad CONTEXT_CONTROL\n");
2036                         return -EINVAL;
2037                 }
2038                 break;
2039         case PACKET3_INDEX_TYPE:
2040         case PACKET3_NUM_INSTANCES:
2041         case PACKET3_CLEAR_STATE:
2042                 if (pkt->count) {
2043                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2044                         return -EINVAL;
2045                 }
2046                 break;
2047         case CAYMAN_PACKET3_DEALLOC_STATE:
2048                 if (p->rdev->family < CHIP_CAYMAN) {
2049                         DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
2050                         return -EINVAL;
2051                 }
2052                 if (pkt->count) {
2053                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
2054                         return -EINVAL;
2055                 }
2056                 break;
2057         case PACKET3_INDEX_BASE:
2058         {
2059                 uint64_t offset;
2060
2061                 if (pkt->count != 1) {
2062                         DRM_ERROR("bad INDEX_BASE\n");
2063                         return -EINVAL;
2064                 }
2065                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2066                 if (r) {
2067                         DRM_ERROR("bad INDEX_BASE\n");
2068                         return -EINVAL;
2069                 }
2070
2071                 offset = reloc->lobj.gpu_offset +
2072                          idx_value +
2073                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2074
2075                 ib[idx+0] = offset;
2076                 ib[idx+1] = upper_32_bits(offset) & 0xff;
2077
2078                 r = evergreen_cs_track_check(p);
2079                 if (r) {
2080                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2081                         return r;
2082                 }
2083                 break;
2084         }
2085         case PACKET3_DRAW_INDEX:
2086         {
2087                 uint64_t offset;
2088                 if (pkt->count != 3) {
2089                         DRM_ERROR("bad DRAW_INDEX\n");
2090                         return -EINVAL;
2091                 }
2092                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2093                 if (r) {
2094                         DRM_ERROR("bad DRAW_INDEX\n");
2095                         return -EINVAL;
2096                 }
2097
2098                 offset = reloc->lobj.gpu_offset +
2099                          idx_value +
2100                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2101
2102                 ib[idx+0] = offset;
2103                 ib[idx+1] = upper_32_bits(offset) & 0xff;
2104
2105                 r = evergreen_cs_track_check(p);
2106                 if (r) {
2107                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2108                         return r;
2109                 }
2110                 break;
2111         }
2112         case PACKET3_DRAW_INDEX_2:
2113         {
2114                 uint64_t offset;
2115
2116                 if (pkt->count != 4) {
2117                         DRM_ERROR("bad DRAW_INDEX_2\n");
2118                         return -EINVAL;
2119                 }
2120                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2121                 if (r) {
2122                         DRM_ERROR("bad DRAW_INDEX_2\n");
2123                         return -EINVAL;
2124                 }
2125
2126                 offset = reloc->lobj.gpu_offset +
2127                          radeon_get_ib_value(p, idx+1) +
2128                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2129
2130                 ib[idx+1] = offset;
2131                 ib[idx+2] = upper_32_bits(offset) & 0xff;
2132
2133                 r = evergreen_cs_track_check(p);
2134                 if (r) {
2135                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2136                         return r;
2137                 }
2138                 break;
2139         }
2140         case PACKET3_DRAW_INDEX_AUTO:
2141                 if (pkt->count != 1) {
2142                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
2143                         return -EINVAL;
2144                 }
2145                 r = evergreen_cs_track_check(p);
2146                 if (r) {
2147                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2148                         return r;
2149                 }
2150                 break;
2151         case PACKET3_DRAW_INDEX_MULTI_AUTO:
2152                 if (pkt->count != 2) {
2153                         DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
2154                         return -EINVAL;
2155                 }
2156                 r = evergreen_cs_track_check(p);
2157                 if (r) {
2158                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2159                         return r;
2160                 }
2161                 break;
2162         case PACKET3_DRAW_INDEX_IMMD:
2163                 if (pkt->count < 2) {
2164                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
2165                         return -EINVAL;
2166                 }
2167                 r = evergreen_cs_track_check(p);
2168                 if (r) {
2169                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2170                         return r;
2171                 }
2172                 break;
2173         case PACKET3_DRAW_INDEX_OFFSET:
2174                 if (pkt->count != 2) {
2175                         DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
2176                         return -EINVAL;
2177                 }
2178                 r = evergreen_cs_track_check(p);
2179                 if (r) {
2180                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2181                         return r;
2182                 }
2183                 break;
2184         case PACKET3_DRAW_INDEX_OFFSET_2:
2185                 if (pkt->count != 3) {
2186                         DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2187                         return -EINVAL;
2188                 }
2189                 r = evergreen_cs_track_check(p);
2190                 if (r) {
2191                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2192                         return r;
2193                 }
2194                 break;
2195         case PACKET3_DISPATCH_DIRECT:
2196                 if (pkt->count != 3) {
2197                         DRM_ERROR("bad DISPATCH_DIRECT\n");
2198                         return -EINVAL;
2199                 }
2200                 r = evergreen_cs_track_check(p);
2201                 if (r) {
2202                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2203                         return r;
2204                 }
2205                 break;
2206         case PACKET3_DISPATCH_INDIRECT:
2207                 if (pkt->count != 1) {
2208                         DRM_ERROR("bad DISPATCH_INDIRECT\n");
2209                         return -EINVAL;
2210                 }
2211                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2212                 if (r) {
2213                         DRM_ERROR("bad DISPATCH_INDIRECT\n");
2214                         return -EINVAL;
2215                 }
2216                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2217                 r = evergreen_cs_track_check(p);
2218                 if (r) {
2219                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2220                         return r;
2221                 }
2222                 break;
2223         case PACKET3_WAIT_REG_MEM:
2224                 if (pkt->count != 5) {
2225                         DRM_ERROR("bad WAIT_REG_MEM\n");
2226                         return -EINVAL;
2227                 }
2228                 /* bit 4 is reg (0) or mem (1) */
2229                 if (idx_value & 0x10) {
2230                         uint64_t offset;
2231
2232                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2233                         if (r) {
2234                                 DRM_ERROR("bad WAIT_REG_MEM\n");
2235                                 return -EINVAL;
2236                         }
2237
2238                         offset = reloc->lobj.gpu_offset +
2239                                  (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2240                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2241
2242                         ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2243                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2244                 }
2245                 break;
2246         case PACKET3_CP_DMA:
2247         {
2248                 u32 command, size, info;
2249                 u64 offset, tmp;
2250                 if (pkt->count != 4) {
2251                         DRM_ERROR("bad CP DMA\n");
2252                         return -EINVAL;
2253                 }
2254                 command = radeon_get_ib_value(p, idx+4);
2255                 size = command & 0x1fffff;
2256                 info = radeon_get_ib_value(p, idx+1);
2257                 if (command & PACKET3_CP_DMA_CMD_SAS) {
2258                         /* src address space is register */
2259                         /* GDS is ok */
2260                         if (((info & 0x60000000) >> 29) != 1) {
2261                                 DRM_ERROR("CP DMA SAS not supported\n");
2262                                 return -EINVAL;
2263                         }
2264                 } else {
2265                         if (command & PACKET3_CP_DMA_CMD_SAIC) {
2266                                 DRM_ERROR("CP DMA SAIC only supported for registers\n");
2267                                 return -EINVAL;
2268                         }
2269                         /* src address space is memory */
2270                         if (((info & 0x60000000) >> 29) == 0) {
2271                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2272                                 if (r) {
2273                                         DRM_ERROR("bad CP DMA SRC\n");
2274                                         return -EINVAL;
2275                                 }
2276
2277                                 tmp = radeon_get_ib_value(p, idx) +
2278                                         ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
2279
2280                                 offset = reloc->lobj.gpu_offset + tmp;
2281
2282                                 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2283                                         dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",
2284                                                  tmp + size, radeon_bo_size(reloc->robj));
2285                                         return -EINVAL;
2286                                 }
2287
2288                                 ib[idx] = offset;
2289                                 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2290                         } else if (((info & 0x60000000) >> 29) != 2) {
2291                                 DRM_ERROR("bad CP DMA SRC_SEL\n");
2292                                 return -EINVAL;
2293                         }
2294                 }
2295                 if (command & PACKET3_CP_DMA_CMD_DAS) {
2296                         /* dst address space is register */
2297                         /* GDS is ok */
2298                         if (((info & 0x00300000) >> 20) != 1) {
2299                                 DRM_ERROR("CP DMA DAS not supported\n");
2300                                 return -EINVAL;
2301                         }
2302                 } else {
2303                         /* dst address space is memory */
2304                         if (command & PACKET3_CP_DMA_CMD_DAIC) {
2305                                 DRM_ERROR("CP DMA DAIC only supported for registers\n");
2306                                 return -EINVAL;
2307                         }
2308                         if (((info & 0x00300000) >> 20) == 0) {
2309                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2310                                 if (r) {
2311                                         DRM_ERROR("bad CP DMA DST\n");
2312                                         return -EINVAL;
2313                                 }
2314
2315                                 tmp = radeon_get_ib_value(p, idx+2) +
2316                                         ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);
2317
2318                                 offset = reloc->lobj.gpu_offset + tmp;
2319
2320                                 if ((tmp + size) > radeon_bo_size(reloc->robj)) {
2321                                         dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",
2322                                                  tmp + size, radeon_bo_size(reloc->robj));
2323                                         return -EINVAL;
2324                                 }
2325
2326                                 ib[idx+2] = offset;
2327                                 ib[idx+3] = upper_32_bits(offset) & 0xff;
2328                         } else {
2329                                 DRM_ERROR("bad CP DMA DST_SEL\n");
2330                                 return -EINVAL;
2331                         }
2332                 }
2333                 break;
2334         }
2335         case PACKET3_SURFACE_SYNC:
2336                 if (pkt->count != 3) {
2337                         DRM_ERROR("bad SURFACE_SYNC\n");
2338                         return -EINVAL;
2339                 }
2340                 /* 0xffffffff/0x0 is flush all cache flag */
2341                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2342                     radeon_get_ib_value(p, idx + 2) != 0) {
2343                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2344                         if (r) {
2345                                 DRM_ERROR("bad SURFACE_SYNC\n");
2346                                 return -EINVAL;
2347                         }
2348                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2349                 }
2350                 break;
2351         case PACKET3_EVENT_WRITE:
2352                 if (pkt->count != 2 && pkt->count != 0) {
2353                         DRM_ERROR("bad EVENT_WRITE\n");
2354                         return -EINVAL;
2355                 }
2356                 if (pkt->count) {
2357                         uint64_t offset;
2358
2359                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2360                         if (r) {
2361                                 DRM_ERROR("bad EVENT_WRITE\n");
2362                                 return -EINVAL;
2363                         }
2364                         offset = reloc->lobj.gpu_offset +
2365                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2366                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2367
2368                         ib[idx+1] = offset & 0xfffffff8;
2369                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2370                 }
2371                 break;
2372         case PACKET3_EVENT_WRITE_EOP:
2373         {
2374                 uint64_t offset;
2375
2376                 if (pkt->count != 4) {
2377                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
2378                         return -EINVAL;
2379                 }
2380                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2381                 if (r) {
2382                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
2383                         return -EINVAL;
2384                 }
2385
2386                 offset = reloc->lobj.gpu_offset +
2387                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2388                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2389
2390                 ib[idx+1] = offset & 0xfffffffc;
2391                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2392                 break;
2393         }
2394         case PACKET3_EVENT_WRITE_EOS:
2395         {
2396                 uint64_t offset;
2397
2398                 if (pkt->count != 3) {
2399                         DRM_ERROR("bad EVENT_WRITE_EOS\n");
2400                         return -EINVAL;
2401                 }
2402                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2403                 if (r) {
2404                         DRM_ERROR("bad EVENT_WRITE_EOS\n");
2405                         return -EINVAL;
2406                 }
2407
2408                 offset = reloc->lobj.gpu_offset +
2409                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2410                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2411
2412                 ib[idx+1] = offset & 0xfffffffc;
2413                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2414                 break;
2415         }
2416         case PACKET3_SET_CONFIG_REG:
2417                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2418                 end_reg = 4 * pkt->count + start_reg - 4;
2419                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2420                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2421                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2422                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2423                         return -EINVAL;
2424                 }
2425                 for (i = 0; i < pkt->count; i++) {
2426                         reg = start_reg + (4 * i);
2427                         r = evergreen_cs_check_reg(p, reg, idx+1+i);
2428                         if (r)
2429                                 return r;
2430                 }
2431                 break;
2432         case PACKET3_SET_CONTEXT_REG:
2433                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2434                 end_reg = 4 * pkt->count + start_reg - 4;
2435                 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2436                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2437                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2438                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2439                         return -EINVAL;
2440                 }
2441                 for (i = 0; i < pkt->count; i++) {
2442                         reg = start_reg + (4 * i);
2443                         r = evergreen_cs_check_reg(p, reg, idx+1+i);
2444                         if (r)
2445                                 return r;
2446                 }
2447                 break;
2448         case PACKET3_SET_RESOURCE:
2449                 if (pkt->count % 8) {
2450                         DRM_ERROR("bad SET_RESOURCE\n");
2451                         return -EINVAL;
2452                 }
2453                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2454                 end_reg = 4 * pkt->count + start_reg - 4;
2455                 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2456                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
2457                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
2458                         DRM_ERROR("bad SET_RESOURCE\n");
2459                         return -EINVAL;
2460                 }
2461                 for (i = 0; i < (pkt->count / 8); i++) {
2462                         struct radeon_bo *texture, *mipmap;
2463                         u32 toffset, moffset;
2464                         u32 size, offset, mip_address, tex_dim;
2465
2466                         switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2467                         case SQ_TEX_VTX_VALID_TEXTURE:
2468                                 /* tex base */
2469                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2470                                 if (r) {
2471                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
2472                                         return -EINVAL;
2473                                 }
2474                                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2475                                         ib[idx+1+(i*8)+1] |=
2476                                                 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2477                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2478                                                 unsigned bankw, bankh, mtaspect, tile_split;
2479
2480                                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
2481                                                                         &bankw, &bankh, &mtaspect,
2482                                                                         &tile_split);
2483                                                 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2484                                                 ib[idx+1+(i*8)+7] |=
2485                                                         TEX_BANK_WIDTH(bankw) |
2486                                                         TEX_BANK_HEIGHT(bankh) |
2487                                                         MACRO_TILE_ASPECT(mtaspect) |
2488                                                         TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2489                                         }
2490                                 }
2491                                 texture = reloc->robj;
2492                                 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2493
2494                                 /* tex mip base */
2495                                 tex_dim = ib[idx+1+(i*8)+0] & 0x7;
2496                                 mip_address = ib[idx+1+(i*8)+3];
2497
2498                                 if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&
2499                                     !mip_address &&
2500                                     !evergreen_cs_packet_next_is_pkt3_nop(p)) {
2501                                         /* MIP_ADDRESS should point to FMASK for an MSAA texture.
2502                                          * It should be 0 if FMASK is disabled. */
2503                                         moffset = 0;
2504                                         mipmap = NULL;
2505                                 } else {
2506                                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2507                                         if (r) {
2508                                                 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2509                                                 return -EINVAL;
2510                                         }
2511                                         moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2512                                         mipmap = reloc->robj;
2513                                 }
2514
2515                                 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
2516                                 if (r)
2517                                         return r;
2518                                 ib[idx+1+(i*8)+2] += toffset;
2519                                 ib[idx+1+(i*8)+3] += moffset;
2520                                 break;
2521                         case SQ_TEX_VTX_VALID_BUFFER:
2522                         {
2523                                 uint64_t offset64;
2524                                 /* vtx base */
2525                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2526                                 if (r) {
2527                                         DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2528                                         return -EINVAL;
2529                                 }
2530                                 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2531                                 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2532                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2533                                         /* force size to size of the buffer */
2534                                         dev_warn(p->dev, "vbo resource seems too big for the bo\n");
2535                                         ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2536                                 }
2537
2538                                 offset64 = reloc->lobj.gpu_offset + offset;
2539                                 ib[idx+1+(i*8)+0] = offset64;
2540                                 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2541                                                     (upper_32_bits(offset64) & 0xff);
2542                                 break;
2543                         }
2544                         case SQ_TEX_VTX_INVALID_TEXTURE:
2545                         case SQ_TEX_VTX_INVALID_BUFFER:
2546                         default:
2547                                 DRM_ERROR("bad SET_RESOURCE\n");
2548                                 return -EINVAL;
2549                         }
2550                 }
2551                 break;
2552         case PACKET3_SET_ALU_CONST:
2553                 /* XXX fix me ALU const buffers only */
2554                 break;
2555         case PACKET3_SET_BOOL_CONST:
2556                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2557                 end_reg = 4 * pkt->count + start_reg - 4;
2558                 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2559                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2560                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2561                         DRM_ERROR("bad SET_BOOL_CONST\n");
2562                         return -EINVAL;
2563                 }
2564                 break;
2565         case PACKET3_SET_LOOP_CONST:
2566                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2567                 end_reg = 4 * pkt->count + start_reg - 4;
2568                 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2569                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2570                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2571                         DRM_ERROR("bad SET_LOOP_CONST\n");
2572                         return -EINVAL;
2573                 }
2574                 break;
2575         case PACKET3_SET_CTL_CONST:
2576                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2577                 end_reg = 4 * pkt->count + start_reg - 4;
2578                 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2579                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2580                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2581                         DRM_ERROR("bad SET_CTL_CONST\n");
2582                         return -EINVAL;
2583                 }
2584                 break;
2585         case PACKET3_SET_SAMPLER:
2586                 if (pkt->count % 3) {
2587                         DRM_ERROR("bad SET_SAMPLER\n");
2588                         return -EINVAL;
2589                 }
2590                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2591                 end_reg = 4 * pkt->count + start_reg - 4;
2592                 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2593                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
2594                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
2595                         DRM_ERROR("bad SET_SAMPLER\n");
2596                         return -EINVAL;
2597                 }
2598                 break;
2599         case PACKET3_STRMOUT_BUFFER_UPDATE:
2600                 if (pkt->count != 4) {
2601                         DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2602                         return -EINVAL;
2603                 }
2604                 /* Updating memory at DST_ADDRESS. */
2605                 if (idx_value & 0x1) {
2606                         u64 offset;
2607                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2608                         if (r) {
2609                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2610                                 return -EINVAL;
2611                         }
2612                         offset = radeon_get_ib_value(p, idx+1);
2613                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2614                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2615                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2616                                           offset + 4, radeon_bo_size(reloc->robj));
2617                                 return -EINVAL;
2618                         }
2619                         offset += reloc->lobj.gpu_offset;
2620                         ib[idx+1] = offset;
2621                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2622                 }
2623                 /* Reading data from SRC_ADDRESS. */
2624                 if (((idx_value >> 1) & 0x3) == 2) {
2625                         u64 offset;
2626                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2627                         if (r) {
2628                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2629                                 return -EINVAL;
2630                         }
2631                         offset = radeon_get_ib_value(p, idx+3);
2632                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2633                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2634                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2635                                           offset + 4, radeon_bo_size(reloc->robj));
2636                                 return -EINVAL;
2637                         }
2638                         offset += reloc->lobj.gpu_offset;
2639                         ib[idx+3] = offset;
2640                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2641                 }
2642                 break;
2643         case PACKET3_COPY_DW:
2644                 if (pkt->count != 4) {
2645                         DRM_ERROR("bad COPY_DW (invalid count)\n");
2646                         return -EINVAL;
2647                 }
2648                 if (idx_value & 0x1) {
2649                         u64 offset;
2650                         /* SRC is memory. */
2651                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2652                         if (r) {
2653                                 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2654                                 return -EINVAL;
2655                         }
2656                         offset = radeon_get_ib_value(p, idx+1);
2657                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2658                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2659                                 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2660                                           offset + 4, radeon_bo_size(reloc->robj));
2661                                 return -EINVAL;
2662                         }
2663                         offset += reloc->lobj.gpu_offset;
2664                         ib[idx+1] = offset;
2665                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2666                 } else {
2667                         /* SRC is a reg. */
2668                         reg = radeon_get_ib_value(p, idx+1) << 2;
2669                         if (!evergreen_is_safe_reg(p, reg, idx+1))
2670                                 return -EINVAL;
2671                 }
2672                 if (idx_value & 0x2) {
2673                         u64 offset;
2674                         /* DST is memory. */
2675                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2676                         if (r) {
2677                                 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2678                                 return -EINVAL;
2679                         }
2680                         offset = radeon_get_ib_value(p, idx+3);
2681                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2682                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2683                                 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2684                                           offset + 4, radeon_bo_size(reloc->robj));
2685                                 return -EINVAL;
2686                         }
2687                         offset += reloc->lobj.gpu_offset;
2688                         ib[idx+3] = offset;
2689                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2690                 } else {
2691                         /* DST is a reg. */
2692                         reg = radeon_get_ib_value(p, idx+3) << 2;
2693                         if (!evergreen_is_safe_reg(p, reg, idx+3))
2694                                 return -EINVAL;
2695                 }
2696                 break;
2697         case PACKET3_NOP:
2698                 break;
2699         default:
2700                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2701                 return -EINVAL;
2702         }
2703         return 0;
2704 }
2705
2706 int evergreen_cs_parse(struct radeon_cs_parser *p)
2707 {
2708         struct radeon_cs_packet pkt;
2709         struct evergreen_cs_track *track;
2710         u32 tmp;
2711         int r;
2712
2713         if (p->track == NULL) {
2714                 /* initialize tracker, we are in kms */
2715                 track = kzalloc(sizeof(*track), GFP_KERNEL);
2716                 if (track == NULL)
2717                         return -ENOMEM;
2718                 evergreen_cs_track_init(track);
2719                 if (p->rdev->family >= CHIP_CAYMAN)
2720                         tmp = p->rdev->config.cayman.tile_config;
2721                 else
2722                         tmp = p->rdev->config.evergreen.tile_config;
2723
2724                 switch (tmp & 0xf) {
2725                 case 0:
2726                         track->npipes = 1;
2727                         break;
2728                 case 1:
2729                 default:
2730                         track->npipes = 2;
2731                         break;
2732                 case 2:
2733                         track->npipes = 4;
2734                         break;
2735                 case 3:
2736                         track->npipes = 8;
2737                         break;
2738                 }
2739
2740                 switch ((tmp & 0xf0) >> 4) {
2741                 case 0:
2742                         track->nbanks = 4;
2743                         break;
2744                 case 1:
2745                 default:
2746                         track->nbanks = 8;
2747                         break;
2748                 case 2:
2749                         track->nbanks = 16;
2750                         break;
2751                 }
2752
2753                 switch ((tmp & 0xf00) >> 8) {
2754                 case 0:
2755                         track->group_size = 256;
2756                         break;
2757                 case 1:
2758                 default:
2759                         track->group_size = 512;
2760                         break;
2761                 }
2762
2763                 switch ((tmp & 0xf000) >> 12) {
2764                 case 0:
2765                         track->row_size = 1;
2766                         break;
2767                 case 1:
2768                 default:
2769                         track->row_size = 2;
2770                         break;
2771                 case 2:
2772                         track->row_size = 4;
2773                         break;
2774                 }
2775
2776                 p->track = track;
2777         }
2778         do {
2779                 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
2780                 if (r) {
2781                         kfree(p->track);
2782                         p->track = NULL;
2783                         return r;
2784                 }
2785                 p->idx += pkt.count + 2;
2786                 switch (pkt.type) {
2787                 case PACKET_TYPE0:
2788                         r = evergreen_cs_parse_packet0(p, &pkt);
2789                         break;
2790                 case PACKET_TYPE2:
2791                         break;
2792                 case PACKET_TYPE3:
2793                         r = evergreen_packet3_check(p, &pkt);
2794                         break;
2795                 default:
2796                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2797                         kfree(p->track);
2798                         p->track = NULL;
2799                         return -EINVAL;
2800                 }
2801                 if (r) {
2802                         kfree(p->track);
2803                         p->track = NULL;
2804                         return r;
2805                 }
2806         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2807 #if 0
2808         for (r = 0; r < p->ib.length_dw; r++) {
2809                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib.ptr[r]);
2810                 mdelay(1);
2811         }
2812 #endif
2813         kfree(p->track);
2814         p->track = NULL;
2815         return 0;
2816 }
2817
2818 /* vm parser */
2819 static bool evergreen_vm_reg_valid(u32 reg)
2820 {
2821         /* context regs are fine */
2822         if (reg >= 0x28000)
2823                 return true;
2824
2825         /* check config regs */
2826         switch (reg) {
2827         case GRBM_GFX_INDEX:
2828         case CP_STRMOUT_CNTL:
2829         case CP_COHER_CNTL:
2830         case CP_COHER_SIZE:
2831         case VGT_VTX_VECT_EJECT_REG:
2832         case VGT_CACHE_INVALIDATION:
2833         case VGT_GS_VERTEX_REUSE:
2834         case VGT_PRIMITIVE_TYPE:
2835         case VGT_INDEX_TYPE:
2836         case VGT_NUM_INDICES:
2837         case VGT_NUM_INSTANCES:
2838         case VGT_COMPUTE_DIM_X:
2839         case VGT_COMPUTE_DIM_Y:
2840         case VGT_COMPUTE_DIM_Z:
2841         case VGT_COMPUTE_START_X:
2842         case VGT_COMPUTE_START_Y:
2843         case VGT_COMPUTE_START_Z:
2844         case VGT_COMPUTE_INDEX:
2845         case VGT_COMPUTE_THREAD_GROUP_SIZE:
2846         case VGT_HS_OFFCHIP_PARAM:
2847         case PA_CL_ENHANCE:
2848         case PA_SU_LINE_STIPPLE_VALUE:
2849         case PA_SC_LINE_STIPPLE_STATE:
2850         case PA_SC_ENHANCE:
2851         case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
2852         case SQ_DYN_GPR_SIMD_LOCK_EN:
2853         case SQ_CONFIG:
2854         case SQ_GPR_RESOURCE_MGMT_1:
2855         case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
2856         case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
2857         case SQ_CONST_MEM_BASE:
2858         case SQ_STATIC_THREAD_MGMT_1:
2859         case SQ_STATIC_THREAD_MGMT_2:
2860         case SQ_STATIC_THREAD_MGMT_3:
2861         case SPI_CONFIG_CNTL:
2862         case SPI_CONFIG_CNTL_1:
2863         case TA_CNTL_AUX:
2864         case DB_DEBUG:
2865         case DB_DEBUG2:
2866         case DB_DEBUG3:
2867         case DB_DEBUG4:
2868         case DB_WATERMARKS:
2869         case TD_PS_BORDER_COLOR_INDEX:
2870         case TD_PS_BORDER_COLOR_RED:
2871         case TD_PS_BORDER_COLOR_GREEN:
2872         case TD_PS_BORDER_COLOR_BLUE:
2873         case TD_PS_BORDER_COLOR_ALPHA:
2874         case TD_VS_BORDER_COLOR_INDEX:
2875         case TD_VS_BORDER_COLOR_RED:
2876         case TD_VS_BORDER_COLOR_GREEN:
2877         case TD_VS_BORDER_COLOR_BLUE:
2878         case TD_VS_BORDER_COLOR_ALPHA:
2879         case TD_GS_BORDER_COLOR_INDEX:
2880         case TD_GS_BORDER_COLOR_RED:
2881         case TD_GS_BORDER_COLOR_GREEN:
2882         case TD_GS_BORDER_COLOR_BLUE:
2883         case TD_GS_BORDER_COLOR_ALPHA:
2884         case TD_HS_BORDER_COLOR_INDEX:
2885         case TD_HS_BORDER_COLOR_RED:
2886         case TD_HS_BORDER_COLOR_GREEN:
2887         case TD_HS_BORDER_COLOR_BLUE:
2888         case TD_HS_BORDER_COLOR_ALPHA:
2889         case TD_LS_BORDER_COLOR_INDEX:
2890         case TD_LS_BORDER_COLOR_RED:
2891         case TD_LS_BORDER_COLOR_GREEN:
2892         case TD_LS_BORDER_COLOR_BLUE:
2893         case TD_LS_BORDER_COLOR_ALPHA:
2894         case TD_CS_BORDER_COLOR_INDEX:
2895         case TD_CS_BORDER_COLOR_RED:
2896         case TD_CS_BORDER_COLOR_GREEN:
2897         case TD_CS_BORDER_COLOR_BLUE:
2898         case TD_CS_BORDER_COLOR_ALPHA:
2899         case SQ_ESGS_RING_SIZE:
2900         case SQ_GSVS_RING_SIZE:
2901         case SQ_ESTMP_RING_SIZE:
2902         case SQ_GSTMP_RING_SIZE:
2903         case SQ_HSTMP_RING_SIZE:
2904         case SQ_LSTMP_RING_SIZE:
2905         case SQ_PSTMP_RING_SIZE:
2906         case SQ_VSTMP_RING_SIZE:
2907         case SQ_ESGS_RING_ITEMSIZE:
2908         case SQ_ESTMP_RING_ITEMSIZE:
2909         case SQ_GSTMP_RING_ITEMSIZE:
2910         case SQ_GSVS_RING_ITEMSIZE:
2911         case SQ_GS_VERT_ITEMSIZE:
2912         case SQ_GS_VERT_ITEMSIZE_1:
2913         case SQ_GS_VERT_ITEMSIZE_2:
2914         case SQ_GS_VERT_ITEMSIZE_3:
2915         case SQ_GSVS_RING_OFFSET_1:
2916         case SQ_GSVS_RING_OFFSET_2:
2917         case SQ_GSVS_RING_OFFSET_3:
2918         case SQ_HSTMP_RING_ITEMSIZE:
2919         case SQ_LSTMP_RING_ITEMSIZE:
2920         case SQ_PSTMP_RING_ITEMSIZE:
2921         case SQ_VSTMP_RING_ITEMSIZE:
2922         case VGT_TF_RING_SIZE:
2923         case SQ_ESGS_RING_BASE:
2924         case SQ_GSVS_RING_BASE:
2925         case SQ_ESTMP_RING_BASE:
2926         case SQ_GSTMP_RING_BASE:
2927         case SQ_HSTMP_RING_BASE:
2928         case SQ_LSTMP_RING_BASE:
2929         case SQ_PSTMP_RING_BASE:
2930         case SQ_VSTMP_RING_BASE:
2931         case CAYMAN_VGT_OFFCHIP_LDS_BASE:
2932         case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2933                 return true;
2934         default:
2935                 DRM_ERROR("Invalid register 0x%x in CS\n", reg);
2936                 return false;
2937         }
2938 }
2939
2940 static int evergreen_vm_packet3_check(struct radeon_device *rdev,
2941                                       u32 *ib, struct radeon_cs_packet *pkt)
2942 {
2943         u32 idx = pkt->idx + 1;
2944         u32 idx_value = ib[idx];
2945         u32 start_reg, end_reg, reg, i;
2946         u32 command, info;
2947
2948         switch (pkt->opcode) {
2949         case PACKET3_NOP:
2950         case PACKET3_SET_BASE:
2951         case PACKET3_CLEAR_STATE:
2952         case PACKET3_INDEX_BUFFER_SIZE:
2953         case PACKET3_DISPATCH_DIRECT:
2954         case PACKET3_DISPATCH_INDIRECT:
2955         case PACKET3_MODE_CONTROL:
2956         case PACKET3_SET_PREDICATION:
2957         case PACKET3_COND_EXEC:
2958         case PACKET3_PRED_EXEC:
2959         case PACKET3_DRAW_INDIRECT:
2960         case PACKET3_DRAW_INDEX_INDIRECT:
2961         case PACKET3_INDEX_BASE:
2962         case PACKET3_DRAW_INDEX_2:
2963         case PACKET3_CONTEXT_CONTROL:
2964         case PACKET3_DRAW_INDEX_OFFSET:
2965         case PACKET3_INDEX_TYPE:
2966         case PACKET3_DRAW_INDEX:
2967         case PACKET3_DRAW_INDEX_AUTO:
2968         case PACKET3_DRAW_INDEX_IMMD:
2969         case PACKET3_NUM_INSTANCES:
2970         case PACKET3_DRAW_INDEX_MULTI_AUTO:
2971         case PACKET3_STRMOUT_BUFFER_UPDATE:
2972         case PACKET3_DRAW_INDEX_OFFSET_2:
2973         case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2974         case PACKET3_MPEG_INDEX:
2975         case PACKET3_WAIT_REG_MEM:
2976         case PACKET3_MEM_WRITE:
2977         case PACKET3_SURFACE_SYNC:
2978         case PACKET3_EVENT_WRITE:
2979         case PACKET3_EVENT_WRITE_EOP:
2980         case PACKET3_EVENT_WRITE_EOS:
2981         case PACKET3_SET_CONTEXT_REG:
2982         case PACKET3_SET_BOOL_CONST:
2983         case PACKET3_SET_LOOP_CONST:
2984         case PACKET3_SET_RESOURCE:
2985         case PACKET3_SET_SAMPLER:
2986         case PACKET3_SET_CTL_CONST:
2987         case PACKET3_SET_RESOURCE_OFFSET:
2988         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2989         case PACKET3_SET_RESOURCE_INDIRECT:
2990         case CAYMAN_PACKET3_DEALLOC_STATE:
2991                 break;
2992         case PACKET3_COND_WRITE:
2993                 if (idx_value & 0x100) {
2994                         reg = ib[idx + 5] * 4;
2995                         if (!evergreen_vm_reg_valid(reg))
2996                                 return -EINVAL;
2997                 }
2998                 break;
2999         case PACKET3_COPY_DW:
3000                 if (idx_value & 0x2) {
3001                         reg = ib[idx + 3] * 4;
3002                         if (!evergreen_vm_reg_valid(reg))
3003                                 return -EINVAL;
3004                 }
3005                 break;
3006         case PACKET3_SET_CONFIG_REG:
3007                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
3008                 end_reg = 4 * pkt->count + start_reg - 4;
3009                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
3010                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
3011                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
3012                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
3013                         return -EINVAL;
3014                 }
3015                 for (i = 0; i < pkt->count; i++) {
3016                         reg = start_reg + (4 * i);
3017                         if (!evergreen_vm_reg_valid(reg))
3018                                 return -EINVAL;
3019                 }
3020                 break;
3021         case PACKET3_CP_DMA:
3022                 command = ib[idx + 4];
3023                 info = ib[idx + 1];
3024                 if (command & PACKET3_CP_DMA_CMD_SAS) {
3025                         /* src address space is register */
3026                         if (((info & 0x60000000) >> 29) == 0) {
3027                                 start_reg = idx_value << 2;
3028                                 if (command & PACKET3_CP_DMA_CMD_SAIC) {
3029                                         reg = start_reg;
3030                                         if (!evergreen_vm_reg_valid(reg)) {
3031                                                 DRM_ERROR("CP DMA Bad SRC register\n");
3032                                                 return -EINVAL;
3033                                         }
3034                                 } else {
3035                                         for (i = 0; i < (command & 0x1fffff); i++) {
3036                                                 reg = start_reg + (4 * i);
3037                                                 if (!evergreen_vm_reg_valid(reg)) {
3038                                                         DRM_ERROR("CP DMA Bad SRC register\n");
3039                                                         return -EINVAL;
3040                                                 }
3041                                         }
3042                                 }
3043                         }
3044                 }
3045                 if (command & PACKET3_CP_DMA_CMD_DAS) {
3046                         /* dst address space is register */
3047                         if (((info & 0x00300000) >> 20) == 0) {
3048                                 start_reg = ib[idx + 2];
3049                                 if (command & PACKET3_CP_DMA_CMD_DAIC) {
3050                                         reg = start_reg;
3051                                         if (!evergreen_vm_reg_valid(reg)) {
3052                                                 DRM_ERROR("CP DMA Bad DST register\n");
3053                                                 return -EINVAL;
3054                                         }
3055                                 } else {
3056                                         for (i = 0; i < (command & 0x1fffff); i++) {
3057                                                 reg = start_reg + (4 * i);
3058                                                 if (!evergreen_vm_reg_valid(reg)) {
3059                                                         DRM_ERROR("CP DMA Bad DST register\n");
3060                                                         return -EINVAL;
3061                                                 }
3062                                         }
3063                                 }
3064                         }
3065                 }
3066                 break;
3067         default:
3068                 return -EINVAL;
3069         }
3070         return 0;
3071 }
3072
3073 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3074 {
3075         int ret = 0;
3076         u32 idx = 0;
3077         struct radeon_cs_packet pkt;
3078
3079         do {
3080                 pkt.idx = idx;
3081                 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
3082                 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
3083                 pkt.one_reg_wr = 0;
3084                 switch (pkt.type) {
3085                 case PACKET_TYPE0:
3086                         dev_err(rdev->dev, "Packet0 not allowed!\n");
3087                         ret = -EINVAL;
3088                         break;
3089                 case PACKET_TYPE2:
3090                         idx += 1;
3091                         break;
3092                 case PACKET_TYPE3:
3093                         pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
3094                         ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
3095                         idx += pkt.count + 2;
3096                         break;
3097                 default:
3098                         dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
3099                         ret = -EINVAL;
3100                         break;
3101                 }
3102                 if (ret)
3103                         break;
3104         } while (idx < ib->length_dw);
3105
3106         return ret;
3107 }