drivers/gpu/drm/radeon/evergreen_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *          Rafał Miłecki
  26  */
  27 #include <linux/hdmi.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "evergreend.h"
  33 #include "atom.h"
  34
  35 extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
  36 extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
  37 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
  38 extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
  39                                            struct drm_display_mode *mode);
  40
  41 /*
  42  * update the N and CTS parameters for a given pixel clock rate
  43  */
  44 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  45 {
  46         struct drm_device *dev = encoder->dev;
  47         struct radeon_device *rdev = dev->dev_private;
  48         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  49         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  50         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  51         uint32_t offset = dig->afmt->offset;
  52
  53         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  54         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  55
  56         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  57         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  58
  59         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  60         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  61 }
  62
  63 static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
  64                                            struct drm_display_mode *mode)
  65 {
  66         struct radeon_device *rdev = encoder->dev->dev_private;
  67         struct drm_connector *connector;
  68         struct radeon_connector *radeon_connector = NULL;
  69         u32 tmp = 0;
  70
  71         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  72                 if (connector->encoder == encoder) {
  73                         radeon_connector = to_radeon_connector(connector);
  74                         break;
  75                 }
  76         }
  77
  78         if (!radeon_connector) {
  79                 DRM_ERROR("Couldn't find encoder's connector\n");
  80                 return;
  81         }
  82
  83         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  84                 if (connector->latency_present[1])
  85                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
  86                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
  87                 else
  88                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
  89         } else {
  90                 if (connector->latency_present[0])
  91                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
  92                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
  93                 else
  94                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
  95         }
  96         WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
  97 }
  98
  99 static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
 100 {
 101         struct radeon_device *rdev = encoder->dev->dev_private;
 102         struct drm_connector *connector;
 103         struct radeon_connector *radeon_connector = NULL;
 104         u32 tmp;
 105         u8 *sadb;
 106         int sad_count;
 107
 108         /* XXX: setting this register causes hangs on some asics */
 109         return;
 110
 111         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 112                 if (connector->encoder == encoder) {
 113                         radeon_connector = to_radeon_connector(connector);
 114                         break;
 115                 }
 116         }
 117
 118         if (!radeon_connector) {
 119                 DRM_ERROR("Couldn't find encoder's connector\n");
 120                 return;
 121         }
 122
 123         sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
 124         if (sad_count < 0) {
 125                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
 126                 return;
 127         }
 128
 129         /* program the speaker allocation */
 130         tmp = RREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
 131         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 132         /* set HDMI mode */
 133         tmp |= HDMI_CONNECTION;
 134         if (sad_count)
 135                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 136         else
 137                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 138         WREG32(AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
 139
 140         kfree(sadb);
 141 }
 142
 143 static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
 144 {
 145         struct radeon_device *rdev = encoder->dev->dev_private;
 146         struct drm_connector *connector;
 147         struct radeon_connector *radeon_connector = NULL;
 148         struct cea_sad *sads;
 149         int i, sad_count;
 150
 151         static const u16 eld_reg_to_type[][2] = {
 152                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 153                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 154                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 155                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 156                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 157                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 158                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 159                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 160                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 161                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 162                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 163                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 164         };
 165
 166         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 167                 if (connector->encoder == encoder) {
 168                         radeon_connector = to_radeon_connector(connector);
 169                         break;
 170                 }
 171         }
 172
 173         if (!radeon_connector) {
 174                 DRM_ERROR("Couldn't find encoder's connector\n");
 175                 return;
 176         }
 177
 178         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
 179         if (sad_count < 0) {
 180                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 181                 return;
 182         }
 183         BUG_ON(!sads);
 184
 185         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 186                 u32 value = 0;
 187                 int j;
 188
 189                 for (j = 0; j < sad_count; j++) {
 190                         struct cea_sad *sad = &sads[j];
 191
 192                         if (sad->format == eld_reg_to_type[i][1]) {
 193                                 value = MAX_CHANNELS(sad->channels) |
 194                                         DESCRIPTOR_BYTE_2(sad->byte2) |
 195                                         SUPPORTED_FREQUENCIES(sad->freq);
 196                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 197                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
 198                                 break;
 199                         }
 200                 }
 201                 WREG32(eld_reg_to_type[i][0], value);
 202         }
 203
 204         kfree(sads);
 205 }
 206
 207 /*
 208  * build a HDMI Video Info Frame
 209  */
 210 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 211                                                 void *buffer, size_t size)
 212 {
 213         struct drm_device *dev = encoder->dev;
 214         struct radeon_device *rdev = dev->dev_private;
 215         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 216         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 217         uint32_t offset = dig->afmt->offset;
 218         uint8_t *frame = buffer + 3;
 219         uint8_t *header = buffer;
 220
 221         WREG32(AFMT_AVI_INFO0 + offset,
 222                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 223         WREG32(AFMT_AVI_INFO1 + offset,
 224                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 225         WREG32(AFMT_AVI_INFO2 + offset,
 226                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 227         WREG32(AFMT_AVI_INFO3 + offset,
 228                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 229 }
 230
 231 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 232 {
 233         struct drm_device *dev = encoder->dev;
 234         struct radeon_device *rdev = dev->dev_private;
 235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 236         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 237         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 238         u32 base_rate = 24000;
 239         u32 max_ratio = clock / base_rate;
 240         u32 dto_phase;
 241         u32 dto_modulo = clock;
 242         u32 wallclock_ratio;
 243         u32 dto_cntl;
 244
 245         if (!dig || !dig->afmt)
 246                 return;
 247
 248         if (ASIC_IS_DCE6(rdev)) {
 249                 dto_phase = 24 * 1000;
 250         } else {
 251                 if (max_ratio >= 8) {
 252                         dto_phase = 192 * 1000;
 253                         wallclock_ratio = 3;
 254                 } else if (max_ratio >= 4) {
 255                         dto_phase = 96 * 1000;
 256                         wallclock_ratio = 2;
 257                 } else if (max_ratio >= 2) {
 258                         dto_phase = 48 * 1000;
 259                         wallclock_ratio = 1;
 260                 } else {
 261                         dto_phase = 24 * 1000;
 262                         wallclock_ratio = 0;
 263                 }
 264                 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 265                 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 266                 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 267         }
 268
 269         /* XXX two dtos; generally use dto0 for hdmi */
 270         /* Express [24MHz / target pixel clock] as an exact rational
 271          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 272          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 273          */
 274         WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
 275         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 276         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 277 }
 278
 279
 280 /*
 281  * update the info frames with the data from the current display mode
 282  */
 283 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 284 {
 285         struct drm_device *dev = encoder->dev;
 286         struct radeon_device *rdev = dev->dev_private;
 287         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 288         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 289         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 290         struct hdmi_avi_infoframe frame;
 291         uint32_t offset;
 292         ssize_t err;
 293
 294         if (!dig || !dig->afmt)
 295                 return;
 296
 297         /* Silent, r600_hdmi_enable will raise WARN for us */
 298         if (!dig->afmt->enabled)
 299                 return;
 300         offset = dig->afmt->offset;
 301
 302         evergreen_audio_set_dto(encoder, mode->clock);
 303
 304         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 305                HDMI_NULL_SEND); /* send null packets when required */
 306
 307         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 308
 309         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 310                HDMI_NULL_SEND | /* send null packets when required */
 311                HDMI_GC_SEND | /* send general control packets */
 312                HDMI_GC_CONT); /* send general control packets every frame */
 313
 314         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
 315                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 316                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 317
 318         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
 319                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 320
 321         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
 322                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 323
 324         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 325
 326         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
 327                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
 328                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 329
 330         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 331                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 332
 333         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 334
 335         WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 336                HDMI_ACR_SOURCE | /* select SW CTS value */
 337                HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 338
 339         evergreen_hdmi_update_ACR(encoder, mode->clock);
 340
 341         WREG32(AFMT_60958_0 + offset,
 342                AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 343
 344         WREG32(AFMT_60958_1 + offset,
 345                AFMT_60958_CS_CHANNEL_NUMBER_R(2));
 346
 347         WREG32(AFMT_60958_2 + offset,
 348                AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
 349                AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
 350                AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
 351                AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
 352                AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
 353                AFMT_60958_CS_CHANNEL_NUMBER_7(8));
 354
 355         if (ASIC_IS_DCE6(rdev)) {
 356                 dce6_afmt_write_speaker_allocation(encoder);
 357         } else {
 358                 dce4_afmt_write_speaker_allocation(encoder);
 359         }
 360
 361         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
 362                AFMT_AUDIO_CHANNEL_ENABLE(0xff));
 363
 364         /* fglrx sets 0x40 in 0x5f80 here */
 365
 366         if (ASIC_IS_DCE6(rdev)) {
 367                 dce6_afmt_select_pin(encoder);
 368                 dce6_afmt_write_sad_regs(encoder);
 369                 dce6_afmt_write_latency_fields(encoder, mode);
 370         } else {
 371                 evergreen_hdmi_write_sad_regs(encoder);
 372                 dce4_afmt_write_latency_fields(encoder, mode);
 373         }
 374
 375         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 376         if (err < 0) {
 377                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 378                 return;
 379         }
 380
 381         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 382         if (err < 0) {
 383                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 384                 return;
 385         }
 386
 387         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 388
 389         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 390                   HDMI_AVI_INFO_SEND | /* enable AVI info frames */
 391                   HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
 392
 393         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
 394                  HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
 395                  ~HDMI_AVI_INFO_LINE_MASK);
 396
 397         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
 398                   AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
 399
 400         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 401         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 402         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
 403         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
 404         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
 405 }
 406
 407 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
 408 {
 409         struct drm_device *dev = encoder->dev;
 410         struct radeon_device *rdev = dev->dev_private;
 411         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 412         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 413
 414         if (!dig || !dig->afmt)
 415                 return;
 416
 417         /* Silent, r600_hdmi_enable will raise WARN for us */
 418         if (enable && dig->afmt->enabled)
 419                 return;
 420         if (!enable && !dig->afmt->enabled)
 421                 return;
 422
 423         if (enable) {
 424                 if (ASIC_IS_DCE6(rdev))
 425                         dig->afmt->pin = dce6_audio_get_pin(rdev);
 426                 else
 427                         dig->afmt->pin = r600_audio_get_pin(rdev);
 428         } else {
 429                 dig->afmt->pin = NULL;
 430         }
 431
 432         dig->afmt->enabled = enable;
 433
 434         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 435                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 436 }