drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/module.h>
  33 #include <drm/drmP.h>
  34 #include <drm/radeon_drm.h>
  35 #include "radeon.h"
  36 #include "radeon_asic.h"
  37 #include "radeon_mode.h"
  38 #include "r600d.h"
  39 #include "atom.h"
  40 #include "avivod.h"
  41
  42 #define PFP_UCODE_SIZE 576
  43 #define PM4_UCODE_SIZE 1792
  44 #define RLC_UCODE_SIZE 768
  45 #define R700_PFP_UCODE_SIZE 848
  46 #define R700_PM4_UCODE_SIZE 1360
  47 #define R700_RLC_UCODE_SIZE 1024
  48 #define EVERGREEN_PFP_UCODE_SIZE 1120
  49 #define EVERGREEN_PM4_UCODE_SIZE 1376
  50 #define EVERGREEN_RLC_UCODE_SIZE 768
  51 #define CAYMAN_RLC_UCODE_SIZE 1024
  52 #define ARUBA_RLC_UCODE_SIZE 1536
  53
  54 /* Firmware Names */
  55 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  56 MODULE_FIRMWARE("radeon/R600_me.bin");
  57 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV610_me.bin");
  59 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV630_me.bin");
  61 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV620_me.bin");
  63 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV635_me.bin");
  65 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RV670_me.bin");
  67 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RS780_me.bin");
  69 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV770_me.bin");
  71 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV730_me.bin");
  73 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  74 MODULE_FIRMWARE("radeon/RV710_me.bin");
  75 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  76 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  78 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  79 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  81 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  82 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  84 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  85 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  87 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  88 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  89 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  90 MODULE_FIRMWARE("radeon/PALM_me.bin");
  91 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  92 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  93 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  94 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  95 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  96
  97 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  98
  99 /* r600,rv610,rv630,rv620,rv635,rv670 */
 100 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 101 static void r600_gpu_init(struct radeon_device *rdev);
 102 void r600_fini(struct radeon_device *rdev);
 103 void r600_irq_disable(struct radeon_device *rdev);
 104 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 105
 106 /* get temperature in millidegrees */
 107 int rv6xx_get_temp(struct radeon_device *rdev)
 108 {
 109         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 110                 ASIC_T_SHIFT;
 111         int actual_temp = temp & 0xff;
 112
 113         if (temp & 0x100)
 114                 actual_temp -= 256;
 115
 116         return actual_temp * 1000;
 117 }
 118
 119 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 120 {
 121         int i;
 122
 123         rdev->pm.dynpm_can_upclock = true;
 124         rdev->pm.dynpm_can_downclock = true;
 125
 126         /* power state array is low to high, default is first */
 127         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 128                 int min_power_state_index = 0;
 129
 130                 if (rdev->pm.num_power_states > 2)
 131                         min_power_state_index = 1;
 132
 133                 switch (rdev->pm.dynpm_planned_action) {
 134                 case DYNPM_ACTION_MINIMUM:
 135                         rdev->pm.requested_power_state_index = min_power_state_index;
 136                         rdev->pm.requested_clock_mode_index = 0;
 137                         rdev->pm.dynpm_can_downclock = false;
 138                         break;
 139                 case DYNPM_ACTION_DOWNCLOCK:
 140                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 141                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 142                                 rdev->pm.dynpm_can_downclock = false;
 143                         } else {
 144                                 if (rdev->pm.active_crtc_count > 1) {
 145                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 146                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 147                                                         continue;
 148                                                 else if (i >= rdev->pm.current_power_state_index) {
 149                                                         rdev->pm.requested_power_state_index =
 150                                                                 rdev->pm.current_power_state_index;
 151                                                         break;
 152                                                 } else {
 153                                                         rdev->pm.requested_power_state_index = i;
 154                                                         break;
 155                                                 }
 156                                         }
 157                                 } else {
 158                                         if (rdev->pm.current_power_state_index == 0)
 159                                                 rdev->pm.requested_power_state_index =
 160                                                         rdev->pm.num_power_states - 1;
 161                                         else
 162                                                 rdev->pm.requested_power_state_index =
 163                                                         rdev->pm.current_power_state_index - 1;
 164                                 }
 165                         }
 166                         rdev->pm.requested_clock_mode_index = 0;
 167                         /* don't use the power state if crtcs are active and no display flag is set */
 168                         if ((rdev->pm.active_crtc_count > 0) &&
 169                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 170                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 171                              RADEON_PM_MODE_NO_DISPLAY)) {
 172                                 rdev->pm.requested_power_state_index++;
 173                         }
 174                         break;
 175                 case DYNPM_ACTION_UPCLOCK:
 176                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 177                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 178                                 rdev->pm.dynpm_can_upclock = false;
 179                         } else {
 180                                 if (rdev->pm.active_crtc_count > 1) {
 181                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 182                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 183                                                         continue;
 184                                                 else if (i <= rdev->pm.current_power_state_index) {
 185                                                         rdev->pm.requested_power_state_index =
 186                                                                 rdev->pm.current_power_state_index;
 187                                                         break;
 188                                                 } else {
 189                                                         rdev->pm.requested_power_state_index = i;
 190                                                         break;
 191                                                 }
 192                                         }
 193                                 } else
 194                                         rdev->pm.requested_power_state_index =
 195                                                 rdev->pm.current_power_state_index + 1;
 196                         }
 197                         rdev->pm.requested_clock_mode_index = 0;
 198                         break;
 199                 case DYNPM_ACTION_DEFAULT:
 200                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 201                         rdev->pm.requested_clock_mode_index = 0;
 202                         rdev->pm.dynpm_can_upclock = false;
 203                         break;
 204                 case DYNPM_ACTION_NONE:
 205                 default:
 206                         DRM_ERROR("Requested mode for not defined action\n");
 207                         return;
 208                 }
 209         } else {
 210                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 211                 /* for now just select the first power state and switch between clock modes */
 212                 /* power state array is low to high, default is first (0) */
 213                 if (rdev->pm.active_crtc_count > 1) {
 214                         rdev->pm.requested_power_state_index = -1;
 215                         /* start at 1 as we don't want the default mode */
 216                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 217                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 218                                         continue;
 219                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 220                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 221                                         rdev->pm.requested_power_state_index = i;
 222                                         break;
 223                                 }
 224                         }
 225                         /* if nothing selected, grab the default state. */
 226                         if (rdev->pm.requested_power_state_index == -1)
 227                                 rdev->pm.requested_power_state_index = 0;
 228                 } else
 229                         rdev->pm.requested_power_state_index = 1;
 230
 231                 switch (rdev->pm.dynpm_planned_action) {
 232                 case DYNPM_ACTION_MINIMUM:
 233                         rdev->pm.requested_clock_mode_index = 0;
 234                         rdev->pm.dynpm_can_downclock = false;
 235                         break;
 236                 case DYNPM_ACTION_DOWNCLOCK:
 237                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 238                                 if (rdev->pm.current_clock_mode_index == 0) {
 239                                         rdev->pm.requested_clock_mode_index = 0;
 240                                         rdev->pm.dynpm_can_downclock = false;
 241                                 } else
 242                                         rdev->pm.requested_clock_mode_index =
 243                                                 rdev->pm.current_clock_mode_index - 1;
 244                         } else {
 245                                 rdev->pm.requested_clock_mode_index = 0;
 246                                 rdev->pm.dynpm_can_downclock = false;
 247                         }
 248                         /* don't use the power state if crtcs are active and no display flag is set */
 249                         if ((rdev->pm.active_crtc_count > 0) &&
 250                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 251                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 252                              RADEON_PM_MODE_NO_DISPLAY)) {
 253                                 rdev->pm.requested_clock_mode_index++;
 254                         }
 255                         break;
 256                 case DYNPM_ACTION_UPCLOCK:
 257                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 258                                 if (rdev->pm.current_clock_mode_index ==
 259                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 260                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 261                                         rdev->pm.dynpm_can_upclock = false;
 262                                 } else
 263                                         rdev->pm.requested_clock_mode_index =
 264                                                 rdev->pm.current_clock_mode_index + 1;
 265                         } else {
 266                                 rdev->pm.requested_clock_mode_index =
 267                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 268                                 rdev->pm.dynpm_can_upclock = false;
 269                         }
 270                         break;
 271                 case DYNPM_ACTION_DEFAULT:
 272                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 273                         rdev->pm.requested_clock_mode_index = 0;
 274                         rdev->pm.dynpm_can_upclock = false;
 275                         break;
 276                 case DYNPM_ACTION_NONE:
 277                 default:
 278                         DRM_ERROR("Requested mode for not defined action\n");
 279                         return;
 280                 }
 281         }
 282
 283         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 284                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 285                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 286                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 287                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 288                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 289                   pcie_lanes);
 290 }
 291
 292 void rs780_pm_init_profile(struct radeon_device *rdev)
 293 {
 294         if (rdev->pm.num_power_states == 2) {
 295                 /* default */
 296                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 297                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 298                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 299                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 300                 /* low sh */
 301                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 302                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 304                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 305                 /* mid sh */
 306                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 309                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 310                 /* high sh */
 311                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 313                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 315                 /* low mh */
 316                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 317                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 320                 /* mid mh */
 321                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 322                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 325                 /* high mh */
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 327                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 328                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 330         } else if (rdev->pm.num_power_states == 3) {
 331                 /* default */
 332                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 333                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 334                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 336                 /* low sh */
 337                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 338                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 339                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 340                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 341                 /* mid sh */
 342                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 343                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 345                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 346                 /* high sh */
 347                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 349                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 350                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 351                 /* low mh */
 352                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 353                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 355                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 356                 /* mid mh */
 357                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 358                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 360                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 361                 /* high mh */
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 363                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 364                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 365                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 366         } else {
 367                 /* default */
 368                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 369                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 370                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 372                 /* low sh */
 373                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 374                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 375                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 377                 /* mid sh */
 378                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 379                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 381                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 382                 /* high sh */
 383                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 384                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 385                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 387                 /* low mh */
 388                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 389                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 391                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 392                 /* mid mh */
 393                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 394                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 395                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 396                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 397                 /* high mh */
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 399                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 400                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 402         }
 403 }
 404
 405 void r600_pm_init_profile(struct radeon_device *rdev)
 406 {
 407         int idx;
 408
 409         if (rdev->family == CHIP_R600) {
 410                 /* XXX */
 411                 /* default */
 412                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 413                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 414                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 415                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 416                 /* low sh */
 417                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 418                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 419                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 420                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 421                 /* mid sh */
 422                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 426                 /* high sh */
 427                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 431                 /* low mh */
 432                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 436                 /* mid mh */
 437                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 441                 /* high mh */
 442                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 445                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 446         } else {
 447                 if (rdev->pm.num_power_states < 4) {
 448                         /* default */
 449                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 450                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 451                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 452                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 453                         /* low sh */
 454                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 455                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 456                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 457                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 458                         /* mid sh */
 459                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 460                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 461                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 462                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 463                         /* high sh */
 464                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 467                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 468                         /* low mh */
 469                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 470                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 471                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 472                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 473                         /* low mh */
 474                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 475                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 476                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 477                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 478                         /* high mh */
 479                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 482                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 483                 } else {
 484                         /* default */
 485                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 486                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 487                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 488                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 489                         /* low sh */
 490                         if (rdev->flags & RADEON_IS_MOBILITY)
 491                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 492                         else
 493                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 494                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 495                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 496                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 497                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 498                         /* mid sh */
 499                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 500                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 501                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 502                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 503                         /* high sh */
 504                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 505                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 506                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 507                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 508                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 509                         /* low mh */
 510                         if (rdev->flags & RADEON_IS_MOBILITY)
 511                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 512                         else
 513                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 514                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 515                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 516                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 517                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 518                         /* mid mh */
 519                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 520                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 521                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 522                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 523                         /* high mh */
 524                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 525                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 526                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 527                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 529                 }
 530         }
 531 }
 532
 533 void r600_pm_misc(struct radeon_device *rdev)
 534 {
 535         int req_ps_idx = rdev->pm.requested_power_state_index;
 536         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 537         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 538         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 539
 540         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 541                 /* 0xff01 is a flag rather then an actual voltage */
 542                 if (voltage->voltage == 0xff01)
 543                         return;
 544                 if (voltage->voltage != rdev->pm.current_vddc) {
 545                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 546                         rdev->pm.current_vddc = voltage->voltage;
 547                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 548                 }
 549         }
 550 }
 551
 552 bool r600_gui_idle(struct radeon_device *rdev)
 553 {
 554         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 555                 return false;
 556         else
 557                 return true;
 558 }
 559
 560 /* hpd for digital panel detect/disconnect */
 561 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 562 {
 563         bool connected = false;
 564
 565         if (ASIC_IS_DCE3(rdev)) {
 566                 switch (hpd) {
 567                 case RADEON_HPD_1:
 568                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 569                                 connected = true;
 570                         break;
 571                 case RADEON_HPD_2:
 572                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 573                                 connected = true;
 574                         break;
 575                 case RADEON_HPD_3:
 576                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 577                                 connected = true;
 578                         break;
 579                 case RADEON_HPD_4:
 580                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 581                                 connected = true;
 582                         break;
 583                         /* DCE 3.2 */
 584                 case RADEON_HPD_5:
 585                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 586                                 connected = true;
 587                         break;
 588                 case RADEON_HPD_6:
 589                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 590                                 connected = true;
 591                         break;
 592                 default:
 593                         break;
 594                 }
 595         } else {
 596                 switch (hpd) {
 597                 case RADEON_HPD_1:
 598                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 599                                 connected = true;
 600                         break;
 601                 case RADEON_HPD_2:
 602                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 603                                 connected = true;
 604                         break;
 605                 case RADEON_HPD_3:
 606                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 607                                 connected = true;
 608                         break;
 609                 default:
 610                         break;
 611                 }
 612         }
 613         return connected;
 614 }
 615
 616 void r600_hpd_set_polarity(struct radeon_device *rdev,
 617                            enum radeon_hpd_id hpd)
 618 {
 619         u32 tmp;
 620         bool connected = r600_hpd_sense(rdev, hpd);
 621
 622         if (ASIC_IS_DCE3(rdev)) {
 623                 switch (hpd) {
 624                 case RADEON_HPD_1:
 625                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 626                         if (connected)
 627                                 tmp &= ~DC_HPDx_INT_POLARITY;
 628                         else
 629                                 tmp |= DC_HPDx_INT_POLARITY;
 630                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 631                         break;
 632                 case RADEON_HPD_2:
 633                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 634                         if (connected)
 635                                 tmp &= ~DC_HPDx_INT_POLARITY;
 636                         else
 637                                 tmp |= DC_HPDx_INT_POLARITY;
 638                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 639                         break;
 640                 case RADEON_HPD_3:
 641                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 642                         if (connected)
 643                                 tmp &= ~DC_HPDx_INT_POLARITY;
 644                         else
 645                                 tmp |= DC_HPDx_INT_POLARITY;
 646                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 647                         break;
 648                 case RADEON_HPD_4:
 649                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 650                         if (connected)
 651                                 tmp &= ~DC_HPDx_INT_POLARITY;
 652                         else
 653                                 tmp |= DC_HPDx_INT_POLARITY;
 654                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 655                         break;
 656                 case RADEON_HPD_5:
 657                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 658                         if (connected)
 659                                 tmp &= ~DC_HPDx_INT_POLARITY;
 660                         else
 661                                 tmp |= DC_HPDx_INT_POLARITY;
 662                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 663                         break;
 664                         /* DCE 3.2 */
 665                 case RADEON_HPD_6:
 666                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 667                         if (connected)
 668                                 tmp &= ~DC_HPDx_INT_POLARITY;
 669                         else
 670                                 tmp |= DC_HPDx_INT_POLARITY;
 671                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 672                         break;
 673                 default:
 674                         break;
 675                 }
 676         } else {
 677                 switch (hpd) {
 678                 case RADEON_HPD_1:
 679                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 680                         if (connected)
 681                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 682                         else
 683                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 684                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 685                         break;
 686                 case RADEON_HPD_2:
 687                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 688                         if (connected)
 689                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 690                         else
 691                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 692                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 693                         break;
 694                 case RADEON_HPD_3:
 695                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 696                         if (connected)
 697                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 698                         else
 699                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 700                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 701                         break;
 702                 default:
 703                         break;
 704                 }
 705         }
 706 }
 707
 708 void r600_hpd_init(struct radeon_device *rdev)
 709 {
 710         struct drm_device *dev = rdev->ddev;
 711         struct drm_connector *connector;
 712         unsigned enable = 0;
 713
 714         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 715                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 716
 717                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 718                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 719                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 720                          * aux dp channel on imac and help (but not completely fix)
 721                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 722                          */
 723                         continue;
 724                 }
 725                 if (ASIC_IS_DCE3(rdev)) {
 726                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 727                         if (ASIC_IS_DCE32(rdev))
 728                                 tmp |= DC_HPDx_EN;
 729
 730                         switch (radeon_connector->hpd.hpd) {
 731                         case RADEON_HPD_1:
 732                                 WREG32(DC_HPD1_CONTROL, tmp);
 733                                 break;
 734                         case RADEON_HPD_2:
 735                                 WREG32(DC_HPD2_CONTROL, tmp);
 736                                 break;
 737                         case RADEON_HPD_3:
 738                                 WREG32(DC_HPD3_CONTROL, tmp);
 739                                 break;
 740                         case RADEON_HPD_4:
 741                                 WREG32(DC_HPD4_CONTROL, tmp);
 742                                 break;
 743                                 /* DCE 3.2 */
 744                         case RADEON_HPD_5:
 745                                 WREG32(DC_HPD5_CONTROL, tmp);
 746                                 break;
 747                         case RADEON_HPD_6:
 748                                 WREG32(DC_HPD6_CONTROL, tmp);
 749                                 break;
 750                         default:
 751                                 break;
 752                         }
 753                 } else {
 754                         switch (radeon_connector->hpd.hpd) {
 755                         case RADEON_HPD_1:
 756                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 757                                 break;
 758                         case RADEON_HPD_2:
 759                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 760                                 break;
 761                         case RADEON_HPD_3:
 762                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 763                                 break;
 764                         default:
 765                                 break;
 766                         }
 767                 }
 768                 enable |= 1 << radeon_connector->hpd.hpd;
 769                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 770         }
 771         radeon_irq_kms_enable_hpd(rdev, enable);
 772 }
 773
 774 void r600_hpd_fini(struct radeon_device *rdev)
 775 {
 776         struct drm_device *dev = rdev->ddev;
 777         struct drm_connector *connector;
 778         unsigned disable = 0;
 779
 780         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 781                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 782                 if (ASIC_IS_DCE3(rdev)) {
 783                         switch (radeon_connector->hpd.hpd) {
 784                         case RADEON_HPD_1:
 785                                 WREG32(DC_HPD1_CONTROL, 0);
 786                                 break;
 787                         case RADEON_HPD_2:
 788                                 WREG32(DC_HPD2_CONTROL, 0);
 789                                 break;
 790                         case RADEON_HPD_3:
 791                                 WREG32(DC_HPD3_CONTROL, 0);
 792                                 break;
 793                         case RADEON_HPD_4:
 794                                 WREG32(DC_HPD4_CONTROL, 0);
 795                                 break;
 796                                 /* DCE 3.2 */
 797                         case RADEON_HPD_5:
 798                                 WREG32(DC_HPD5_CONTROL, 0);
 799                                 break;
 800                         case RADEON_HPD_6:
 801                                 WREG32(DC_HPD6_CONTROL, 0);
 802                                 break;
 803                         default:
 804                                 break;
 805                         }
 806                 } else {
 807                         switch (radeon_connector->hpd.hpd) {
 808                         case RADEON_HPD_1:
 809                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 810                                 break;
 811                         case RADEON_HPD_2:
 812                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 813                                 break;
 814                         case RADEON_HPD_3:
 815                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 816                                 break;
 817                         default:
 818                                 break;
 819                         }
 820                 }
 821                 disable |= 1 << radeon_connector->hpd.hpd;
 822         }
 823         radeon_irq_kms_disable_hpd(rdev, disable);
 824 }
 825
 826 /*
 827  * R600 PCIE GART
 828  */
 829 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 830 {
 831         unsigned i;
 832         u32 tmp;
 833
 834         /* flush hdp cache so updates hit vram */
 835         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 836             !(rdev->flags & RADEON_IS_AGP)) {
 837                 void __iomem *ptr = (void *)rdev->gart.ptr;
 838                 u32 tmp;
 839
 840                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 841                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 842                  * This seems to cause problems on some AGP cards. Just use the old
 843                  * method for them.
 844                  */
 845                 WREG32(HDP_DEBUG1, 0);
 846                 tmp = readl((void __iomem *)ptr);
 847         } else
 848                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 849
 850         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 851         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 852         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 853         for (i = 0; i < rdev->usec_timeout; i++) {
 854                 /* read MC_STATUS */
 855                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 856                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 857                 if (tmp == 2) {
 858                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 859                         return;
 860                 }
 861                 if (tmp) {
 862                         return;
 863                 }
 864                 udelay(1);
 865         }
 866 }
 867
 868 int r600_pcie_gart_init(struct radeon_device *rdev)
 869 {
 870         int r;
 871
 872         if (rdev->gart.robj) {
 873                 WARN(1, "R600 PCIE GART already initialized\n");
 874                 return 0;
 875         }
 876         /* Initialize common gart structure */
 877         r = radeon_gart_init(rdev);
 878         if (r)
 879                 return r;
 880         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 881         return radeon_gart_table_vram_alloc(rdev);
 882 }
 883
 884 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 885 {
 886         u32 tmp;
 887         int r, i;
 888
 889         if (rdev->gart.robj == NULL) {
 890                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 891                 return -EINVAL;
 892         }
 893         r = radeon_gart_table_vram_pin(rdev);
 894         if (r)
 895                 return r;
 896         radeon_gart_restore(rdev);
 897
 898         /* Setup L2 cache */
 899         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 900                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 901                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 902         WREG32(VM_L2_CNTL2, 0);
 903         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 904         /* Setup TLB control */
 905         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 906                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 907                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 908                 ENABLE_WAIT_L2_QUERY;
 909         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 910         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 911         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 912         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 913         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 914         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 915         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 916         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 917         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 918         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 919         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 920         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 921         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 922         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 923         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 924         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 925         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 926         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 927                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 928         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 929                         (u32)(rdev->dummy_page.addr >> 12));
 930         for (i = 1; i < 7; i++)
 931                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 932
 933         r600_pcie_gart_tlb_flush(rdev);
 934         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 935                  (unsigned)(rdev->mc.gtt_size >> 20),
 936                  (unsigned long long)rdev->gart.table_addr);
 937         rdev->gart.ready = true;
 938         return 0;
 939 }
 940
 941 static void r600_pcie_gart_disable(struct radeon_device *rdev)
 942 {
 943         u32 tmp;
 944         int i;
 945
 946         /* Disable all tables */
 947         for (i = 0; i < 7; i++)
 948                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 949
 950         /* Disable L2 cache */
 951         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 952                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 953         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 954         /* Setup L1 TLB control */
 955         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 956                 ENABLE_WAIT_L2_QUERY;
 957         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 958         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 961         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 971         radeon_gart_table_vram_unpin(rdev);
 972 }
 973
 974 static void r600_pcie_gart_fini(struct radeon_device *rdev)
 975 {
 976         radeon_gart_fini(rdev);
 977         r600_pcie_gart_disable(rdev);
 978         radeon_gart_table_vram_free(rdev);
 979 }
 980
 981 static void r600_agp_enable(struct radeon_device *rdev)
 982 {
 983         u32 tmp;
 984         int i;
 985
 986         /* Setup L2 cache */
 987         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 988                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 989                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 990         WREG32(VM_L2_CNTL2, 0);
 991         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 992         /* Setup TLB control */
 993         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 994                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 995                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 996                 ENABLE_WAIT_L2_QUERY;
 997         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 998         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 999         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1000         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1001         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1002         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1003         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1011         for (i = 0; i < 7; i++)
1012                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1013 }
1014
1015 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1016 {
1017         unsigned i;
1018         u32 tmp;
1019
1020         for (i = 0; i < rdev->usec_timeout; i++) {
1021                 /* read MC_STATUS */
1022                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1023                 if (!tmp)
1024                         return 0;
1025                 udelay(1);
1026         }
1027         return -1;
1028 }
1029
1030 static void r600_mc_program(struct radeon_device *rdev)
1031 {
1032         struct rv515_mc_save save;
1033         u32 tmp;
1034         int i, j;
1035
1036         /* Initialize HDP */
1037         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1038                 WREG32((0x2c14 + j), 0x00000000);
1039                 WREG32((0x2c18 + j), 0x00000000);
1040                 WREG32((0x2c1c + j), 0x00000000);
1041                 WREG32((0x2c20 + j), 0x00000000);
1042                 WREG32((0x2c24 + j), 0x00000000);
1043         }
1044         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1045
1046         rv515_mc_stop(rdev, &save);
1047         if (r600_mc_wait_for_idle(rdev)) {
1048                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1049         }
1050         /* Lockout access through VGA aperture (doesn't exist before R600) */
1051         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1052         /* Update configuration */
1053         if (rdev->flags & RADEON_IS_AGP) {
1054                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1055                         /* VRAM before AGP */
1056                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1057                                 rdev->mc.vram_start >> 12);
1058                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1059                                 rdev->mc.gtt_end >> 12);
1060                 } else {
1061                         /* VRAM after AGP */
1062                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1063                                 rdev->mc.gtt_start >> 12);
1064                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1065                                 rdev->mc.vram_end >> 12);
1066                 }
1067         } else {
1068                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1069                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1070         }
1071         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1072         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1073         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1074         WREG32(MC_VM_FB_LOCATION, tmp);
1075         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1076         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1077         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1078         if (rdev->flags & RADEON_IS_AGP) {
1079                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1080                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1081                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1082         } else {
1083                 WREG32(MC_VM_AGP_BASE, 0);
1084                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1085                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1086         }
1087         if (r600_mc_wait_for_idle(rdev)) {
1088                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1089         }
1090         rv515_mc_resume(rdev, &save);
1091         /* we need to own VRAM, so turn off the VGA renderer here
1092          * to stop it overwriting our objects */
1093         rv515_vga_render_disable(rdev);
1094 }
1095
1096 /**
1097  * r600_vram_gtt_location - try to find VRAM & GTT location
1098  * @rdev: radeon device structure holding all necessary informations
1099  * @mc: memory controller structure holding memory informations
1100  *
1101  * Function will place try to place VRAM at same place as in CPU (PCI)
1102  * address space as some GPU seems to have issue when we reprogram at
1103  * different address space.
1104  *
1105  * If there is not enough space to fit the unvisible VRAM after the
1106  * aperture then we limit the VRAM size to the aperture.
1107  *
1108  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1109  * them to be in one from GPU point of view so that we can program GPU to
1110  * catch access outside them (weird GPU policy see ??).
1111  *
1112  * This function will never fails, worst case are limiting VRAM or GTT.
1113  *
1114  * Note: GTT start, end, size should be initialized before calling this
1115  * function on AGP platform.
1116  */
1117 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1118 {
1119         u64 size_bf, size_af;
1120
1121         if (mc->mc_vram_size > 0xE0000000) {
1122                 /* leave room for at least 512M GTT */
1123                 dev_warn(rdev->dev, "limiting VRAM\n");
1124                 mc->real_vram_size = 0xE0000000;
1125                 mc->mc_vram_size = 0xE0000000;
1126         }
1127         if (rdev->flags & RADEON_IS_AGP) {
1128                 size_bf = mc->gtt_start;
1129                 size_af = 0xFFFFFFFF - mc->gtt_end;
1130                 if (size_bf > size_af) {
1131                         if (mc->mc_vram_size > size_bf) {
1132                                 dev_warn(rdev->dev, "limiting VRAM\n");
1133                                 mc->real_vram_size = size_bf;
1134                                 mc->mc_vram_size = size_bf;
1135                         }
1136                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1137                 } else {
1138                         if (mc->mc_vram_size > size_af) {
1139                                 dev_warn(rdev->dev, "limiting VRAM\n");
1140                                 mc->real_vram_size = size_af;
1141                                 mc->mc_vram_size = size_af;
1142                         }
1143                         mc->vram_start = mc->gtt_end + 1;
1144                 }
1145                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1146                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1147                                 mc->mc_vram_size >> 20, mc->vram_start,
1148                                 mc->vram_end, mc->real_vram_size >> 20);
1149         } else {
1150                 u64 base = 0;
1151                 if (rdev->flags & RADEON_IS_IGP) {
1152                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1153                         base <<= 24;
1154                 }
1155                 radeon_vram_location(rdev, &rdev->mc, base);
1156                 rdev->mc.gtt_base_align = 0;
1157                 radeon_gtt_location(rdev, mc);
1158         }
1159 }
1160
1161 static int r600_mc_init(struct radeon_device *rdev)
1162 {
1163         u32 tmp;
1164         int chansize, numchan;
1165
1166         /* Get VRAM informations */
1167         rdev->mc.vram_is_ddr = true;
1168         tmp = RREG32(RAMCFG);
1169         if (tmp & CHANSIZE_OVERRIDE) {
1170                 chansize = 16;
1171         } else if (tmp & CHANSIZE_MASK) {
1172                 chansize = 64;
1173         } else {
1174                 chansize = 32;
1175         }
1176         tmp = RREG32(CHMAP);
1177         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1178         case 0:
1179         default:
1180                 numchan = 1;
1181                 break;
1182         case 1:
1183                 numchan = 2;
1184                 break;
1185         case 2:
1186                 numchan = 4;
1187                 break;
1188         case 3:
1189                 numchan = 8;
1190                 break;
1191         }
1192         rdev->mc.vram_width = numchan * chansize;
1193         /* Could aper size report 0 ? */
1194         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1195         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1196         /* Setup GPU memory space */
1197         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1198         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1199         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1200         r600_vram_gtt_location(rdev, &rdev->mc);
1201
1202         if (rdev->flags & RADEON_IS_IGP) {
1203                 rs690_pm_info(rdev);
1204                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1205         }
1206         radeon_update_bandwidth_info(rdev);
1207         return 0;
1208 }
1209
1210 int r600_vram_scratch_init(struct radeon_device *rdev)
1211 {
1212         int r;
1213
1214         if (rdev->vram_scratch.robj == NULL) {
1215                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1216                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1217                                      NULL, &rdev->vram_scratch.robj);
1218                 if (r) {
1219                         return r;
1220                 }
1221         }
1222
1223         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1224         if (unlikely(r != 0))
1225                 return r;
1226         r = radeon_bo_pin(rdev->vram_scratch.robj,
1227                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1228         if (r) {
1229                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1230                 return r;
1231         }
1232         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1233                                 (void **)&rdev->vram_scratch.ptr);
1234         if (r)
1235                 radeon_bo_unpin(rdev->vram_scratch.robj);
1236         radeon_bo_unreserve(rdev->vram_scratch.robj);
1237
1238         return r;
1239 }
1240
1241 void r600_vram_scratch_fini(struct radeon_device *rdev)
1242 {
1243         int r;
1244
1245         if (rdev->vram_scratch.robj == NULL) {
1246                 return;
1247         }
1248         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1249         if (likely(r == 0)) {
1250                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1251                 radeon_bo_unpin(rdev->vram_scratch.robj);
1252                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1253         }
1254         radeon_bo_unref(&rdev->vram_scratch.robj);
1255 }
1256
1257 /* We doesn't check that the GPU really needs a reset we simply do the
1258  * reset, it's up to the caller to determine if the GPU needs one. We
1259  * might add an helper function to check that.
1260  */
1261 static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
1262 {
1263         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1264                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1265                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1266                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1267                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1268                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1269                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1270                                 S_008010_GUI_ACTIVE(1);
1271         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1272                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1273                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1274                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1275                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1276                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1277                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1278                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1279         u32 tmp;
1280
1281         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1282                 return;
1283
1284         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1285                 RREG32(R_008010_GRBM_STATUS));
1286         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1287                 RREG32(R_008014_GRBM_STATUS2));
1288         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1289                 RREG32(R_000E50_SRBM_STATUS));
1290         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1291                 RREG32(CP_STALLED_STAT1));
1292         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1293                 RREG32(CP_STALLED_STAT2));
1294         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1295                 RREG32(CP_BUSY_STAT));
1296         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1297                 RREG32(CP_STAT));
1298
1299         /* Disable CP parsing/prefetching */
1300         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1301
1302         /* Check if any of the rendering block is busy and reset it */
1303         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1304             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1305                 tmp = S_008020_SOFT_RESET_CR(1) |
1306                         S_008020_SOFT_RESET_DB(1) |
1307                         S_008020_SOFT_RESET_CB(1) |
1308                         S_008020_SOFT_RESET_PA(1) |
1309                         S_008020_SOFT_RESET_SC(1) |
1310                         S_008020_SOFT_RESET_SMX(1) |
1311                         S_008020_SOFT_RESET_SPI(1) |
1312                         S_008020_SOFT_RESET_SX(1) |
1313                         S_008020_SOFT_RESET_SH(1) |
1314                         S_008020_SOFT_RESET_TC(1) |
1315                         S_008020_SOFT_RESET_TA(1) |
1316                         S_008020_SOFT_RESET_VC(1) |
1317                         S_008020_SOFT_RESET_VGT(1);
1318                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1319                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1320                 RREG32(R_008020_GRBM_SOFT_RESET);
1321                 mdelay(15);
1322                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1323         }
1324         /* Reset CP (we always reset CP) */
1325         tmp = S_008020_SOFT_RESET_CP(1);
1326         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1327         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1328         RREG32(R_008020_GRBM_SOFT_RESET);
1329         mdelay(15);
1330         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1331
1332         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1333                 RREG32(R_008010_GRBM_STATUS));
1334         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1335                 RREG32(R_008014_GRBM_STATUS2));
1336         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1337                 RREG32(R_000E50_SRBM_STATUS));
1338         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1339                 RREG32(CP_STALLED_STAT1));
1340         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1341                 RREG32(CP_STALLED_STAT2));
1342         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1343                 RREG32(CP_BUSY_STAT));
1344         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1345                 RREG32(CP_STAT));
1346
1347 }
1348
1349 static void r600_gpu_soft_reset_dma(struct radeon_device *rdev)
1350 {
1351         u32 tmp;
1352
1353         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1354                 return;
1355
1356         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1357                 RREG32(DMA_STATUS_REG));
1358
1359         /* Disable DMA */
1360         tmp = RREG32(DMA_RB_CNTL);
1361         tmp &= ~DMA_RB_ENABLE;
1362         WREG32(DMA_RB_CNTL, tmp);
1363
1364         /* Reset dma */
1365         if (rdev->family >= CHIP_RV770)
1366                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
1367         else
1368                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1369         RREG32(SRBM_SOFT_RESET);
1370         udelay(50);
1371         WREG32(SRBM_SOFT_RESET, 0);
1372
1373         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1374                 RREG32(DMA_STATUS_REG));
1375 }
1376
1377 static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1378 {
1379         struct rv515_mc_save save;
1380
1381         if (reset_mask == 0)
1382                 return 0;
1383
1384         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1385
1386         rv515_mc_stop(rdev, &save);
1387         if (r600_mc_wait_for_idle(rdev)) {
1388                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1389         }
1390
1391         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
1392                 r600_gpu_soft_reset_gfx(rdev);
1393
1394         if (reset_mask & RADEON_RESET_DMA)
1395                 r600_gpu_soft_reset_dma(rdev);
1396
1397         /* Wait a little for things to settle down */
1398         mdelay(1);
1399
1400         rv515_mc_resume(rdev, &save);
1401         return 0;
1402 }
1403
1404 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1405 {
1406         u32 srbm_status;
1407         u32 grbm_status;
1408         u32 grbm_status2;
1409
1410         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1411         grbm_status = RREG32(R_008010_GRBM_STATUS);
1412         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1413         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1414                 radeon_ring_lockup_update(ring);
1415                 return false;
1416         }
1417         /* force CP activities */
1418         radeon_ring_force_activity(rdev, ring);
1419         return radeon_ring_test_lockup(rdev, ring);
1420 }
1421
1422 /**
1423  * r600_dma_is_lockup - Check if the DMA engine is locked up
1424  *
1425  * @rdev: radeon_device pointer
1426  * @ring: radeon_ring structure holding ring information
1427  *
1428  * Check if the async DMA engine is locked up (r6xx-evergreen).
1429  * Returns true if the engine appears to be locked up, false if not.
1430  */
1431 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1432 {
1433         u32 dma_status_reg;
1434
1435         dma_status_reg = RREG32(DMA_STATUS_REG);
1436         if (dma_status_reg & DMA_IDLE) {
1437                 radeon_ring_lockup_update(ring);
1438                 return false;
1439         }
1440         /* force ring activities */
1441         radeon_ring_force_activity(rdev, ring);
1442         return radeon_ring_test_lockup(rdev, ring);
1443 }
1444
1445 int r600_asic_reset(struct radeon_device *rdev)
1446 {
1447         return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1448                                           RADEON_RESET_COMPUTE |
1449                                           RADEON_RESET_DMA));
1450 }
1451
1452 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1453                               u32 tiling_pipe_num,
1454                               u32 max_rb_num,
1455                               u32 total_max_rb_num,
1456                               u32 disabled_rb_mask)
1457 {
1458         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1459         u32 pipe_rb_ratio, pipe_rb_remain;
1460         u32 data = 0, mask = 1 << (max_rb_num - 1);
1461         unsigned i, j;
1462
1463         /* mask out the RBs that don't exist on that asic */
1464         disabled_rb_mask |= (0xff << max_rb_num) & 0xff;
1465
1466         rendering_pipe_num = 1 << tiling_pipe_num;
1467         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1468         BUG_ON(rendering_pipe_num < req_rb_num);
1469
1470         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1471         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1472
1473         if (rdev->family <= CHIP_RV740) {
1474                 /* r6xx/r7xx */
1475                 rb_num_width = 2;
1476         } else {
1477                 /* eg+ */
1478                 rb_num_width = 4;
1479         }
1480
1481         for (i = 0; i < max_rb_num; i++) {
1482                 if (!(mask & disabled_rb_mask)) {
1483                         for (j = 0; j < pipe_rb_ratio; j++) {
1484                                 data <<= rb_num_width;
1485                                 data |= max_rb_num - i - 1;
1486                         }
1487                         if (pipe_rb_remain) {
1488                                 data <<= rb_num_width;
1489                                 data |= max_rb_num - i - 1;
1490                                 pipe_rb_remain--;
1491                         }
1492                 }
1493                 mask >>= 1;
1494         }
1495
1496         return data;
1497 }
1498
1499 int r600_count_pipe_bits(uint32_t val)
1500 {
1501         return hweight32(val);
1502 }
1503
1504 static void r600_gpu_init(struct radeon_device *rdev)
1505 {
1506         u32 tiling_config;
1507         u32 ramcfg;
1508         u32 cc_rb_backend_disable;
1509         u32 cc_gc_shader_pipe_config;
1510         u32 tmp;
1511         int i, j;
1512         u32 sq_config;
1513         u32 sq_gpr_resource_mgmt_1 = 0;
1514         u32 sq_gpr_resource_mgmt_2 = 0;
1515         u32 sq_thread_resource_mgmt = 0;
1516         u32 sq_stack_resource_mgmt_1 = 0;
1517         u32 sq_stack_resource_mgmt_2 = 0;
1518         u32 disabled_rb_mask;
1519
1520         rdev->config.r600.tiling_group_size = 256;
1521         switch (rdev->family) {
1522         case CHIP_R600:
1523                 rdev->config.r600.max_pipes = 4;
1524                 rdev->config.r600.max_tile_pipes = 8;
1525                 rdev->config.r600.max_simds = 4;
1526                 rdev->config.r600.max_backends = 4;
1527                 rdev->config.r600.max_gprs = 256;
1528                 rdev->config.r600.max_threads = 192;
1529                 rdev->config.r600.max_stack_entries = 256;
1530                 rdev->config.r600.max_hw_contexts = 8;
1531                 rdev->config.r600.max_gs_threads = 16;
1532                 rdev->config.r600.sx_max_export_size = 128;
1533                 rdev->config.r600.sx_max_export_pos_size = 16;
1534                 rdev->config.r600.sx_max_export_smx_size = 128;
1535                 rdev->config.r600.sq_num_cf_insts = 2;
1536                 break;
1537         case CHIP_RV630:
1538         case CHIP_RV635:
1539                 rdev->config.r600.max_pipes = 2;
1540                 rdev->config.r600.max_tile_pipes = 2;
1541                 rdev->config.r600.max_simds = 3;
1542                 rdev->config.r600.max_backends = 1;
1543                 rdev->config.r600.max_gprs = 128;
1544                 rdev->config.r600.max_threads = 192;
1545                 rdev->config.r600.max_stack_entries = 128;
1546                 rdev->config.r600.max_hw_contexts = 8;
1547                 rdev->config.r600.max_gs_threads = 4;
1548                 rdev->config.r600.sx_max_export_size = 128;
1549                 rdev->config.r600.sx_max_export_pos_size = 16;
1550                 rdev->config.r600.sx_max_export_smx_size = 128;
1551                 rdev->config.r600.sq_num_cf_insts = 2;
1552                 break;
1553         case CHIP_RV610:
1554         case CHIP_RV620:
1555         case CHIP_RS780:
1556         case CHIP_RS880:
1557                 rdev->config.r600.max_pipes = 1;
1558                 rdev->config.r600.max_tile_pipes = 1;
1559                 rdev->config.r600.max_simds = 2;
1560                 rdev->config.r600.max_backends = 1;
1561                 rdev->config.r600.max_gprs = 128;
1562                 rdev->config.r600.max_threads = 192;
1563                 rdev->config.r600.max_stack_entries = 128;
1564                 rdev->config.r600.max_hw_contexts = 4;
1565                 rdev->config.r600.max_gs_threads = 4;
1566                 rdev->config.r600.sx_max_export_size = 128;
1567                 rdev->config.r600.sx_max_export_pos_size = 16;
1568                 rdev->config.r600.sx_max_export_smx_size = 128;
1569                 rdev->config.r600.sq_num_cf_insts = 1;
1570                 break;
1571         case CHIP_RV670:
1572                 rdev->config.r600.max_pipes = 4;
1573                 rdev->config.r600.max_tile_pipes = 4;
1574                 rdev->config.r600.max_simds = 4;
1575                 rdev->config.r600.max_backends = 4;
1576                 rdev->config.r600.max_gprs = 192;
1577                 rdev->config.r600.max_threads = 192;
1578                 rdev->config.r600.max_stack_entries = 256;
1579                 rdev->config.r600.max_hw_contexts = 8;
1580                 rdev->config.r600.max_gs_threads = 16;
1581                 rdev->config.r600.sx_max_export_size = 128;
1582                 rdev->config.r600.sx_max_export_pos_size = 16;
1583                 rdev->config.r600.sx_max_export_smx_size = 128;
1584                 rdev->config.r600.sq_num_cf_insts = 2;
1585                 break;
1586         default:
1587                 break;
1588         }
1589
1590         /* Initialize HDP */
1591         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1592                 WREG32((0x2c14 + j), 0x00000000);
1593                 WREG32((0x2c18 + j), 0x00000000);
1594                 WREG32((0x2c1c + j), 0x00000000);
1595                 WREG32((0x2c20 + j), 0x00000000);
1596                 WREG32((0x2c24 + j), 0x00000000);
1597         }
1598
1599         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1600
1601         /* Setup tiling */
1602         tiling_config = 0;
1603         ramcfg = RREG32(RAMCFG);
1604         switch (rdev->config.r600.max_tile_pipes) {
1605         case 1:
1606                 tiling_config |= PIPE_TILING(0);
1607                 break;
1608         case 2:
1609                 tiling_config |= PIPE_TILING(1);
1610                 break;
1611         case 4:
1612                 tiling_config |= PIPE_TILING(2);
1613                 break;
1614         case 8:
1615                 tiling_config |= PIPE_TILING(3);
1616                 break;
1617         default:
1618                 break;
1619         }
1620         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1621         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1622         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1623         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1624
1625         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1626         if (tmp > 3) {
1627                 tiling_config |= ROW_TILING(3);
1628                 tiling_config |= SAMPLE_SPLIT(3);
1629         } else {
1630                 tiling_config |= ROW_TILING(tmp);
1631                 tiling_config |= SAMPLE_SPLIT(tmp);
1632         }
1633         tiling_config |= BANK_SWAPS(1);
1634
1635         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1636         tmp = R6XX_MAX_BACKENDS -
1637                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1638         if (tmp < rdev->config.r600.max_backends) {
1639                 rdev->config.r600.max_backends = tmp;
1640         }
1641
1642         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1643         tmp = R6XX_MAX_PIPES -
1644                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1645         if (tmp < rdev->config.r600.max_pipes) {
1646                 rdev->config.r600.max_pipes = tmp;
1647         }
1648         tmp = R6XX_MAX_SIMDS -
1649                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1650         if (tmp < rdev->config.r600.max_simds) {
1651                 rdev->config.r600.max_simds = tmp;
1652         }
1653
1654         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1655         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1656         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1657                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1658         tiling_config |= tmp << 16;
1659         rdev->config.r600.backend_map = tmp;
1660
1661         rdev->config.r600.tile_config = tiling_config;
1662         WREG32(GB_TILING_CONFIG, tiling_config);
1663         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1664         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1665         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1666
1667         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1668         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1669         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1670
1671         /* Setup some CP states */
1672         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1673         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1674
1675         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1676                              SYNC_WALKER | SYNC_ALIGNER));
1677         /* Setup various GPU states */
1678         if (rdev->family == CHIP_RV670)
1679                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1680
1681         tmp = RREG32(SX_DEBUG_1);
1682         tmp |= SMX_EVENT_RELEASE;
1683         if ((rdev->family > CHIP_R600))
1684                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1685         WREG32(SX_DEBUG_1, tmp);
1686
1687         if (((rdev->family) == CHIP_R600) ||
1688             ((rdev->family) == CHIP_RV630) ||
1689             ((rdev->family) == CHIP_RV610) ||
1690             ((rdev->family) == CHIP_RV620) ||
1691             ((rdev->family) == CHIP_RS780) ||
1692             ((rdev->family) == CHIP_RS880)) {
1693                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1694         } else {
1695                 WREG32(DB_DEBUG, 0);
1696         }
1697         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1698                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1699
1700         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1701         WREG32(VGT_NUM_INSTANCES, 0);
1702
1703         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1704         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1705
1706         tmp = RREG32(SQ_MS_FIFO_SIZES);
1707         if (((rdev->family) == CHIP_RV610) ||
1708             ((rdev->family) == CHIP_RV620) ||
1709             ((rdev->family) == CHIP_RS780) ||
1710             ((rdev->family) == CHIP_RS880)) {
1711                 tmp = (CACHE_FIFO_SIZE(0xa) |
1712                        FETCH_FIFO_HIWATER(0xa) |
1713                        DONE_FIFO_HIWATER(0xe0) |
1714                        ALU_UPDATE_FIFO_HIWATER(0x8));
1715         } else if (((rdev->family) == CHIP_R600) ||
1716                    ((rdev->family) == CHIP_RV630)) {
1717                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1718                 tmp |= DONE_FIFO_HIWATER(0x4);
1719         }
1720         WREG32(SQ_MS_FIFO_SIZES, tmp);
1721
1722         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1723          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1724          */
1725         sq_config = RREG32(SQ_CONFIG);
1726         sq_config &= ~(PS_PRIO(3) |
1727                        VS_PRIO(3) |
1728                        GS_PRIO(3) |
1729                        ES_PRIO(3));
1730         sq_config |= (DX9_CONSTS |
1731                       VC_ENABLE |
1732                       PS_PRIO(0) |
1733                       VS_PRIO(1) |
1734                       GS_PRIO(2) |
1735                       ES_PRIO(3));
1736
1737         if ((rdev->family) == CHIP_R600) {
1738                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1739                                           NUM_VS_GPRS(124) |
1740                                           NUM_CLAUSE_TEMP_GPRS(4));
1741                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1742                                           NUM_ES_GPRS(0));
1743                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1744                                            NUM_VS_THREADS(48) |
1745                                            NUM_GS_THREADS(4) |
1746                                            NUM_ES_THREADS(4));
1747                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1748                                             NUM_VS_STACK_ENTRIES(128));
1749                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1750                                             NUM_ES_STACK_ENTRIES(0));
1751         } else if (((rdev->family) == CHIP_RV610) ||
1752                    ((rdev->family) == CHIP_RV620) ||
1753                    ((rdev->family) == CHIP_RS780) ||
1754                    ((rdev->family) == CHIP_RS880)) {
1755                 /* no vertex cache */
1756                 sq_config &= ~VC_ENABLE;
1757
1758                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1759                                           NUM_VS_GPRS(44) |
1760                                           NUM_CLAUSE_TEMP_GPRS(2));
1761                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1762                                           NUM_ES_GPRS(17));
1763                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1764                                            NUM_VS_THREADS(78) |
1765                                            NUM_GS_THREADS(4) |
1766                                            NUM_ES_THREADS(31));
1767                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1768                                             NUM_VS_STACK_ENTRIES(40));
1769                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1770                                             NUM_ES_STACK_ENTRIES(16));
1771         } else if (((rdev->family) == CHIP_RV630) ||
1772                    ((rdev->family) == CHIP_RV635)) {
1773                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1774                                           NUM_VS_GPRS(44) |
1775                                           NUM_CLAUSE_TEMP_GPRS(2));
1776                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1777                                           NUM_ES_GPRS(18));
1778                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1779                                            NUM_VS_THREADS(78) |
1780                                            NUM_GS_THREADS(4) |
1781                                            NUM_ES_THREADS(31));
1782                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1783                                             NUM_VS_STACK_ENTRIES(40));
1784                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1785                                             NUM_ES_STACK_ENTRIES(16));
1786         } else if ((rdev->family) == CHIP_RV670) {
1787                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1788                                           NUM_VS_GPRS(44) |
1789                                           NUM_CLAUSE_TEMP_GPRS(2));
1790                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1791                                           NUM_ES_GPRS(17));
1792                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1793                                            NUM_VS_THREADS(78) |
1794                                            NUM_GS_THREADS(4) |
1795                                            NUM_ES_THREADS(31));
1796                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1797                                             NUM_VS_STACK_ENTRIES(64));
1798                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1799                                             NUM_ES_STACK_ENTRIES(64));
1800         }
1801
1802         WREG32(SQ_CONFIG, sq_config);
1803         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1804         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1805         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1806         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1807         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1808
1809         if (((rdev->family) == CHIP_RV610) ||
1810             ((rdev->family) == CHIP_RV620) ||
1811             ((rdev->family) == CHIP_RS780) ||
1812             ((rdev->family) == CHIP_RS880)) {
1813                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1814         } else {
1815                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1816         }
1817
1818         /* More default values. 2D/3D driver should adjust as needed */
1819         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1820                                          S1_X(0x4) | S1_Y(0xc)));
1821         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1822                                          S1_X(0x2) | S1_Y(0x2) |
1823                                          S2_X(0xa) | S2_Y(0x6) |
1824                                          S3_X(0x6) | S3_Y(0xa)));
1825         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1826                                              S1_X(0x4) | S1_Y(0xc) |
1827                                              S2_X(0x1) | S2_Y(0x6) |
1828                                              S3_X(0xa) | S3_Y(0xe)));
1829         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1830                                              S5_X(0x0) | S5_Y(0x0) |
1831                                              S6_X(0xb) | S6_Y(0x4) |
1832                                              S7_X(0x7) | S7_Y(0x8)));
1833
1834         WREG32(VGT_STRMOUT_EN, 0);
1835         tmp = rdev->config.r600.max_pipes * 16;
1836         switch (rdev->family) {
1837         case CHIP_RV610:
1838         case CHIP_RV620:
1839         case CHIP_RS780:
1840         case CHIP_RS880:
1841                 tmp += 32;
1842                 break;
1843         case CHIP_RV670:
1844                 tmp += 128;
1845                 break;
1846         default:
1847                 break;
1848         }
1849         if (tmp > 256) {
1850                 tmp = 256;
1851         }
1852         WREG32(VGT_ES_PER_GS, 128);
1853         WREG32(VGT_GS_PER_ES, tmp);
1854         WREG32(VGT_GS_PER_VS, 2);
1855         WREG32(VGT_GS_VERTEX_REUSE, 16);
1856
1857         /* more default values. 2D/3D driver should adjust as needed */
1858         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1859         WREG32(VGT_STRMOUT_EN, 0);
1860         WREG32(SX_MISC, 0);
1861         WREG32(PA_SC_MODE_CNTL, 0);
1862         WREG32(PA_SC_AA_CONFIG, 0);
1863         WREG32(PA_SC_LINE_STIPPLE, 0);
1864         WREG32(SPI_INPUT_Z, 0);
1865         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1866         WREG32(CB_COLOR7_FRAG, 0);
1867
1868         /* Clear render buffer base addresses */
1869         WREG32(CB_COLOR0_BASE, 0);
1870         WREG32(CB_COLOR1_BASE, 0);
1871         WREG32(CB_COLOR2_BASE, 0);
1872         WREG32(CB_COLOR3_BASE, 0);
1873         WREG32(CB_COLOR4_BASE, 0);
1874         WREG32(CB_COLOR5_BASE, 0);
1875         WREG32(CB_COLOR6_BASE, 0);
1876         WREG32(CB_COLOR7_BASE, 0);
1877         WREG32(CB_COLOR7_FRAG, 0);
1878
1879         switch (rdev->family) {
1880         case CHIP_RV610:
1881         case CHIP_RV620:
1882         case CHIP_RS780:
1883         case CHIP_RS880:
1884                 tmp = TC_L2_SIZE(8);
1885                 break;
1886         case CHIP_RV630:
1887         case CHIP_RV635:
1888                 tmp = TC_L2_SIZE(4);
1889                 break;
1890         case CHIP_R600:
1891                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1892                 break;
1893         default:
1894                 tmp = TC_L2_SIZE(0);
1895                 break;
1896         }
1897         WREG32(TC_CNTL, tmp);
1898
1899         tmp = RREG32(HDP_HOST_PATH_CNTL);
1900         WREG32(HDP_HOST_PATH_CNTL, tmp);
1901
1902         tmp = RREG32(ARB_POP);
1903         tmp |= ENABLE_TC128;
1904         WREG32(ARB_POP, tmp);
1905
1906         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1907         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1908                                NUM_CLIP_SEQ(3)));
1909         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1910         WREG32(VC_ENHANCE, 0);
1911 }
1912
1913
1914 /*
1915  * Indirect registers accessor
1916  */
1917 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1918 {
1919         u32 r;
1920
1921         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1922         (void)RREG32(PCIE_PORT_INDEX);
1923         r = RREG32(PCIE_PORT_DATA);
1924         return r;
1925 }
1926
1927 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1928 {
1929         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1930         (void)RREG32(PCIE_PORT_INDEX);
1931         WREG32(PCIE_PORT_DATA, (v));
1932         (void)RREG32(PCIE_PORT_DATA);
1933 }
1934
1935 /*
1936  * CP & Ring
1937  */
1938 void r600_cp_stop(struct radeon_device *rdev)
1939 {
1940         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1941         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1942         WREG32(SCRATCH_UMSK, 0);
1943         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1944 }
1945
1946 int r600_init_microcode(struct radeon_device *rdev)
1947 {
1948         struct platform_device *pdev;
1949         const char *chip_name;
1950         const char *rlc_chip_name;
1951         size_t pfp_req_size, me_req_size, rlc_req_size;
1952         char fw_name[30];
1953         int err;
1954
1955         DRM_DEBUG("\n");
1956
1957         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1958         err = IS_ERR(pdev);
1959         if (err) {
1960                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1961                 return -EINVAL;
1962         }
1963
1964         switch (rdev->family) {
1965         case CHIP_R600:
1966                 chip_name = "R600";
1967                 rlc_chip_name = "R600";
1968                 break;
1969         case CHIP_RV610:
1970                 chip_name = "RV610";
1971                 rlc_chip_name = "R600";
1972                 break;
1973         case CHIP_RV630:
1974                 chip_name = "RV630";
1975                 rlc_chip_name = "R600";
1976                 break;
1977         case CHIP_RV620:
1978                 chip_name = "RV620";
1979                 rlc_chip_name = "R600";
1980                 break;
1981         case CHIP_RV635:
1982                 chip_name = "RV635";
1983                 rlc_chip_name = "R600";
1984                 break;
1985         case CHIP_RV670:
1986                 chip_name = "RV670";
1987                 rlc_chip_name = "R600";
1988                 break;
1989         case CHIP_RS780:
1990         case CHIP_RS880:
1991                 chip_name = "RS780";
1992                 rlc_chip_name = "R600";
1993                 break;
1994         case CHIP_RV770:
1995                 chip_name = "RV770";
1996                 rlc_chip_name = "R700";
1997                 break;
1998         case CHIP_RV730:
1999         case CHIP_RV740:
2000                 chip_name = "RV730";
2001                 rlc_chip_name = "R700";
2002                 break;
2003         case CHIP_RV710:
2004                 chip_name = "RV710";
2005                 rlc_chip_name = "R700";
2006                 break;
2007         case CHIP_CEDAR:
2008                 chip_name = "CEDAR";
2009                 rlc_chip_name = "CEDAR";
2010                 break;
2011         case CHIP_REDWOOD:
2012                 chip_name = "REDWOOD";
2013                 rlc_chip_name = "REDWOOD";
2014                 break;
2015         case CHIP_JUNIPER:
2016                 chip_name = "JUNIPER";
2017                 rlc_chip_name = "JUNIPER";
2018                 break;
2019         case CHIP_CYPRESS:
2020         case CHIP_HEMLOCK:
2021                 chip_name = "CYPRESS";
2022                 rlc_chip_name = "CYPRESS";
2023                 break;
2024         case CHIP_PALM:
2025                 chip_name = "PALM";
2026                 rlc_chip_name = "SUMO";
2027                 break;
2028         case CHIP_SUMO:
2029                 chip_name = "SUMO";
2030                 rlc_chip_name = "SUMO";
2031                 break;
2032         case CHIP_SUMO2:
2033                 chip_name = "SUMO2";
2034                 rlc_chip_name = "SUMO";
2035                 break;
2036         default: BUG();
2037         }
2038
2039         if (rdev->family >= CHIP_CEDAR) {
2040                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2041                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2042                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2043         } else if (rdev->family >= CHIP_RV770) {
2044                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2045                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2046                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2047         } else {
2048                 pfp_req_size = PFP_UCODE_SIZE * 4;
2049                 me_req_size = PM4_UCODE_SIZE * 12;
2050                 rlc_req_size = RLC_UCODE_SIZE * 4;
2051         }
2052
2053         DRM_INFO("Loading %s Microcode\n", chip_name);
2054
2055         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2056         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2057         if (err)
2058                 goto out;
2059         if (rdev->pfp_fw->size != pfp_req_size) {
2060                 printk(KERN_ERR
2061                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2062                        rdev->pfp_fw->size, fw_name);
2063                 err = -EINVAL;
2064                 goto out;
2065         }
2066
2067         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2068         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2069         if (err)
2070                 goto out;
2071         if (rdev->me_fw->size != me_req_size) {
2072                 printk(KERN_ERR
2073                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2074                        rdev->me_fw->size, fw_name);
2075                 err = -EINVAL;
2076         }
2077
2078         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2079         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2080         if (err)
2081                 goto out;
2082         if (rdev->rlc_fw->size != rlc_req_size) {
2083                 printk(KERN_ERR
2084                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2085                        rdev->rlc_fw->size, fw_name);
2086                 err = -EINVAL;
2087         }
2088
2089 out:
2090         platform_device_unregister(pdev);
2091
2092         if (err) {
2093                 if (err != -EINVAL)
2094                         printk(KERN_ERR
2095                                "r600_cp: Failed to load firmware \"%s\"\n",
2096                                fw_name);
2097                 release_firmware(rdev->pfp_fw);
2098                 rdev->pfp_fw = NULL;
2099                 release_firmware(rdev->me_fw);
2100                 rdev->me_fw = NULL;
2101                 release_firmware(rdev->rlc_fw);
2102                 rdev->rlc_fw = NULL;
2103         }
2104         return err;
2105 }
2106
2107 static int r600_cp_load_microcode(struct radeon_device *rdev)
2108 {
2109         const __be32 *fw_data;
2110         int i;
2111
2112         if (!rdev->me_fw || !rdev->pfp_fw)
2113                 return -EINVAL;
2114
2115         r600_cp_stop(rdev);
2116
2117         WREG32(CP_RB_CNTL,
2118 #ifdef __BIG_ENDIAN
2119                BUF_SWAP_32BIT |
2120 #endif
2121                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2122
2123         /* Reset cp */
2124         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2125         RREG32(GRBM_SOFT_RESET);
2126         mdelay(15);
2127         WREG32(GRBM_SOFT_RESET, 0);
2128
2129         WREG32(CP_ME_RAM_WADDR, 0);
2130
2131         fw_data = (const __be32 *)rdev->me_fw->data;
2132         WREG32(CP_ME_RAM_WADDR, 0);
2133         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2134                 WREG32(CP_ME_RAM_DATA,
2135                        be32_to_cpup(fw_data++));
2136
2137         fw_data = (const __be32 *)rdev->pfp_fw->data;
2138         WREG32(CP_PFP_UCODE_ADDR, 0);
2139         for (i = 0; i < PFP_UCODE_SIZE; i++)
2140                 WREG32(CP_PFP_UCODE_DATA,
2141                        be32_to_cpup(fw_data++));
2142
2143         WREG32(CP_PFP_UCODE_ADDR, 0);
2144         WREG32(CP_ME_RAM_WADDR, 0);
2145         WREG32(CP_ME_RAM_RADDR, 0);
2146         return 0;
2147 }
2148
2149 int r600_cp_start(struct radeon_device *rdev)
2150 {
2151         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2152         int r;
2153         uint32_t cp_me;
2154
2155         r = radeon_ring_lock(rdev, ring, 7);
2156         if (r) {
2157                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2158                 return r;
2159         }
2160         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2161         radeon_ring_write(ring, 0x1);
2162         if (rdev->family >= CHIP_RV770) {
2163                 radeon_ring_write(ring, 0x0);
2164                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2165         } else {
2166                 radeon_ring_write(ring, 0x3);
2167                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2168         }
2169         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2170         radeon_ring_write(ring, 0);
2171         radeon_ring_write(ring, 0);
2172         radeon_ring_unlock_commit(rdev, ring);
2173
2174         cp_me = 0xff;
2175         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2176         return 0;
2177 }
2178
2179 int r600_cp_resume(struct radeon_device *rdev)
2180 {
2181         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2182         u32 tmp;
2183         u32 rb_bufsz;
2184         int r;
2185
2186         /* Reset cp */
2187         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2188         RREG32(GRBM_SOFT_RESET);
2189         mdelay(15);
2190         WREG32(GRBM_SOFT_RESET, 0);
2191
2192         /* Set ring buffer size */
2193         rb_bufsz = drm_order(ring->ring_size / 8);
2194         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2195 #ifdef __BIG_ENDIAN
2196         tmp |= BUF_SWAP_32BIT;
2197 #endif
2198         WREG32(CP_RB_CNTL, tmp);
2199         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2200
2201         /* Set the write pointer delay */
2202         WREG32(CP_RB_WPTR_DELAY, 0);
2203
2204         /* Initialize the ring buffer's read and write pointers */
2205         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2206         WREG32(CP_RB_RPTR_WR, 0);
2207         ring->wptr = 0;
2208         WREG32(CP_RB_WPTR, ring->wptr);
2209
2210         /* set the wb address whether it's enabled or not */
2211         WREG32(CP_RB_RPTR_ADDR,
2212                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2213         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2214         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2215
2216         if (rdev->wb.enabled)
2217                 WREG32(SCRATCH_UMSK, 0xff);
2218         else {
2219                 tmp |= RB_NO_UPDATE;
2220                 WREG32(SCRATCH_UMSK, 0);
2221         }
2222
2223         mdelay(1);
2224         WREG32(CP_RB_CNTL, tmp);
2225
2226         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2227         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2228
2229         ring->rptr = RREG32(CP_RB_RPTR);
2230
2231         r600_cp_start(rdev);
2232         ring->ready = true;
2233         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2234         if (r) {
2235                 ring->ready = false;
2236                 return r;
2237         }
2238         return 0;
2239 }
2240
2241 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2242 {
2243         u32 rb_bufsz;
2244         int r;
2245
2246         /* Align ring size */
2247         rb_bufsz = drm_order(ring_size / 8);
2248         ring_size = (1 << (rb_bufsz + 1)) * 4;
2249         ring->ring_size = ring_size;
2250         ring->align_mask = 16 - 1;
2251
2252         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2253                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2254                 if (r) {
2255                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2256                         ring->rptr_save_reg = 0;
2257                 }
2258         }
2259 }
2260
2261 void r600_cp_fini(struct radeon_device *rdev)
2262 {
2263         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2264         r600_cp_stop(rdev);
2265         radeon_ring_fini(rdev, ring);
2266         radeon_scratch_free(rdev, ring->rptr_save_reg);
2267 }
2268
2269 /*
2270  * DMA
2271  * Starting with R600, the GPU has an asynchronous
2272  * DMA engine.  The programming model is very similar
2273  * to the 3D engine (ring buffer, IBs, etc.), but the
2274  * DMA controller has it's own packet format that is
2275  * different form the PM4 format used by the 3D engine.
2276  * It supports copying data, writing embedded data,
2277  * solid fills, and a number of other things.  It also
2278  * has support for tiling/detiling of buffers.
2279  */
2280 /**
2281  * r600_dma_stop - stop the async dma engine
2282  *
2283  * @rdev: radeon_device pointer
2284  *
2285  * Stop the async dma engine (r6xx-evergreen).
2286  */
2287 void r600_dma_stop(struct radeon_device *rdev)
2288 {
2289         u32 rb_cntl = RREG32(DMA_RB_CNTL);
2290
2291         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2292
2293         rb_cntl &= ~DMA_RB_ENABLE;
2294         WREG32(DMA_RB_CNTL, rb_cntl);
2295
2296         rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
2297 }
2298
2299 /**
2300  * r600_dma_resume - setup and start the async dma engine
2301  *
2302  * @rdev: radeon_device pointer
2303  *
2304  * Set up the DMA ring buffer and enable it. (r6xx-evergreen).
2305  * Returns 0 for success, error for failure.
2306  */
2307 int r600_dma_resume(struct radeon_device *rdev)
2308 {
2309         struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2310         u32 rb_cntl, dma_cntl;
2311         u32 rb_bufsz;
2312         int r;
2313
2314         /* Reset dma */
2315         if (rdev->family >= CHIP_RV770)
2316                 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA);
2317         else
2318                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2319         RREG32(SRBM_SOFT_RESET);
2320         udelay(50);
2321         WREG32(SRBM_SOFT_RESET, 0);
2322
2323         WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
2324         WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL, 0);
2325
2326         /* Set ring buffer size in dwords */
2327         rb_bufsz = drm_order(ring->ring_size / 4);
2328         rb_cntl = rb_bufsz << 1;
2329 #ifdef __BIG_ENDIAN
2330         rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;
2331 #endif
2332         WREG32(DMA_RB_CNTL, rb_cntl);
2333
2334         /* Initialize the ring buffer's read and write pointers */
2335         WREG32(DMA_RB_RPTR, 0);
2336         WREG32(DMA_RB_WPTR, 0);
2337
2338         /* set the wb address whether it's enabled or not */
2339         WREG32(DMA_RB_RPTR_ADDR_HI,
2340                upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
2341         WREG32(DMA_RB_RPTR_ADDR_LO,
2342                ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
2343
2344         if (rdev->wb.enabled)
2345                 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE;
2346
2347         WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2348
2349         /* enable DMA IBs */
2350         WREG32(DMA_IB_CNTL, DMA_IB_ENABLE);
2351
2352         dma_cntl = RREG32(DMA_CNTL);
2353         dma_cntl &= ~CTXEMPTY_INT_ENABLE;
2354         WREG32(DMA_CNTL, dma_cntl);
2355
2356         if (rdev->family >= CHIP_RV770)
2357                 WREG32(DMA_MODE, 1);
2358
2359         ring->wptr = 0;
2360         WREG32(DMA_RB_WPTR, ring->wptr << 2);
2361
2362         ring->rptr = RREG32(DMA_RB_RPTR) >> 2;
2363
2364         WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);
2365
2366         ring->ready = true;
2367
2368         r = radeon_ring_test(rdev, R600_RING_TYPE_DMA_INDEX, ring);
2369         if (r) {
2370                 ring->ready = false;
2371                 return r;
2372         }
2373
2374         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2375
2376         return 0;
2377 }
2378
2379 /**
2380  * r600_dma_fini - tear down the async dma engine
2381  *
2382  * @rdev: radeon_device pointer
2383  *
2384  * Stop the async dma engine and free the ring (r6xx-evergreen).
2385  */
2386 void r600_dma_fini(struct radeon_device *rdev)
2387 {
2388         r600_dma_stop(rdev);
2389         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2390 }
2391
2392 /*
2393  * GPU scratch registers helpers function.
2394  */
2395 void r600_scratch_init(struct radeon_device *rdev)
2396 {
2397         int i;
2398
2399         rdev->scratch.num_reg = 7;
2400         rdev->scratch.reg_base = SCRATCH_REG0;
2401         for (i = 0; i < rdev->scratch.num_reg; i++) {
2402                 rdev->scratch.free[i] = true;
2403                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2404         }
2405 }
2406
2407 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2408 {
2409         uint32_t scratch;
2410         uint32_t tmp = 0;
2411         unsigned i;
2412         int r;
2413
2414         r = radeon_scratch_get(rdev, &scratch);
2415         if (r) {
2416                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2417                 return r;
2418         }
2419         WREG32(scratch, 0xCAFEDEAD);
2420         r = radeon_ring_lock(rdev, ring, 3);
2421         if (r) {
2422                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2423                 radeon_scratch_free(rdev, scratch);
2424                 return r;
2425         }
2426         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2427         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2428         radeon_ring_write(ring, 0xDEADBEEF);
2429         radeon_ring_unlock_commit(rdev, ring);
2430         for (i = 0; i < rdev->usec_timeout; i++) {
2431                 tmp = RREG32(scratch);
2432                 if (tmp == 0xDEADBEEF)
2433                         break;
2434                 DRM_UDELAY(1);
2435         }
2436         if (i < rdev->usec_timeout) {
2437                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2438         } else {
2439                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2440                           ring->idx, scratch, tmp);
2441                 r = -EINVAL;
2442         }
2443         radeon_scratch_free(rdev, scratch);
2444         return r;
2445 }
2446
2447 /**
2448  * r600_dma_ring_test - simple async dma engine test
2449  *
2450  * @rdev: radeon_device pointer
2451  * @ring: radeon_ring structure holding ring information
2452  *
2453  * Test the DMA engine by writing using it to write an
2454  * value to memory. (r6xx-SI).
2455  * Returns 0 for success, error for failure.
2456  */
2457 int r600_dma_ring_test(struct radeon_device *rdev,
2458                        struct radeon_ring *ring)
2459 {
2460         unsigned i;
2461         int r;
2462         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2463         u32 tmp;
2464
2465         if (!ptr) {
2466                 DRM_ERROR("invalid vram scratch pointer\n");
2467                 return -EINVAL;
2468         }
2469
2470         tmp = 0xCAFEDEAD;
2471         writel(tmp, ptr);
2472
2473         r = radeon_ring_lock(rdev, ring, 4);
2474         if (r) {
2475                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2476                 return r;
2477         }
2478         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
2479         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2480         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff);
2481         radeon_ring_write(ring, 0xDEADBEEF);
2482         radeon_ring_unlock_commit(rdev, ring);
2483
2484         for (i = 0; i < rdev->usec_timeout; i++) {
2485                 tmp = readl(ptr);
2486                 if (tmp == 0xDEADBEEF)
2487                         break;
2488                 DRM_UDELAY(1);
2489         }
2490
2491         if (i < rdev->usec_timeout) {
2492                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2493         } else {
2494                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2495                           ring->idx, tmp);
2496                 r = -EINVAL;
2497         }
2498         return r;
2499 }
2500
2501 /*
2502  * CP fences/semaphores
2503  */
2504
2505 void r600_fence_ring_emit(struct radeon_device *rdev,
2506                           struct radeon_fence *fence)
2507 {
2508         struct radeon_ring *ring = &rdev->ring[fence->ring];
2509
2510         if (rdev->wb.use_event) {
2511                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2512                 /* flush read cache over gart */
2513                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2514                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2515                                         PACKET3_VC_ACTION_ENA |
2516                                         PACKET3_SH_ACTION_ENA);
2517                 radeon_ring_write(ring, 0xFFFFFFFF);
2518                 radeon_ring_write(ring, 0);
2519                 radeon_ring_write(ring, 10); /* poll interval */
2520                 /* EVENT_WRITE_EOP - flush caches, send int */
2521                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2522                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2523                 radeon_ring_write(ring, addr & 0xffffffff);
2524                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2525                 radeon_ring_write(ring, fence->seq);
2526                 radeon_ring_write(ring, 0);
2527         } else {
2528                 /* flush read cache over gart */
2529                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2530                 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
2531                                         PACKET3_VC_ACTION_ENA |
2532                                         PACKET3_SH_ACTION_ENA);
2533                 radeon_ring_write(ring, 0xFFFFFFFF);
2534                 radeon_ring_write(ring, 0);
2535                 radeon_ring_write(ring, 10); /* poll interval */
2536                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2537                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2538                 /* wait for 3D idle clean */
2539                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2540                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2541                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2542                 /* Emit fence sequence & fire IRQ */
2543                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2544                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2545                 radeon_ring_write(ring, fence->seq);
2546                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2547                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2548                 radeon_ring_write(ring, RB_INT_STAT);
2549         }
2550 }
2551
2552 void r600_semaphore_ring_emit(struct radeon_device *rdev,
2553                               struct radeon_ring *ring,
2554                               struct radeon_semaphore *semaphore,
2555                               bool emit_wait)
2556 {
2557         uint64_t addr = semaphore->gpu_addr;
2558         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2559
2560         if (rdev->family < CHIP_CAYMAN)
2561                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2562
2563         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2564         radeon_ring_write(ring, addr & 0xffffffff);
2565         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2566 }
2567
2568 /*
2569  * DMA fences/semaphores
2570  */
2571
2572 /**
2573  * r600_dma_fence_ring_emit - emit a fence on the DMA ring
2574  *
2575  * @rdev: radeon_device pointer
2576  * @fence: radeon fence object
2577  *
2578  * Add a DMA fence packet to the ring to write
2579  * the fence seq number and DMA trap packet to generate
2580  * an interrupt if needed (r6xx-r7xx).
2581  */
2582 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
2583                               struct radeon_fence *fence)
2584 {
2585         struct radeon_ring *ring = &rdev->ring[fence->ring];
2586         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2587
2588         /* write the fence */
2589         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
2590         radeon_ring_write(ring, addr & 0xfffffffc);
2591         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
2592         radeon_ring_write(ring, lower_32_bits(fence->seq));
2593         /* generate an interrupt */
2594         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
2595 }
2596
2597 /**
2598  * r600_dma_semaphore_ring_emit - emit a semaphore on the dma ring
2599  *
2600  * @rdev: radeon_device pointer
2601  * @ring: radeon_ring structure holding ring information
2602  * @semaphore: radeon semaphore object
2603  * @emit_wait: wait or signal semaphore
2604  *
2605  * Add a DMA semaphore packet to the ring wait on or signal
2606  * other rings (r6xx-SI).
2607  */
2608 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
2609                                   struct radeon_ring *ring,
2610                                   struct radeon_semaphore *semaphore,
2611                                   bool emit_wait)
2612 {
2613         u64 addr = semaphore->gpu_addr;
2614         u32 s = emit_wait ? 0 : 1;
2615
2616         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SEMAPHORE, 0, s, 0));
2617         radeon_ring_write(ring, addr & 0xfffffffc);
2618         radeon_ring_write(ring, upper_32_bits(addr) & 0xff);
2619 }
2620
2621 int r600_copy_blit(struct radeon_device *rdev,
2622                    uint64_t src_offset,
2623                    uint64_t dst_offset,
2624                    unsigned num_gpu_pages,
2625                    struct radeon_fence **fence)
2626 {
2627         struct radeon_semaphore *sem = NULL;
2628         struct radeon_sa_bo *vb = NULL;
2629         int r;
2630
2631         r = r600_blit_prepare_copy(rdev, num_gpu_pages, fence, &vb, &sem);
2632         if (r) {
2633                 return r;
2634         }
2635         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages, vb);
2636         r600_blit_done_copy(rdev, fence, vb, sem);
2637         return 0;
2638 }
2639
2640 /**
2641  * r600_copy_dma - copy pages using the DMA engine
2642  *
2643  * @rdev: radeon_device pointer
2644  * @src_offset: src GPU address
2645  * @dst_offset: dst GPU address
2646  * @num_gpu_pages: number of GPU pages to xfer
2647  * @fence: radeon fence object
2648  *
2649  * Copy GPU paging using the DMA engine (r6xx).
2650  * Used by the radeon ttm implementation to move pages if
2651  * registered as the asic copy callback.
2652  */
2653 int r600_copy_dma(struct radeon_device *rdev,
2654                   uint64_t src_offset, uint64_t dst_offset,
2655                   unsigned num_gpu_pages,
2656                   struct radeon_fence **fence)
2657 {
2658         struct radeon_semaphore *sem = NULL;
2659         int ring_index = rdev->asic->copy.dma_ring_index;
2660         struct radeon_ring *ring = &rdev->ring[ring_index];
2661         u32 size_in_dw, cur_size_in_dw;
2662         int i, num_loops;
2663         int r = 0;
2664
2665         r = radeon_semaphore_create(rdev, &sem);
2666         if (r) {
2667                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2668                 return r;
2669         }
2670
2671         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
2672         num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFE);
2673         r = radeon_ring_lock(rdev, ring, num_loops * 4 + 8);
2674         if (r) {
2675                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2676                 radeon_semaphore_free(rdev, &sem, NULL);
2677                 return r;
2678         }
2679
2680         if (radeon_fence_need_sync(*fence, ring->idx)) {
2681                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2682                                             ring->idx);
2683                 radeon_fence_note_sync(*fence, ring->idx);
2684         } else {
2685                 radeon_semaphore_free(rdev, &sem, NULL);
2686         }
2687
2688         for (i = 0; i < num_loops; i++) {
2689                 cur_size_in_dw = size_in_dw;
2690                 if (cur_size_in_dw > 0xFFFE)
2691                         cur_size_in_dw = 0xFFFE;
2692                 size_in_dw -= cur_size_in_dw;
2693                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
2694                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2695                 radeon_ring_write(ring, src_offset & 0xfffffffc);
2696                 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) |
2697                                          (upper_32_bits(src_offset) & 0xff)));
2698                 src_offset += cur_size_in_dw * 4;
2699                 dst_offset += cur_size_in_dw * 4;
2700         }
2701
2702         r = radeon_fence_emit(rdev, fence, ring->idx);
2703         if (r) {
2704                 radeon_ring_unlock_undo(rdev, ring);
2705                 return r;
2706         }
2707
2708         radeon_ring_unlock_commit(rdev, ring);
2709         radeon_semaphore_free(rdev, &sem, *fence);
2710
2711         return r;
2712 }
2713
2714 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2715                          uint32_t tiling_flags, uint32_t pitch,
2716                          uint32_t offset, uint32_t obj_size)
2717 {
2718         /* FIXME: implement */
2719         return 0;
2720 }
2721
2722 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2723 {
2724         /* FIXME: implement */
2725 }
2726
2727 static int r600_startup(struct radeon_device *rdev)
2728 {
2729         struct radeon_ring *ring;
2730         int r;
2731
2732         /* enable pcie gen2 link */
2733         r600_pcie_gen2_enable(rdev);
2734
2735         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2736                 r = r600_init_microcode(rdev);
2737                 if (r) {
2738                         DRM_ERROR("Failed to load firmware!\n");
2739                         return r;
2740                 }
2741         }
2742
2743         r = r600_vram_scratch_init(rdev);
2744         if (r)
2745                 return r;
2746
2747         r600_mc_program(rdev);
2748         if (rdev->flags & RADEON_IS_AGP) {
2749                 r600_agp_enable(rdev);
2750         } else {
2751                 r = r600_pcie_gart_enable(rdev);
2752                 if (r)
2753                         return r;
2754         }
2755         r600_gpu_init(rdev);
2756         r = r600_blit_init(rdev);
2757         if (r) {
2758                 r600_blit_fini(rdev);
2759                 rdev->asic->copy.copy = NULL;
2760                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2761         }
2762
2763         /* allocate wb buffer */
2764         r = radeon_wb_init(rdev);
2765         if (r)
2766                 return r;
2767
2768         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2769         if (r) {
2770                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2771                 return r;
2772         }
2773
2774         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2775         if (r) {
2776                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2777                 return r;
2778         }
2779
2780         /* Enable IRQ */
2781         r = r600_irq_init(rdev);
2782         if (r) {
2783                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2784                 radeon_irq_kms_fini(rdev);
2785                 return r;
2786         }
2787         r600_irq_set(rdev);
2788
2789         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2790         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2791                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
2792                              0, 0xfffff, RADEON_CP_PACKET2);
2793         if (r)
2794                 return r;
2795
2796         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2797         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2798                              DMA_RB_RPTR, DMA_RB_WPTR,
2799                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2800         if (r)
2801                 return r;
2802
2803         r = r600_cp_load_microcode(rdev);
2804         if (r)
2805                 return r;
2806         r = r600_cp_resume(rdev);
2807         if (r)
2808                 return r;
2809
2810         r = r600_dma_resume(rdev);
2811         if (r)
2812                 return r;
2813
2814         r = radeon_ib_pool_init(rdev);
2815         if (r) {
2816                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2817                 return r;
2818         }
2819
2820         r = r600_audio_init(rdev);
2821         if (r) {
2822                 DRM_ERROR("radeon: audio init failed\n");
2823                 return r;
2824         }
2825
2826         return 0;
2827 }
2828
2829 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2830 {
2831         uint32_t temp;
2832
2833         temp = RREG32(CONFIG_CNTL);
2834         if (state == false) {
2835                 temp &= ~(1<<0);
2836                 temp |= (1<<1);
2837         } else {
2838                 temp &= ~(1<<1);
2839         }
2840         WREG32(CONFIG_CNTL, temp);
2841 }
2842
2843 int r600_resume(struct radeon_device *rdev)
2844 {
2845         int r;
2846
2847         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2848          * posting will perform necessary task to bring back GPU into good
2849          * shape.
2850          */
2851         /* post card */
2852         atom_asic_init(rdev->mode_info.atom_context);
2853
2854         rdev->accel_working = true;
2855         r = r600_startup(rdev);
2856         if (r) {
2857                 DRM_ERROR("r600 startup failed on resume\n");
2858                 rdev->accel_working = false;
2859                 return r;
2860         }
2861
2862         return r;
2863 }
2864
2865 int r600_suspend(struct radeon_device *rdev)
2866 {
2867         r600_audio_fini(rdev);
2868         r600_cp_stop(rdev);
2869         r600_dma_stop(rdev);
2870         r600_irq_suspend(rdev);
2871         radeon_wb_disable(rdev);
2872         r600_pcie_gart_disable(rdev);
2873
2874         return 0;
2875 }
2876
2877 /* Plan is to move initialization in that function and use
2878  * helper function so that radeon_device_init pretty much
2879  * do nothing more than calling asic specific function. This
2880  * should also allow to remove a bunch of callback function
2881  * like vram_info.
2882  */
2883 int r600_init(struct radeon_device *rdev)
2884 {
2885         int r;
2886
2887         if (r600_debugfs_mc_info_init(rdev)) {
2888                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2889         }
2890         /* Read BIOS */
2891         if (!radeon_get_bios(rdev)) {
2892                 if (ASIC_IS_AVIVO(rdev))
2893                         return -EINVAL;
2894         }
2895         /* Must be an ATOMBIOS */
2896         if (!rdev->is_atom_bios) {
2897                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2898                 return -EINVAL;
2899         }
2900         r = radeon_atombios_init(rdev);
2901         if (r)
2902                 return r;
2903         /* Post card if necessary */
2904         if (!radeon_card_posted(rdev)) {
2905                 if (!rdev->bios) {
2906                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2907                         return -EINVAL;
2908                 }
2909                 DRM_INFO("GPU not posted. posting now...\n");
2910                 atom_asic_init(rdev->mode_info.atom_context);
2911         }
2912         /* Initialize scratch registers */
2913         r600_scratch_init(rdev);
2914         /* Initialize surface registers */
2915         radeon_surface_init(rdev);
2916         /* Initialize clocks */
2917         radeon_get_clock_info(rdev->ddev);
2918         /* Fence driver */
2919         r = radeon_fence_driver_init(rdev);
2920         if (r)
2921                 return r;
2922         if (rdev->flags & RADEON_IS_AGP) {
2923                 r = radeon_agp_init(rdev);
2924                 if (r)
2925                         radeon_agp_disable(rdev);
2926         }
2927         r = r600_mc_init(rdev);
2928         if (r)
2929                 return r;
2930         /* Memory manager */
2931         r = radeon_bo_init(rdev);
2932         if (r)
2933                 return r;
2934
2935         r = radeon_irq_kms_init(rdev);
2936         if (r)
2937                 return r;
2938
2939         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2940         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2941
2942         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2943         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2944
2945         rdev->ih.ring_obj = NULL;
2946         r600_ih_ring_init(rdev, 64 * 1024);
2947
2948         r = r600_pcie_gart_init(rdev);
2949         if (r)
2950                 return r;
2951
2952         rdev->accel_working = true;
2953         r = r600_startup(rdev);
2954         if (r) {
2955                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2956                 r600_cp_fini(rdev);
2957                 r600_dma_fini(rdev);
2958                 r600_irq_fini(rdev);
2959                 radeon_wb_fini(rdev);
2960                 radeon_ib_pool_fini(rdev);
2961                 radeon_irq_kms_fini(rdev);
2962                 r600_pcie_gart_fini(rdev);
2963                 rdev->accel_working = false;
2964         }
2965
2966         return 0;
2967 }
2968
2969 void r600_fini(struct radeon_device *rdev)
2970 {
2971         r600_audio_fini(rdev);
2972         r600_blit_fini(rdev);
2973         r600_cp_fini(rdev);
2974         r600_dma_fini(rdev);
2975         r600_irq_fini(rdev);
2976         radeon_wb_fini(rdev);
2977         radeon_ib_pool_fini(rdev);
2978         radeon_irq_kms_fini(rdev);
2979         r600_pcie_gart_fini(rdev);
2980         r600_vram_scratch_fini(rdev);
2981         radeon_agp_fini(rdev);
2982         radeon_gem_fini(rdev);
2983         radeon_fence_driver_fini(rdev);
2984         radeon_bo_fini(rdev);
2985         radeon_atombios_fini(rdev);
2986         kfree(rdev->bios);
2987         rdev->bios = NULL;
2988 }
2989
2990
2991 /*
2992  * CS stuff
2993  */
2994 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2995 {
2996         struct radeon_ring *ring = &rdev->ring[ib->ring];
2997         u32 next_rptr;
2998
2999         if (ring->rptr_save_reg) {
3000                 next_rptr = ring->wptr + 3 + 4;
3001                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3002                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3003                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3004                 radeon_ring_write(ring, next_rptr);
3005         } else if (rdev->wb.enabled) {
3006                 next_rptr = ring->wptr + 5 + 4;
3007                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3008                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3009                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3010                 radeon_ring_write(ring, next_rptr);
3011                 radeon_ring_write(ring, 0);
3012         }
3013
3014         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3015         radeon_ring_write(ring,
3016 #ifdef __BIG_ENDIAN
3017                           (2 << 0) |
3018 #endif
3019                           (ib->gpu_addr & 0xFFFFFFFC));
3020         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3021         radeon_ring_write(ring, ib->length_dw);
3022 }
3023
3024 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3025 {
3026         struct radeon_ib ib;
3027         uint32_t scratch;
3028         uint32_t tmp = 0;
3029         unsigned i;
3030         int r;
3031
3032         r = radeon_scratch_get(rdev, &scratch);
3033         if (r) {
3034                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3035                 return r;
3036         }
3037         WREG32(scratch, 0xCAFEDEAD);
3038         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3039         if (r) {
3040                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3041                 goto free_scratch;
3042         }
3043         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3044         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3045         ib.ptr[2] = 0xDEADBEEF;
3046         ib.length_dw = 3;
3047         r = radeon_ib_schedule(rdev, &ib, NULL);
3048         if (r) {
3049                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3050                 goto free_ib;
3051         }
3052         r = radeon_fence_wait(ib.fence, false);
3053         if (r) {
3054                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3055                 goto free_ib;
3056         }
3057         for (i = 0; i < rdev->usec_timeout; i++) {
3058                 tmp = RREG32(scratch);
3059                 if (tmp == 0xDEADBEEF)
3060                         break;
3061                 DRM_UDELAY(1);
3062         }
3063         if (i < rdev->usec_timeout) {
3064                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3065         } else {
3066                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3067                           scratch, tmp);
3068                 r = -EINVAL;
3069         }
3070 free_ib:
3071         radeon_ib_free(rdev, &ib);
3072 free_scratch:
3073         radeon_scratch_free(rdev, scratch);
3074         return r;
3075 }
3076
3077 /**
3078  * r600_dma_ib_test - test an IB on the DMA engine
3079  *
3080  * @rdev: radeon_device pointer
3081  * @ring: radeon_ring structure holding ring information
3082  *
3083  * Test a simple IB in the DMA ring (r6xx-SI).
3084  * Returns 0 on success, error on failure.
3085  */
3086 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3087 {
3088         struct radeon_ib ib;
3089         unsigned i;
3090         int r;
3091         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3092         u32 tmp = 0;
3093
3094         if (!ptr) {
3095                 DRM_ERROR("invalid vram scratch pointer\n");
3096                 return -EINVAL;
3097         }
3098
3099         tmp = 0xCAFEDEAD;
3100         writel(tmp, ptr);
3101
3102         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3103         if (r) {
3104                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3105                 return r;
3106         }
3107
3108         ib.ptr[0] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1);
3109         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
3110         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xff;
3111         ib.ptr[3] = 0xDEADBEEF;
3112         ib.length_dw = 4;
3113
3114         r = radeon_ib_schedule(rdev, &ib, NULL);
3115         if (r) {
3116                 radeon_ib_free(rdev, &ib);
3117                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3118                 return r;
3119         }
3120         r = radeon_fence_wait(ib.fence, false);
3121         if (r) {
3122                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3123                 return r;
3124         }
3125         for (i = 0; i < rdev->usec_timeout; i++) {
3126                 tmp = readl(ptr);
3127                 if (tmp == 0xDEADBEEF)
3128                         break;
3129                 DRM_UDELAY(1);
3130         }
3131         if (i < rdev->usec_timeout) {
3132                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3133         } else {
3134                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
3135                 r = -EINVAL;
3136         }
3137         radeon_ib_free(rdev, &ib);
3138         return r;
3139 }
3140
3141 /**
3142  * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
3143  *
3144  * @rdev: radeon_device pointer
3145  * @ib: IB object to schedule
3146  *
3147  * Schedule an IB in the DMA ring (r6xx-r7xx).
3148  */
3149 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3150 {
3151         struct radeon_ring *ring = &rdev->ring[ib->ring];
3152
3153         if (rdev->wb.enabled) {
3154                 u32 next_rptr = ring->wptr + 4;
3155                 while ((next_rptr & 7) != 5)
3156                         next_rptr++;
3157                 next_rptr += 3;
3158                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3159                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3160                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3161                 radeon_ring_write(ring, next_rptr);
3162         }
3163
3164         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3165          * Pad as necessary with NOPs.
3166          */
3167         while ((ring->wptr & 7) != 5)
3168                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3169         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3170         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3171         radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3172
3173 }
3174
3175 /*
3176  * Interrupts
3177  *
3178  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3179  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3180  * writing to the ring and the GPU consuming, the GPU writes to the ring
3181  * and host consumes.  As the host irq handler processes interrupts, it
3182  * increments the rptr.  When the rptr catches up with the wptr, all the
3183  * current interrupts have been processed.
3184  */
3185
3186 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3187 {
3188         u32 rb_bufsz;
3189
3190         /* Align ring size */
3191         rb_bufsz = drm_order(ring_size / 4);
3192         ring_size = (1 << rb_bufsz) * 4;
3193         rdev->ih.ring_size = ring_size;
3194         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3195         rdev->ih.rptr = 0;
3196 }
3197
3198 int r600_ih_ring_alloc(struct radeon_device *rdev)
3199 {
3200         int r;
3201
3202         /* Allocate ring buffer */
3203         if (rdev->ih.ring_obj == NULL) {
3204                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3205                                      PAGE_SIZE, true,
3206                                      RADEON_GEM_DOMAIN_GTT,
3207                                      NULL, &rdev->ih.ring_obj);
3208                 if (r) {
3209                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3210                         return r;
3211                 }
3212                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3213                 if (unlikely(r != 0))
3214                         return r;
3215                 r = radeon_bo_pin(rdev->ih.ring_obj,
3216                                   RADEON_GEM_DOMAIN_GTT,
3217                                   &rdev->ih.gpu_addr);
3218                 if (r) {
3219                         radeon_bo_unreserve(rdev->ih.ring_obj);
3220                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3221                         return r;
3222                 }
3223                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3224                                    (void **)&rdev->ih.ring);
3225                 radeon_bo_unreserve(rdev->ih.ring_obj);
3226                 if (r) {
3227                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3228                         return r;
3229                 }
3230         }
3231         return 0;
3232 }
3233
3234 void r600_ih_ring_fini(struct radeon_device *rdev)
3235 {
3236         int r;
3237         if (rdev->ih.ring_obj) {
3238                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3239                 if (likely(r == 0)) {
3240                         radeon_bo_kunmap(rdev->ih.ring_obj);
3241                         radeon_bo_unpin(rdev->ih.ring_obj);
3242                         radeon_bo_unreserve(rdev->ih.ring_obj);
3243                 }
3244                 radeon_bo_unref(&rdev->ih.ring_obj);
3245                 rdev->ih.ring = NULL;
3246                 rdev->ih.ring_obj = NULL;
3247         }
3248 }
3249
3250 void r600_rlc_stop(struct radeon_device *rdev)
3251 {
3252
3253         if ((rdev->family >= CHIP_RV770) &&
3254             (rdev->family <= CHIP_RV740)) {
3255                 /* r7xx asics need to soft reset RLC before halting */
3256                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3257                 RREG32(SRBM_SOFT_RESET);
3258                 mdelay(15);
3259                 WREG32(SRBM_SOFT_RESET, 0);
3260                 RREG32(SRBM_SOFT_RESET);
3261         }
3262
3263         WREG32(RLC_CNTL, 0);
3264 }
3265
3266 static void r600_rlc_start(struct radeon_device *rdev)
3267 {
3268         WREG32(RLC_CNTL, RLC_ENABLE);
3269 }
3270
3271 static int r600_rlc_init(struct radeon_device *rdev)
3272 {
3273         u32 i;
3274         const __be32 *fw_data;
3275
3276         if (!rdev->rlc_fw)
3277                 return -EINVAL;
3278
3279         r600_rlc_stop(rdev);
3280
3281         WREG32(RLC_HB_CNTL, 0);
3282
3283         if (rdev->family == CHIP_ARUBA) {
3284                 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
3285                 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
3286         }
3287         if (rdev->family <= CHIP_CAYMAN) {
3288                 WREG32(RLC_HB_BASE, 0);
3289                 WREG32(RLC_HB_RPTR, 0);
3290                 WREG32(RLC_HB_WPTR, 0);
3291         }
3292         if (rdev->family <= CHIP_CAICOS) {
3293                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3294                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3295         }
3296         WREG32(RLC_MC_CNTL, 0);
3297         WREG32(RLC_UCODE_CNTL, 0);
3298
3299         fw_data = (const __be32 *)rdev->rlc_fw->data;
3300         if (rdev->family >= CHIP_ARUBA) {
3301                 for (i = 0; i < ARUBA_RLC_UCODE_SIZE; i++) {
3302                         WREG32(RLC_UCODE_ADDR, i);
3303                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3304                 }
3305         } else if (rdev->family >= CHIP_CAYMAN) {
3306                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
3307                         WREG32(RLC_UCODE_ADDR, i);
3308                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3309                 }
3310         } else if (rdev->family >= CHIP_CEDAR) {
3311                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
3312                         WREG32(RLC_UCODE_ADDR, i);
3313                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3314                 }
3315         } else if (rdev->family >= CHIP_RV770) {
3316                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3317                         WREG32(RLC_UCODE_ADDR, i);
3318                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3319                 }
3320         } else {
3321                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
3322                         WREG32(RLC_UCODE_ADDR, i);
3323                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3324                 }
3325         }
3326         WREG32(RLC_UCODE_ADDR, 0);
3327
3328         r600_rlc_start(rdev);
3329
3330         return 0;
3331 }
3332
3333 static void r600_enable_interrupts(struct radeon_device *rdev)
3334 {
3335         u32 ih_cntl = RREG32(IH_CNTL);
3336         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3337
3338         ih_cntl |= ENABLE_INTR;
3339         ih_rb_cntl |= IH_RB_ENABLE;
3340         WREG32(IH_CNTL, ih_cntl);
3341         WREG32(IH_RB_CNTL, ih_rb_cntl);
3342         rdev->ih.enabled = true;
3343 }
3344
3345 void r600_disable_interrupts(struct radeon_device *rdev)
3346 {
3347         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3348         u32 ih_cntl = RREG32(IH_CNTL);
3349
3350         ih_rb_cntl &= ~IH_RB_ENABLE;
3351         ih_cntl &= ~ENABLE_INTR;
3352         WREG32(IH_RB_CNTL, ih_rb_cntl);
3353         WREG32(IH_CNTL, ih_cntl);
3354         /* set rptr, wptr to 0 */
3355         WREG32(IH_RB_RPTR, 0);
3356         WREG32(IH_RB_WPTR, 0);
3357         rdev->ih.enabled = false;
3358         rdev->ih.rptr = 0;
3359 }
3360
3361 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3362 {
3363         u32 tmp;
3364
3365         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3366         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3367         WREG32(DMA_CNTL, tmp);
3368         WREG32(GRBM_INT_CNTL, 0);
3369         WREG32(DxMODE_INT_MASK, 0);
3370         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3371         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3372         if (ASIC_IS_DCE3(rdev)) {
3373                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3374                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3375                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3376                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3377                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3378                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3379                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3380                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3381                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3382                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3383                 if (ASIC_IS_DCE32(rdev)) {
3384                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3385                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3386                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3387                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3388                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3389                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3390                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3391                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3392                 } else {
3393                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3394                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3395                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3396                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3397                 }
3398         } else {
3399                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3400                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3401                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3402                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3403                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3404                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3405                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3406                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3407                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3408                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3409                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3410                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3411         }
3412 }
3413
3414 int r600_irq_init(struct radeon_device *rdev)
3415 {
3416         int ret = 0;
3417         int rb_bufsz;
3418         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3419
3420         /* allocate ring */
3421         ret = r600_ih_ring_alloc(rdev);
3422         if (ret)
3423                 return ret;
3424
3425         /* disable irqs */
3426         r600_disable_interrupts(rdev);
3427
3428         /* init rlc */
3429         ret = r600_rlc_init(rdev);
3430         if (ret) {
3431                 r600_ih_ring_fini(rdev);
3432                 return ret;
3433         }
3434
3435         /* setup interrupt control */
3436         /* set dummy read address to ring address */
3437         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3438         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3439         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3440          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3441          */
3442         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3443         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3444         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3445         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3446
3447         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3448         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3449
3450         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3451                       IH_WPTR_OVERFLOW_CLEAR |
3452                       (rb_bufsz << 1));
3453
3454         if (rdev->wb.enabled)
3455                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3456
3457         /* set the writeback address whether it's enabled or not */
3458         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3459         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3460
3461         WREG32(IH_RB_CNTL, ih_rb_cntl);
3462
3463         /* set rptr, wptr to 0 */
3464         WREG32(IH_RB_RPTR, 0);
3465         WREG32(IH_RB_WPTR, 0);
3466
3467         /* Default settings for IH_CNTL (disabled at first) */
3468         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3469         /* RPTR_REARM only works if msi's are enabled */
3470         if (rdev->msi_enabled)
3471                 ih_cntl |= RPTR_REARM;
3472         WREG32(IH_CNTL, ih_cntl);
3473
3474         /* force the active interrupt state to all disabled */
3475         if (rdev->family >= CHIP_CEDAR)
3476                 evergreen_disable_interrupt_state(rdev);
3477         else
3478                 r600_disable_interrupt_state(rdev);
3479
3480         /* at this point everything should be setup correctly to enable master */
3481         pci_set_master(rdev->pdev);
3482
3483         /* enable irqs */
3484         r600_enable_interrupts(rdev);
3485
3486         return ret;
3487 }
3488
3489 void r600_irq_suspend(struct radeon_device *rdev)
3490 {
3491         r600_irq_disable(rdev);
3492         r600_rlc_stop(rdev);
3493 }
3494
3495 void r600_irq_fini(struct radeon_device *rdev)
3496 {
3497         r600_irq_suspend(rdev);
3498         r600_ih_ring_fini(rdev);
3499 }
3500
3501 int r600_irq_set(struct radeon_device *rdev)
3502 {
3503         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3504         u32 mode_int = 0;
3505         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3506         u32 grbm_int_cntl = 0;
3507         u32 hdmi0, hdmi1;
3508         u32 d1grph = 0, d2grph = 0;
3509         u32 dma_cntl;
3510
3511         if (!rdev->irq.installed) {
3512                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3513                 return -EINVAL;
3514         }
3515         /* don't enable anything if the ih is disabled */
3516         if (!rdev->ih.enabled) {
3517                 r600_disable_interrupts(rdev);
3518                 /* force the active interrupt state to all disabled */
3519                 r600_disable_interrupt_state(rdev);
3520                 return 0;
3521         }
3522
3523         if (ASIC_IS_DCE3(rdev)) {
3524                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3525                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3526                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3527                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3528                 if (ASIC_IS_DCE32(rdev)) {
3529                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3530                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3531                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3532                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3533                 } else {
3534                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3535                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3536                 }
3537         } else {
3538                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3539                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3540                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3541                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3542                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3543         }
3544         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3545
3546         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3547                 DRM_DEBUG("r600_irq_set: sw int\n");
3548                 cp_int_cntl |= RB_INT_ENABLE;
3549                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3550         }
3551
3552         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3553                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3554                 dma_cntl |= TRAP_ENABLE;
3555         }
3556
3557         if (rdev->irq.crtc_vblank_int[0] ||
3558             atomic_read(&rdev->irq.pflip[0])) {
3559                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3560                 mode_int |= D1MODE_VBLANK_INT_MASK;
3561         }
3562         if (rdev->irq.crtc_vblank_int[1] ||
3563             atomic_read(&rdev->irq.pflip[1])) {
3564                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3565                 mode_int |= D2MODE_VBLANK_INT_MASK;
3566         }
3567         if (rdev->irq.hpd[0]) {
3568                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3569                 hpd1 |= DC_HPDx_INT_EN;
3570         }
3571         if (rdev->irq.hpd[1]) {
3572                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3573                 hpd2 |= DC_HPDx_INT_EN;
3574         }
3575         if (rdev->irq.hpd[2]) {
3576                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3577                 hpd3 |= DC_HPDx_INT_EN;
3578         }
3579         if (rdev->irq.hpd[3]) {
3580                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3581                 hpd4 |= DC_HPDx_INT_EN;
3582         }
3583         if (rdev->irq.hpd[4]) {
3584                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3585                 hpd5 |= DC_HPDx_INT_EN;
3586         }
3587         if (rdev->irq.hpd[5]) {
3588                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3589                 hpd6 |= DC_HPDx_INT_EN;
3590         }
3591         if (rdev->irq.afmt[0]) {
3592                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3593                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3594         }
3595         if (rdev->irq.afmt[1]) {
3596                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3597                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3598         }
3599
3600         WREG32(CP_INT_CNTL, cp_int_cntl);
3601         WREG32(DMA_CNTL, dma_cntl);
3602         WREG32(DxMODE_INT_MASK, mode_int);
3603         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3604         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3605         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3606         if (ASIC_IS_DCE3(rdev)) {
3607                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3608                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3609                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3610                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3611                 if (ASIC_IS_DCE32(rdev)) {
3612                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3613                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3614                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3615                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3616                 } else {
3617                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3618                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3619                 }
3620         } else {
3621                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3622                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3623                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3624                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3625                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3626         }
3627
3628         return 0;
3629 }
3630
3631 static void r600_irq_ack(struct radeon_device *rdev)
3632 {
3633         u32 tmp;
3634
3635         if (ASIC_IS_DCE3(rdev)) {
3636                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3637                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3638                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3639                 if (ASIC_IS_DCE32(rdev)) {
3640                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3641                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3642                 } else {
3643                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3644                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3645                 }
3646         } else {
3647                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3648                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3649                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3650                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3651                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3652         }
3653         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3654         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3655
3656         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3657                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3658         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3659                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3660         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3661                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3662         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3663                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3664         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3665                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3666         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3667                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3668         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3669                 if (ASIC_IS_DCE3(rdev)) {
3670                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3671                         tmp |= DC_HPDx_INT_ACK;
3672                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3673                 } else {
3674                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3675                         tmp |= DC_HPDx_INT_ACK;
3676                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3677                 }
3678         }
3679         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3680                 if (ASIC_IS_DCE3(rdev)) {
3681                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3682                         tmp |= DC_HPDx_INT_ACK;
3683                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3684                 } else {
3685                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3686                         tmp |= DC_HPDx_INT_ACK;
3687                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3688                 }
3689         }
3690         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3691                 if (ASIC_IS_DCE3(rdev)) {
3692                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3693                         tmp |= DC_HPDx_INT_ACK;
3694                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3695                 } else {
3696                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3697                         tmp |= DC_HPDx_INT_ACK;
3698                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3699                 }
3700         }
3701         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3702                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3703                 tmp |= DC_HPDx_INT_ACK;
3704                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3705         }
3706         if (ASIC_IS_DCE32(rdev)) {
3707                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3708                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3709                         tmp |= DC_HPDx_INT_ACK;
3710                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3711                 }
3712                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3713                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3714                         tmp |= DC_HPDx_INT_ACK;
3715                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3716                 }
3717                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3718                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3719                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3720                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3721                 }
3722                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3723                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3724                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3725                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3726                 }
3727         } else {
3728                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3729                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3730                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3731                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3732                 }
3733                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3734                         if (ASIC_IS_DCE3(rdev)) {
3735                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3736                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3737                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3738                         } else {
3739                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3740                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3741                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3742                         }
3743                 }
3744         }
3745 }
3746
3747 void r600_irq_disable(struct radeon_device *rdev)
3748 {
3749         r600_disable_interrupts(rdev);
3750         /* Wait and acknowledge irq */
3751         mdelay(1);
3752         r600_irq_ack(rdev);
3753         r600_disable_interrupt_state(rdev);
3754 }
3755
3756 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3757 {
3758         u32 wptr, tmp;
3759
3760         if (rdev->wb.enabled)
3761                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3762         else
3763                 wptr = RREG32(IH_RB_WPTR);
3764
3765         if (wptr & RB_OVERFLOW) {
3766                 /* When a ring buffer overflow happen start parsing interrupt
3767                  * from the last not overwritten vector (wptr + 16). Hopefully
3768                  * this should allow us to catchup.
3769                  */
3770                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3771                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3772                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3773                 tmp = RREG32(IH_RB_CNTL);
3774                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3775                 WREG32(IH_RB_CNTL, tmp);
3776         }
3777         return (wptr & rdev->ih.ptr_mask);
3778 }
3779
3780 /*        r600 IV Ring
3781  * Each IV ring entry is 128 bits:
3782  * [7:0]    - interrupt source id
3783  * [31:8]   - reserved
3784  * [59:32]  - interrupt source data
3785  * [127:60]  - reserved
3786  *
3787  * The basic interrupt vector entries
3788  * are decoded as follows:
3789  * src_id  src_data  description
3790  *      1         0  D1 Vblank
3791  *      1         1  D1 Vline
3792  *      5         0  D2 Vblank
3793  *      5         1  D2 Vline
3794  *     19         0  FP Hot plug detection A
3795  *     19         1  FP Hot plug detection B
3796  *     19         2  DAC A auto-detection
3797  *     19         3  DAC B auto-detection
3798  *     21         4  HDMI block A
3799  *     21         5  HDMI block B
3800  *    176         -  CP_INT RB
3801  *    177         -  CP_INT IB1
3802  *    178         -  CP_INT IB2
3803  *    181         -  EOP Interrupt
3804  *    233         -  GUI Idle
3805  *
3806  * Note, these are based on r600 and may need to be
3807  * adjusted or added to on newer asics
3808  */
3809
3810 int r600_irq_process(struct radeon_device *rdev)
3811 {
3812         u32 wptr;
3813         u32 rptr;
3814         u32 src_id, src_data;
3815         u32 ring_index;
3816         bool queue_hotplug = false;
3817         bool queue_hdmi = false;
3818
3819         if (!rdev->ih.enabled || rdev->shutdown)
3820                 return IRQ_NONE;
3821
3822         /* No MSIs, need a dummy read to flush PCI DMAs */
3823         if (!rdev->msi_enabled)
3824                 RREG32(IH_RB_WPTR);
3825
3826         wptr = r600_get_ih_wptr(rdev);
3827
3828 restart_ih:
3829         /* is somebody else already processing irqs? */
3830         if (atomic_xchg(&rdev->ih.lock, 1))
3831                 return IRQ_NONE;
3832
3833         rptr = rdev->ih.rptr;
3834         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3835
3836         /* Order reading of wptr vs. reading of IH ring data */
3837         rmb();
3838
3839         /* display interrupts */
3840         r600_irq_ack(rdev);
3841
3842         while (rptr != wptr) {
3843                 /* wptr/rptr are in bytes! */
3844                 ring_index = rptr / 4;
3845                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3846                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3847
3848                 switch (src_id) {
3849                 case 1: /* D1 vblank/vline */
3850                         switch (src_data) {
3851                         case 0: /* D1 vblank */
3852                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3853                                         if (rdev->irq.crtc_vblank_int[0]) {
3854                                                 drm_handle_vblank(rdev->ddev, 0);
3855                                                 rdev->pm.vblank_sync = true;
3856                                                 wake_up(&rdev->irq.vblank_queue);
3857                                         }
3858                                         if (atomic_read(&rdev->irq.pflip[0]))
3859                                                 radeon_crtc_handle_flip(rdev, 0);
3860                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3861                                         DRM_DEBUG("IH: D1 vblank\n");
3862                                 }
3863                                 break;
3864                         case 1: /* D1 vline */
3865                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3866                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3867                                         DRM_DEBUG("IH: D1 vline\n");
3868                                 }
3869                                 break;
3870                         default:
3871                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3872                                 break;
3873                         }
3874                         break;
3875                 case 5: /* D2 vblank/vline */
3876                         switch (src_data) {
3877                         case 0: /* D2 vblank */
3878                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3879                                         if (rdev->irq.crtc_vblank_int[1]) {
3880                                                 drm_handle_vblank(rdev->ddev, 1);
3881                                                 rdev->pm.vblank_sync = true;
3882                                                 wake_up(&rdev->irq.vblank_queue);
3883                                         }
3884                                         if (atomic_read(&rdev->irq.pflip[1]))
3885                                                 radeon_crtc_handle_flip(rdev, 1);
3886                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3887                                         DRM_DEBUG("IH: D2 vblank\n");
3888                                 }
3889                                 break;
3890                         case 1: /* D1 vline */
3891                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3892                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3893                                         DRM_DEBUG("IH: D2 vline\n");
3894                                 }
3895                                 break;
3896                         default:
3897                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3898                                 break;
3899                         }
3900                         break;
3901                 case 19: /* HPD/DAC hotplug */
3902                         switch (src_data) {
3903                         case 0:
3904                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3905                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3906                                         queue_hotplug = true;
3907                                         DRM_DEBUG("IH: HPD1\n");
3908                                 }
3909                                 break;
3910                         case 1:
3911                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3912                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3913                                         queue_hotplug = true;
3914                                         DRM_DEBUG("IH: HPD2\n");
3915                                 }
3916                                 break;
3917                         case 4:
3918                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3919                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3920                                         queue_hotplug = true;
3921                                         DRM_DEBUG("IH: HPD3\n");
3922                                 }
3923                                 break;
3924                         case 5:
3925                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3926                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3927                                         queue_hotplug = true;
3928                                         DRM_DEBUG("IH: HPD4\n");
3929                                 }
3930                                 break;
3931                         case 10:
3932                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3933                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3934                                         queue_hotplug = true;
3935                                         DRM_DEBUG("IH: HPD5\n");
3936                                 }
3937                                 break;
3938                         case 12:
3939                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3940                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3941                                         queue_hotplug = true;
3942                                         DRM_DEBUG("IH: HPD6\n");
3943                                 }
3944                                 break;
3945                         default:
3946                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3947                                 break;
3948                         }
3949                         break;
3950                 case 21: /* hdmi */
3951                         switch (src_data) {
3952                         case 4:
3953                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3954                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3955                                         queue_hdmi = true;
3956                                         DRM_DEBUG("IH: HDMI0\n");
3957                                 }
3958                                 break;
3959                         case 5:
3960                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3961                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3962                                         queue_hdmi = true;
3963                                         DRM_DEBUG("IH: HDMI1\n");
3964                                 }
3965                                 break;
3966                         default:
3967                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3968                                 break;
3969                         }
3970                         break;
3971                 case 176: /* CP_INT in ring buffer */
3972                 case 177: /* CP_INT in IB1 */
3973                 case 178: /* CP_INT in IB2 */
3974                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3975                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3976                         break;
3977                 case 181: /* CP EOP event */
3978                         DRM_DEBUG("IH: CP EOP\n");
3979                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3980                         break;
3981                 case 224: /* DMA trap event */
3982                         DRM_DEBUG("IH: DMA trap\n");
3983                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3984                         break;
3985                 case 233: /* GUI IDLE */
3986                         DRM_DEBUG("IH: GUI idle\n");
3987                         break;
3988                 default:
3989                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3990                         break;
3991                 }
3992
3993                 /* wptr/rptr are in bytes! */
3994                 rptr += 16;
3995                 rptr &= rdev->ih.ptr_mask;
3996         }
3997         if (queue_hotplug)
3998                 schedule_work(&rdev->hotplug_work);
3999         if (queue_hdmi)
4000                 schedule_work(&rdev->audio_work);
4001         rdev->ih.rptr = rptr;
4002         WREG32(IH_RB_RPTR, rdev->ih.rptr);
4003         atomic_set(&rdev->ih.lock, 0);
4004
4005         /* make sure wptr hasn't changed while processing */
4006         wptr = r600_get_ih_wptr(rdev);
4007         if (wptr != rptr)
4008                 goto restart_ih;
4009
4010         return IRQ_HANDLED;
4011 }
4012
4013 /*
4014  * Debugfs info
4015  */
4016 #if defined(CONFIG_DEBUG_FS)
4017
4018 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4019 {
4020         struct drm_info_node *node = (struct drm_info_node *) m->private;
4021         struct drm_device *dev = node->minor->dev;
4022         struct radeon_device *rdev = dev->dev_private;
4023
4024         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4025         DREG32_SYS(m, rdev, VM_L2_STATUS);
4026         return 0;
4027 }
4028
4029 static struct drm_info_list r600_mc_info_list[] = {
4030         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4031 };
4032 #endif
4033
4034 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4035 {
4036 #if defined(CONFIG_DEBUG_FS)
4037         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4038 #else
4039         return 0;
4040 #endif
4041 }
4042
4043 /**
4044  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4045  * rdev: radeon device structure
4046  * bo: buffer object struct which userspace is waiting for idle
4047  *
4048  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4049  * through ring buffer, this leads to corruption in rendering, see
4050  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4051  * directly perform HDP flush by writing register through MMIO.
4052  */
4053 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4054 {
4055         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4056          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4057          * This seems to cause problems on some AGP cards. Just use the old
4058          * method for them.
4059          */
4060         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4061             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4062                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4063                 u32 tmp;
4064
4065                 WREG32(HDP_DEBUG1, 0);
4066                 tmp = readl((void __iomem *)ptr);
4067         } else
4068                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4069 }
4070
4071 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4072 {
4073         u32 link_width_cntl, mask, target_reg;
4074
4075         if (rdev->flags & RADEON_IS_IGP)
4076                 return;
4077
4078         if (!(rdev->flags & RADEON_IS_PCIE))
4079                 return;
4080
4081         /* x2 cards have a special sequence */
4082         if (ASIC_IS_X2(rdev))
4083                 return;
4084
4085         /* FIXME wait for idle */
4086
4087         switch (lanes) {
4088         case 0:
4089                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4090                 break;
4091         case 1:
4092                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4093                 break;
4094         case 2:
4095                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4096                 break;
4097         case 4:
4098                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4099                 break;
4100         case 8:
4101                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4102                 break;
4103         case 12:
4104                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4105                 break;
4106         case 16:
4107         default:
4108                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4109                 break;
4110         }
4111
4112         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4113
4114         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
4115             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
4116                 return;
4117
4118         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
4119                 return;
4120
4121         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
4122                              RADEON_PCIE_LC_RECONFIG_NOW |
4123                              R600_PCIE_LC_RENEGOTIATE_EN |
4124                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4125         link_width_cntl |= mask;
4126
4127         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4128
4129         /* some northbridges can renegotiate the link rather than requiring
4130          * a complete re-config.
4131          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
4132          */
4133         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
4134                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
4135         else
4136                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
4137
4138         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
4139                                                        RADEON_PCIE_LC_RECONFIG_NOW));
4140
4141         if (rdev->family >= CHIP_RV770)
4142                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
4143         else
4144                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
4145
4146         /* wait for lane set to complete */
4147         link_width_cntl = RREG32(target_reg);
4148         while (link_width_cntl == 0xffffffff)
4149                 link_width_cntl = RREG32(target_reg);
4150
4151 }
4152
4153 int r600_get_pcie_lanes(struct radeon_device *rdev)
4154 {
4155         u32 link_width_cntl;
4156
4157         if (rdev->flags & RADEON_IS_IGP)
4158                 return 0;
4159
4160         if (!(rdev->flags & RADEON_IS_PCIE))
4161                 return 0;
4162
4163         /* x2 cards have a special sequence */
4164         if (ASIC_IS_X2(rdev))
4165                 return 0;
4166
4167         /* FIXME wait for idle */
4168
4169         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4170
4171         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4172         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4173                 return 0;
4174         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4175                 return 1;
4176         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4177                 return 2;
4178         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4179                 return 4;
4180         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4181                 return 8;
4182         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4183         default:
4184                 return 16;
4185         }
4186 }
4187
4188 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4189 {
4190         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4191         u16 link_cntl2;
4192         u32 mask;
4193         int ret;
4194
4195         if (radeon_pcie_gen2 == 0)
4196                 return;
4197
4198         if (rdev->flags & RADEON_IS_IGP)
4199                 return;
4200
4201         if (!(rdev->flags & RADEON_IS_PCIE))
4202                 return;
4203
4204         /* x2 cards have a special sequence */
4205         if (ASIC_IS_X2(rdev))
4206                 return;
4207
4208         /* only RV6xx+ chips are supported */
4209         if (rdev->family <= CHIP_R600)
4210                 return;
4211
4212         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
4213         if (ret != 0)
4214                 return;
4215
4216         if (!(mask & DRM_PCIE_SPEED_50))
4217                 return;
4218
4219         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4220         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4221                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4222                 return;
4223         }
4224
4225         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4226
4227         /* 55 nm r6xx asics */
4228         if ((rdev->family == CHIP_RV670) ||
4229             (rdev->family == CHIP_RV620) ||
4230             (rdev->family == CHIP_RV635)) {
4231                 /* advertise upconfig capability */
4232                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4233                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4234                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4235                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4236                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4237                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4238                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4239                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4240                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4241                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4242                 } else {
4243                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4244                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4245                 }
4246         }
4247
4248         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4249         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4250             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4251
4252                 /* 55 nm r6xx asics */
4253                 if ((rdev->family == CHIP_RV670) ||
4254                     (rdev->family == CHIP_RV620) ||
4255                     (rdev->family == CHIP_RV635)) {
4256                         WREG32(MM_CFGREGS_CNTL, 0x8);
4257                         link_cntl2 = RREG32(0x4088);
4258                         WREG32(MM_CFGREGS_CNTL, 0);
4259                         /* not supported yet */
4260                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4261                                 return;
4262                 }
4263
4264                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4265                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4266                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4267                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4268                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4269                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4270
4271                 tmp = RREG32(0x541c);
4272                 WREG32(0x541c, tmp | 0x8);
4273                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4274                 link_cntl2 = RREG16(0x4088);
4275                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4276                 link_cntl2 |= 0x2;
4277                 WREG16(0x4088, link_cntl2);
4278                 WREG32(MM_CFGREGS_CNTL, 0);
4279
4280                 if ((rdev->family == CHIP_RV670) ||
4281                     (rdev->family == CHIP_RV620) ||
4282                     (rdev->family == CHIP_RV635)) {
4283                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
4284                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4285                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
4286                 } else {
4287                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4288                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4289                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4290                 }
4291
4292                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
4293                 speed_cntl |= LC_GEN2_EN_STRAP;
4294                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
4295
4296         } else {
4297                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
4298                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4299                 if (1)
4300                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4301                 else
4302                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4303                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4304         }
4305 }
4306
4307 /**
4308  * r600_get_gpu_clock - return GPU clock counter snapshot
4309  *
4310  * @rdev: radeon_device pointer
4311  *
4312  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4313  * Returns the 64 bit clock counter snapshot.
4314  */
4315 uint64_t r600_get_gpu_clock(struct radeon_device *rdev)
4316 {
4317         uint64_t clock;
4318
4319         mutex_lock(&rdev->gpu_clock_mutex);
4320         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4321         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4322                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4323         mutex_unlock(&rdev->gpu_clock_mutex);
4324         return clock;
4325 }