drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/module.h>
  32 #include <drm/drmP.h>
  33 #include <drm/radeon_drm.h>
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40 #include "radeon_ucode.h"
  41
  42 /* Firmware Names */
  43 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  44 MODULE_FIRMWARE("radeon/R600_me.bin");
  45 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  46 MODULE_FIRMWARE("radeon/RV610_me.bin");
  47 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  48 MODULE_FIRMWARE("radeon/RV630_me.bin");
  49 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  50 MODULE_FIRMWARE("radeon/RV620_me.bin");
  51 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  52 MODULE_FIRMWARE("radeon/RV635_me.bin");
  53 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  54 MODULE_FIRMWARE("radeon/RV670_me.bin");
  55 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RS780_me.bin");
  57 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV770_me.bin");
  59 MODULE_FIRMWARE("radeon/RV770_smc.bin");
  60 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV730_me.bin");
  62 MODULE_FIRMWARE("radeon/RV730_smc.bin");
  63 MODULE_FIRMWARE("radeon/RV740_smc.bin");
  64 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV710_me.bin");
  66 MODULE_FIRMWARE("radeon/RV710_smc.bin");
  67 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  68 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  69 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  70 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  71 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  72 MODULE_FIRMWARE("radeon/CEDAR_smc.bin");
  73 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  74 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  75 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  76 MODULE_FIRMWARE("radeon/REDWOOD_smc.bin");
  77 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  78 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  79 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_smc.bin");
  81 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  82 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_smc.bin");
  85 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  86 MODULE_FIRMWARE("radeon/PALM_me.bin");
  87 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_me.bin");
  90 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
  91 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
  92
  93 static const u32 crtc_offsets[2] =
  94 {
  95         0,
  96         AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
  97 };
  98
  99 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
 100
 101 /* r600,rv610,rv630,rv620,rv635,rv670 */
 102 int r600_mc_wait_for_idle(struct radeon_device *rdev);
 103 static void r600_gpu_init(struct radeon_device *rdev);
 104 void r600_fini(struct radeon_device *rdev);
 105 void r600_irq_disable(struct radeon_device *rdev);
 106 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
 107 extern int evergreen_rlc_resume(struct radeon_device *rdev);
 108 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 109
 110 /**
 111  * r600_get_xclk - get the xclk
 112  *
 113  * @rdev: radeon_device pointer
 114  *
 115  * Returns the reference clock used by the gfx engine
 116  * (r6xx, IGPs, APUs).
 117  */
 118 u32 r600_get_xclk(struct radeon_device *rdev)
 119 {
 120         return rdev->clock.spll.reference_freq;
 121 }
 122
 123 int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
 124 {
 125         return 0;
 126 }
 127
 128 void dce3_program_fmt(struct drm_encoder *encoder)
 129 {
 130         struct drm_device *dev = encoder->dev;
 131         struct radeon_device *rdev = dev->dev_private;
 132         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 133         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 134         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 135         int bpc = 0;
 136         u32 tmp = 0;
 137         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
 138
 139         if (connector) {
 140                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 141                 bpc = radeon_get_monitor_bpc(connector);
 142                 dither = radeon_connector->dither;
 143         }
 144
 145         /* LVDS FMT is set up by atom */
 146         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
 147                 return;
 148
 149         /* not needed for analog */
 150         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
 151             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
 152                 return;
 153
 154         if (bpc == 0)
 155                 return;
 156
 157         switch (bpc) {
 158         case 6:
 159                 if (dither == RADEON_FMT_DITHER_ENABLE)
 160                         /* XXX sort out optimal dither settings */
 161                         tmp |= FMT_SPATIAL_DITHER_EN;
 162                 else
 163                         tmp |= FMT_TRUNCATE_EN;
 164                 break;
 165         case 8:
 166                 if (dither == RADEON_FMT_DITHER_ENABLE)
 167                         /* XXX sort out optimal dither settings */
 168                         tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
 169                 else
 170                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
 171                 break;
 172         case 10:
 173         default:
 174                 /* not needed */
 175                 break;
 176         }
 177
 178         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
 179 }
 180
 181 /* get temperature in millidegrees */
 182 int rv6xx_get_temp(struct radeon_device *rdev)
 183 {
 184         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 185                 ASIC_T_SHIFT;
 186         int actual_temp = temp & 0xff;
 187
 188         if (temp & 0x100)
 189                 actual_temp -= 256;
 190
 191         return actual_temp * 1000;
 192 }
 193
 194 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 195 {
 196         int i;
 197
 198         rdev->pm.dynpm_can_upclock = true;
 199         rdev->pm.dynpm_can_downclock = true;
 200
 201         /* power state array is low to high, default is first */
 202         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 203                 int min_power_state_index = 0;
 204
 205                 if (rdev->pm.num_power_states > 2)
 206                         min_power_state_index = 1;
 207
 208                 switch (rdev->pm.dynpm_planned_action) {
 209                 case DYNPM_ACTION_MINIMUM:
 210                         rdev->pm.requested_power_state_index = min_power_state_index;
 211                         rdev->pm.requested_clock_mode_index = 0;
 212                         rdev->pm.dynpm_can_downclock = false;
 213                         break;
 214                 case DYNPM_ACTION_DOWNCLOCK:
 215                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 216                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 217                                 rdev->pm.dynpm_can_downclock = false;
 218                         } else {
 219                                 if (rdev->pm.active_crtc_count > 1) {
 220                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 221                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 222                                                         continue;
 223                                                 else if (i >= rdev->pm.current_power_state_index) {
 224                                                         rdev->pm.requested_power_state_index =
 225                                                                 rdev->pm.current_power_state_index;
 226                                                         break;
 227                                                 } else {
 228                                                         rdev->pm.requested_power_state_index = i;
 229                                                         break;
 230                                                 }
 231                                         }
 232                                 } else {
 233                                         if (rdev->pm.current_power_state_index == 0)
 234                                                 rdev->pm.requested_power_state_index =
 235                                                         rdev->pm.num_power_states - 1;
 236                                         else
 237                                                 rdev->pm.requested_power_state_index =
 238                                                         rdev->pm.current_power_state_index - 1;
 239                                 }
 240                         }
 241                         rdev->pm.requested_clock_mode_index = 0;
 242                         /* don't use the power state if crtcs are active and no display flag is set */
 243                         if ((rdev->pm.active_crtc_count > 0) &&
 244                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 245                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 246                              RADEON_PM_MODE_NO_DISPLAY)) {
 247                                 rdev->pm.requested_power_state_index++;
 248                         }
 249                         break;
 250                 case DYNPM_ACTION_UPCLOCK:
 251                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 252                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 253                                 rdev->pm.dynpm_can_upclock = false;
 254                         } else {
 255                                 if (rdev->pm.active_crtc_count > 1) {
 256                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 257                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 258                                                         continue;
 259                                                 else if (i <= rdev->pm.current_power_state_index) {
 260                                                         rdev->pm.requested_power_state_index =
 261                                                                 rdev->pm.current_power_state_index;
 262                                                         break;
 263                                                 } else {
 264                                                         rdev->pm.requested_power_state_index = i;
 265                                                         break;
 266                                                 }
 267                                         }
 268                                 } else
 269                                         rdev->pm.requested_power_state_index =
 270                                                 rdev->pm.current_power_state_index + 1;
 271                         }
 272                         rdev->pm.requested_clock_mode_index = 0;
 273                         break;
 274                 case DYNPM_ACTION_DEFAULT:
 275                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 276                         rdev->pm.requested_clock_mode_index = 0;
 277                         rdev->pm.dynpm_can_upclock = false;
 278                         break;
 279                 case DYNPM_ACTION_NONE:
 280                 default:
 281                         DRM_ERROR("Requested mode for not defined action\n");
 282                         return;
 283                 }
 284         } else {
 285                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 286                 /* for now just select the first power state and switch between clock modes */
 287                 /* power state array is low to high, default is first (0) */
 288                 if (rdev->pm.active_crtc_count > 1) {
 289                         rdev->pm.requested_power_state_index = -1;
 290                         /* start at 1 as we don't want the default mode */
 291                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 292                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 293                                         continue;
 294                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 295                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 296                                         rdev->pm.requested_power_state_index = i;
 297                                         break;
 298                                 }
 299                         }
 300                         /* if nothing selected, grab the default state. */
 301                         if (rdev->pm.requested_power_state_index == -1)
 302                                 rdev->pm.requested_power_state_index = 0;
 303                 } else
 304                         rdev->pm.requested_power_state_index = 1;
 305
 306                 switch (rdev->pm.dynpm_planned_action) {
 307                 case DYNPM_ACTION_MINIMUM:
 308                         rdev->pm.requested_clock_mode_index = 0;
 309                         rdev->pm.dynpm_can_downclock = false;
 310                         break;
 311                 case DYNPM_ACTION_DOWNCLOCK:
 312                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 313                                 if (rdev->pm.current_clock_mode_index == 0) {
 314                                         rdev->pm.requested_clock_mode_index = 0;
 315                                         rdev->pm.dynpm_can_downclock = false;
 316                                 } else
 317                                         rdev->pm.requested_clock_mode_index =
 318                                                 rdev->pm.current_clock_mode_index - 1;
 319                         } else {
 320                                 rdev->pm.requested_clock_mode_index = 0;
 321                                 rdev->pm.dynpm_can_downclock = false;
 322                         }
 323                         /* don't use the power state if crtcs are active and no display flag is set */
 324                         if ((rdev->pm.active_crtc_count > 0) &&
 325                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 326                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 327                              RADEON_PM_MODE_NO_DISPLAY)) {
 328                                 rdev->pm.requested_clock_mode_index++;
 329                         }
 330                         break;
 331                 case DYNPM_ACTION_UPCLOCK:
 332                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 333                                 if (rdev->pm.current_clock_mode_index ==
 334                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 335                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 336                                         rdev->pm.dynpm_can_upclock = false;
 337                                 } else
 338                                         rdev->pm.requested_clock_mode_index =
 339                                                 rdev->pm.current_clock_mode_index + 1;
 340                         } else {
 341                                 rdev->pm.requested_clock_mode_index =
 342                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 343                                 rdev->pm.dynpm_can_upclock = false;
 344                         }
 345                         break;
 346                 case DYNPM_ACTION_DEFAULT:
 347                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 348                         rdev->pm.requested_clock_mode_index = 0;
 349                         rdev->pm.dynpm_can_upclock = false;
 350                         break;
 351                 case DYNPM_ACTION_NONE:
 352                 default:
 353                         DRM_ERROR("Requested mode for not defined action\n");
 354                         return;
 355                 }
 356         }
 357
 358         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 359                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 360                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 361                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 362                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 363                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 364                   pcie_lanes);
 365 }
 366
 367 void rs780_pm_init_profile(struct radeon_device *rdev)
 368 {
 369         if (rdev->pm.num_power_states == 2) {
 370                 /* default */
 371                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 372                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 373                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 374                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 375                 /* low sh */
 376                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 377                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 378                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 379                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 380                 /* mid sh */
 381                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 382                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 383                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 384                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 385                 /* high sh */
 386                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 388                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 389                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 390                 /* low mh */
 391                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 392                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 393                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 394                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 395                 /* mid mh */
 396                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 397                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 398                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 399                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 400                 /* high mh */
 401                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 403                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 404                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 405         } else if (rdev->pm.num_power_states == 3) {
 406                 /* default */
 407                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 408                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 409                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 410                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 411                 /* low sh */
 412                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 413                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 414                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 415                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 416                 /* mid sh */
 417                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 418                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 419                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 420                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 421                 /* high sh */
 422                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 423                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 424                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 426                 /* low mh */
 427                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 428                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 429                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 431                 /* mid mh */
 432                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 433                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 434                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 436                 /* high mh */
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 438                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 439                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 441         } else {
 442                 /* default */
 443                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 445                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 446                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 447                 /* low sh */
 448                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 449                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 450                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 451                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 452                 /* mid sh */
 453                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 454                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 455                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 456                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 457                 /* high sh */
 458                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 459                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 460                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 461                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 462                 /* low mh */
 463                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 464                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 465                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 466                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 467                 /* mid mh */
 468                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 469                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 470                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 471                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 472                 /* high mh */
 473                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 474                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 475                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 476                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 477         }
 478 }
 479
 480 void r600_pm_init_profile(struct radeon_device *rdev)
 481 {
 482         int idx;
 483
 484         if (rdev->family == CHIP_R600) {
 485                 /* XXX */
 486                 /* default */
 487                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 488                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 489                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 490                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 491                 /* low sh */
 492                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 493                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 494                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 495                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 496                 /* mid sh */
 497                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 498                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 499                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 500                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 501                 /* high sh */
 502                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 503                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 504                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 505                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 506                 /* low mh */
 507                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 508                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 509                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 510                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 511                 /* mid mh */
 512                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 513                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 514                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 515                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 516                 /* high mh */
 517                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 518                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 519                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 520                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 521         } else {
 522                 if (rdev->pm.num_power_states < 4) {
 523                         /* default */
 524                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 525                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 526                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 527                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 528                         /* low sh */
 529                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 530                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 531                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 532                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 533                         /* mid sh */
 534                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 535                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 536                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 537                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 538                         /* high sh */
 539                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 540                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 541                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 542                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 543                         /* low mh */
 544                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 545                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 546                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 547                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 548                         /* low mh */
 549                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 550                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 551                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 552                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 553                         /* high mh */
 554                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 555                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 556                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 557                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 558                 } else {
 559                         /* default */
 560                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 561                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 562                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 563                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 564                         /* low sh */
 565                         if (rdev->flags & RADEON_IS_MOBILITY)
 566                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 567                         else
 568                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 569                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 570                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 571                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 572                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 573                         /* mid sh */
 574                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 575                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 576                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 577                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 578                         /* high sh */
 579                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 580                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 581                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 582                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 583                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 584                         /* low mh */
 585                         if (rdev->flags & RADEON_IS_MOBILITY)
 586                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 587                         else
 588                                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 589                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 590                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 591                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 592                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 593                         /* mid mh */
 594                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 595                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 596                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 597                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 598                         /* high mh */
 599                         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 600                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 601                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 602                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 603                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 604                 }
 605         }
 606 }
 607
 608 void r600_pm_misc(struct radeon_device *rdev)
 609 {
 610         int req_ps_idx = rdev->pm.requested_power_state_index;
 611         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 612         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 613         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 614
 615         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 616                 /* 0xff01 is a flag rather then an actual voltage */
 617                 if (voltage->voltage == 0xff01)
 618                         return;
 619                 if (voltage->voltage != rdev->pm.current_vddc) {
 620                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 621                         rdev->pm.current_vddc = voltage->voltage;
 622                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 623                 }
 624         }
 625 }
 626
 627 bool r600_gui_idle(struct radeon_device *rdev)
 628 {
 629         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 630                 return false;
 631         else
 632                 return true;
 633 }
 634
 635 /* hpd for digital panel detect/disconnect */
 636 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 637 {
 638         bool connected = false;
 639
 640         if (ASIC_IS_DCE3(rdev)) {
 641                 switch (hpd) {
 642                 case RADEON_HPD_1:
 643                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 644                                 connected = true;
 645                         break;
 646                 case RADEON_HPD_2:
 647                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 648                                 connected = true;
 649                         break;
 650                 case RADEON_HPD_3:
 651                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 652                                 connected = true;
 653                         break;
 654                 case RADEON_HPD_4:
 655                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 656                                 connected = true;
 657                         break;
 658                         /* DCE 3.2 */
 659                 case RADEON_HPD_5:
 660                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 661                                 connected = true;
 662                         break;
 663                 case RADEON_HPD_6:
 664                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 665                                 connected = true;
 666                         break;
 667                 default:
 668                         break;
 669                 }
 670         } else {
 671                 switch (hpd) {
 672                 case RADEON_HPD_1:
 673                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 674                                 connected = true;
 675                         break;
 676                 case RADEON_HPD_2:
 677                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 678                                 connected = true;
 679                         break;
 680                 case RADEON_HPD_3:
 681                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 682                                 connected = true;
 683                         break;
 684                 default:
 685                         break;
 686                 }
 687         }
 688         return connected;
 689 }
 690
 691 void r600_hpd_set_polarity(struct radeon_device *rdev,
 692                            enum radeon_hpd_id hpd)
 693 {
 694         u32 tmp;
 695         bool connected = r600_hpd_sense(rdev, hpd);
 696
 697         if (ASIC_IS_DCE3(rdev)) {
 698                 switch (hpd) {
 699                 case RADEON_HPD_1:
 700                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 701                         if (connected)
 702                                 tmp &= ~DC_HPDx_INT_POLARITY;
 703                         else
 704                                 tmp |= DC_HPDx_INT_POLARITY;
 705                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 706                         break;
 707                 case RADEON_HPD_2:
 708                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 709                         if (connected)
 710                                 tmp &= ~DC_HPDx_INT_POLARITY;
 711                         else
 712                                 tmp |= DC_HPDx_INT_POLARITY;
 713                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 714                         break;
 715                 case RADEON_HPD_3:
 716                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 717                         if (connected)
 718                                 tmp &= ~DC_HPDx_INT_POLARITY;
 719                         else
 720                                 tmp |= DC_HPDx_INT_POLARITY;
 721                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 722                         break;
 723                 case RADEON_HPD_4:
 724                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 725                         if (connected)
 726                                 tmp &= ~DC_HPDx_INT_POLARITY;
 727                         else
 728                                 tmp |= DC_HPDx_INT_POLARITY;
 729                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 730                         break;
 731                 case RADEON_HPD_5:
 732                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 733                         if (connected)
 734                                 tmp &= ~DC_HPDx_INT_POLARITY;
 735                         else
 736                                 tmp |= DC_HPDx_INT_POLARITY;
 737                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 738                         break;
 739                         /* DCE 3.2 */
 740                 case RADEON_HPD_6:
 741                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 742                         if (connected)
 743                                 tmp &= ~DC_HPDx_INT_POLARITY;
 744                         else
 745                                 tmp |= DC_HPDx_INT_POLARITY;
 746                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 747                         break;
 748                 default:
 749                         break;
 750                 }
 751         } else {
 752                 switch (hpd) {
 753                 case RADEON_HPD_1:
 754                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 755                         if (connected)
 756                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 757                         else
 758                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 759                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 760                         break;
 761                 case RADEON_HPD_2:
 762                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 763                         if (connected)
 764                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 765                         else
 766                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 767                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 768                         break;
 769                 case RADEON_HPD_3:
 770                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 771                         if (connected)
 772                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 773                         else
 774                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 775                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 776                         break;
 777                 default:
 778                         break;
 779                 }
 780         }
 781 }
 782
 783 void r600_hpd_init(struct radeon_device *rdev)
 784 {
 785         struct drm_device *dev = rdev->ddev;
 786         struct drm_connector *connector;
 787         unsigned enable = 0;
 788
 789         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 790                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 791
 792                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
 793                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
 794                         /* don't try to enable hpd on eDP or LVDS avoid breaking the
 795                          * aux dp channel on imac and help (but not completely fix)
 796                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
 797                          */
 798                         continue;
 799                 }
 800                 if (ASIC_IS_DCE3(rdev)) {
 801                         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 802                         if (ASIC_IS_DCE32(rdev))
 803                                 tmp |= DC_HPDx_EN;
 804
 805                         switch (radeon_connector->hpd.hpd) {
 806                         case RADEON_HPD_1:
 807                                 WREG32(DC_HPD1_CONTROL, tmp);
 808                                 break;
 809                         case RADEON_HPD_2:
 810                                 WREG32(DC_HPD2_CONTROL, tmp);
 811                                 break;
 812                         case RADEON_HPD_3:
 813                                 WREG32(DC_HPD3_CONTROL, tmp);
 814                                 break;
 815                         case RADEON_HPD_4:
 816                                 WREG32(DC_HPD4_CONTROL, tmp);
 817                                 break;
 818                                 /* DCE 3.2 */
 819                         case RADEON_HPD_5:
 820                                 WREG32(DC_HPD5_CONTROL, tmp);
 821                                 break;
 822                         case RADEON_HPD_6:
 823                                 WREG32(DC_HPD6_CONTROL, tmp);
 824                                 break;
 825                         default:
 826                                 break;
 827                         }
 828                 } else {
 829                         switch (radeon_connector->hpd.hpd) {
 830                         case RADEON_HPD_1:
 831                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 832                                 break;
 833                         case RADEON_HPD_2:
 834                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 835                                 break;
 836                         case RADEON_HPD_3:
 837                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 838                                 break;
 839                         default:
 840                                 break;
 841                         }
 842                 }
 843                 enable |= 1 << radeon_connector->hpd.hpd;
 844                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 845         }
 846         radeon_irq_kms_enable_hpd(rdev, enable);
 847 }
 848
 849 void r600_hpd_fini(struct radeon_device *rdev)
 850 {
 851         struct drm_device *dev = rdev->ddev;
 852         struct drm_connector *connector;
 853         unsigned disable = 0;
 854
 855         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 856                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 857                 if (ASIC_IS_DCE3(rdev)) {
 858                         switch (radeon_connector->hpd.hpd) {
 859                         case RADEON_HPD_1:
 860                                 WREG32(DC_HPD1_CONTROL, 0);
 861                                 break;
 862                         case RADEON_HPD_2:
 863                                 WREG32(DC_HPD2_CONTROL, 0);
 864                                 break;
 865                         case RADEON_HPD_3:
 866                                 WREG32(DC_HPD3_CONTROL, 0);
 867                                 break;
 868                         case RADEON_HPD_4:
 869                                 WREG32(DC_HPD4_CONTROL, 0);
 870                                 break;
 871                                 /* DCE 3.2 */
 872                         case RADEON_HPD_5:
 873                                 WREG32(DC_HPD5_CONTROL, 0);
 874                                 break;
 875                         case RADEON_HPD_6:
 876                                 WREG32(DC_HPD6_CONTROL, 0);
 877                                 break;
 878                         default:
 879                                 break;
 880                         }
 881                 } else {
 882                         switch (radeon_connector->hpd.hpd) {
 883                         case RADEON_HPD_1:
 884                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 885                                 break;
 886                         case RADEON_HPD_2:
 887                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 888                                 break;
 889                         case RADEON_HPD_3:
 890                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 891                                 break;
 892                         default:
 893                                 break;
 894                         }
 895                 }
 896                 disable |= 1 << radeon_connector->hpd.hpd;
 897         }
 898         radeon_irq_kms_disable_hpd(rdev, disable);
 899 }
 900
 901 /*
 902  * R600 PCIE GART
 903  */
 904 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 905 {
 906         unsigned i;
 907         u32 tmp;
 908
 909         /* flush hdp cache so updates hit vram */
 910         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 911             !(rdev->flags & RADEON_IS_AGP)) {
 912                 void __iomem *ptr = (void *)rdev->gart.ptr;
 913                 u32 tmp;
 914
 915                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 916                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 917                  * This seems to cause problems on some AGP cards. Just use the old
 918                  * method for them.
 919                  */
 920                 WREG32(HDP_DEBUG1, 0);
 921                 tmp = readl((void __iomem *)ptr);
 922         } else
 923                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 924
 925         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 926         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 927         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 928         for (i = 0; i < rdev->usec_timeout; i++) {
 929                 /* read MC_STATUS */
 930                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 931                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 932                 if (tmp == 2) {
 933                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 934                         return;
 935                 }
 936                 if (tmp) {
 937                         return;
 938                 }
 939                 udelay(1);
 940         }
 941 }
 942
 943 int r600_pcie_gart_init(struct radeon_device *rdev)
 944 {
 945         int r;
 946
 947         if (rdev->gart.robj) {
 948                 WARN(1, "R600 PCIE GART already initialized\n");
 949                 return 0;
 950         }
 951         /* Initialize common gart structure */
 952         r = radeon_gart_init(rdev);
 953         if (r)
 954                 return r;
 955         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 956         return radeon_gart_table_vram_alloc(rdev);
 957 }
 958
 959 static int r600_pcie_gart_enable(struct radeon_device *rdev)
 960 {
 961         u32 tmp;
 962         int r, i;
 963
 964         if (rdev->gart.robj == NULL) {
 965                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 966                 return -EINVAL;
 967         }
 968         r = radeon_gart_table_vram_pin(rdev);
 969         if (r)
 970                 return r;
 971         radeon_gart_restore(rdev);
 972
 973         /* Setup L2 cache */
 974         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 975                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 976                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 977         WREG32(VM_L2_CNTL2, 0);
 978         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 979         /* Setup TLB control */
 980         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 981                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 982                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 983                 ENABLE_WAIT_L2_QUERY;
 984         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 986         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 987         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 988         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 989         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 990         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 991         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 992         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 993         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 994         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 995         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 996         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 997         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 998         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 999         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1000         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1001         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1002                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1003         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1004                         (u32)(rdev->dummy_page.addr >> 12));
1005         for (i = 1; i < 7; i++)
1006                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1007
1008         r600_pcie_gart_tlb_flush(rdev);
1009         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1010                  (unsigned)(rdev->mc.gtt_size >> 20),
1011                  (unsigned long long)rdev->gart.table_addr);
1012         rdev->gart.ready = true;
1013         return 0;
1014 }
1015
1016 static void r600_pcie_gart_disable(struct radeon_device *rdev)
1017 {
1018         u32 tmp;
1019         int i;
1020
1021         /* Disable all tables */
1022         for (i = 0; i < 7; i++)
1023                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1024
1025         /* Disable L2 cache */
1026         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1027                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1028         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1029         /* Setup L1 TLB control */
1030         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1031                 ENABLE_WAIT_L2_QUERY;
1032         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1033         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1034         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1035         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1036         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1037         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1038         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1039         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1040         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1041         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1042         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1043         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1044         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1045         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1046         radeon_gart_table_vram_unpin(rdev);
1047 }
1048
1049 static void r600_pcie_gart_fini(struct radeon_device *rdev)
1050 {
1051         radeon_gart_fini(rdev);
1052         r600_pcie_gart_disable(rdev);
1053         radeon_gart_table_vram_free(rdev);
1054 }
1055
1056 static void r600_agp_enable(struct radeon_device *rdev)
1057 {
1058         u32 tmp;
1059         int i;
1060
1061         /* Setup L2 cache */
1062         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1063                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1064                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1065         WREG32(VM_L2_CNTL2, 0);
1066         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1067         /* Setup TLB control */
1068         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1069                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1070                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1071                 ENABLE_WAIT_L2_QUERY;
1072         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1073         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1074         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1075         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1076         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1077         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1078         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1079         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1080         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1081         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1082         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1083         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1084         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1085         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1086         for (i = 0; i < 7; i++)
1087                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1088 }
1089
1090 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1091 {
1092         unsigned i;
1093         u32 tmp;
1094
1095         for (i = 0; i < rdev->usec_timeout; i++) {
1096                 /* read MC_STATUS */
1097                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1098                 if (!tmp)
1099                         return 0;
1100                 udelay(1);
1101         }
1102         return -1;
1103 }
1104
1105 uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1106 {
1107         unsigned long flags;
1108         uint32_t r;
1109
1110         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1111         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1112         r = RREG32(R_0028FC_MC_DATA);
1113         WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1114         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1115         return r;
1116 }
1117
1118 void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1119 {
1120         unsigned long flags;
1121
1122         spin_lock_irqsave(&rdev->mc_idx_lock, flags);
1123         WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1124                 S_0028F8_MC_IND_WR_EN(1));
1125         WREG32(R_0028FC_MC_DATA, v);
1126         WREG32(R_0028F8_MC_INDEX, 0x7F);
1127         spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
1128 }
1129
1130 static void r600_mc_program(struct radeon_device *rdev)
1131 {
1132         struct rv515_mc_save save;
1133         u32 tmp;
1134         int i, j;
1135
1136         /* Initialize HDP */
1137         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1138                 WREG32((0x2c14 + j), 0x00000000);
1139                 WREG32((0x2c18 + j), 0x00000000);
1140                 WREG32((0x2c1c + j), 0x00000000);
1141                 WREG32((0x2c20 + j), 0x00000000);
1142                 WREG32((0x2c24 + j), 0x00000000);
1143         }
1144         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1145
1146         rv515_mc_stop(rdev, &save);
1147         if (r600_mc_wait_for_idle(rdev)) {
1148                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1149         }
1150         /* Lockout access through VGA aperture (doesn't exist before R600) */
1151         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1152         /* Update configuration */
1153         if (rdev->flags & RADEON_IS_AGP) {
1154                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1155                         /* VRAM before AGP */
1156                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1157                                 rdev->mc.vram_start >> 12);
1158                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1159                                 rdev->mc.gtt_end >> 12);
1160                 } else {
1161                         /* VRAM after AGP */
1162                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1163                                 rdev->mc.gtt_start >> 12);
1164                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1165                                 rdev->mc.vram_end >> 12);
1166                 }
1167         } else {
1168                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1169                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1170         }
1171         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1172         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1173         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1174         WREG32(MC_VM_FB_LOCATION, tmp);
1175         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1176         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1177         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1178         if (rdev->flags & RADEON_IS_AGP) {
1179                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1180                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1181                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1182         } else {
1183                 WREG32(MC_VM_AGP_BASE, 0);
1184                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1185                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1186         }
1187         if (r600_mc_wait_for_idle(rdev)) {
1188                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1189         }
1190         rv515_mc_resume(rdev, &save);
1191         /* we need to own VRAM, so turn off the VGA renderer here
1192          * to stop it overwriting our objects */
1193         rv515_vga_render_disable(rdev);
1194 }
1195
1196 /**
1197  * r600_vram_gtt_location - try to find VRAM & GTT location
1198  * @rdev: radeon device structure holding all necessary informations
1199  * @mc: memory controller structure holding memory informations
1200  *
1201  * Function will place try to place VRAM at same place as in CPU (PCI)
1202  * address space as some GPU seems to have issue when we reprogram at
1203  * different address space.
1204  *
1205  * If there is not enough space to fit the unvisible VRAM after the
1206  * aperture then we limit the VRAM size to the aperture.
1207  *
1208  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1209  * them to be in one from GPU point of view so that we can program GPU to
1210  * catch access outside them (weird GPU policy see ??).
1211  *
1212  * This function will never fails, worst case are limiting VRAM or GTT.
1213  *
1214  * Note: GTT start, end, size should be initialized before calling this
1215  * function on AGP platform.
1216  */
1217 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1218 {
1219         u64 size_bf, size_af;
1220
1221         if (mc->mc_vram_size > 0xE0000000) {
1222                 /* leave room for at least 512M GTT */
1223                 dev_warn(rdev->dev, "limiting VRAM\n");
1224                 mc->real_vram_size = 0xE0000000;
1225                 mc->mc_vram_size = 0xE0000000;
1226         }
1227         if (rdev->flags & RADEON_IS_AGP) {
1228                 size_bf = mc->gtt_start;
1229                 size_af = mc->mc_mask - mc->gtt_end;
1230                 if (size_bf > size_af) {
1231                         if (mc->mc_vram_size > size_bf) {
1232                                 dev_warn(rdev->dev, "limiting VRAM\n");
1233                                 mc->real_vram_size = size_bf;
1234                                 mc->mc_vram_size = size_bf;
1235                         }
1236                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1237                 } else {
1238                         if (mc->mc_vram_size > size_af) {
1239                                 dev_warn(rdev->dev, "limiting VRAM\n");
1240                                 mc->real_vram_size = size_af;
1241                                 mc->mc_vram_size = size_af;
1242                         }
1243                         mc->vram_start = mc->gtt_end + 1;
1244                 }
1245                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1246                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1247                                 mc->mc_vram_size >> 20, mc->vram_start,
1248                                 mc->vram_end, mc->real_vram_size >> 20);
1249         } else {
1250                 u64 base = 0;
1251                 if (rdev->flags & RADEON_IS_IGP) {
1252                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1253                         base <<= 24;
1254                 }
1255                 radeon_vram_location(rdev, &rdev->mc, base);
1256                 rdev->mc.gtt_base_align = 0;
1257                 radeon_gtt_location(rdev, mc);
1258         }
1259 }
1260
1261 static int r600_mc_init(struct radeon_device *rdev)
1262 {
1263         u32 tmp;
1264         int chansize, numchan;
1265         uint32_t h_addr, l_addr;
1266         unsigned long long k8_addr;
1267
1268         /* Get VRAM informations */
1269         rdev->mc.vram_is_ddr = true;
1270         tmp = RREG32(RAMCFG);
1271         if (tmp & CHANSIZE_OVERRIDE) {
1272                 chansize = 16;
1273         } else if (tmp & CHANSIZE_MASK) {
1274                 chansize = 64;
1275         } else {
1276                 chansize = 32;
1277         }
1278         tmp = RREG32(CHMAP);
1279         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1280         case 0:
1281         default:
1282                 numchan = 1;
1283                 break;
1284         case 1:
1285                 numchan = 2;
1286                 break;
1287         case 2:
1288                 numchan = 4;
1289                 break;
1290         case 3:
1291                 numchan = 8;
1292                 break;
1293         }
1294         rdev->mc.vram_width = numchan * chansize;
1295         /* Could aper size report 0 ? */
1296         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1297         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1298         /* Setup GPU memory space */
1299         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1300         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1301         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1302         r600_vram_gtt_location(rdev, &rdev->mc);
1303
1304         if (rdev->flags & RADEON_IS_IGP) {
1305                 rs690_pm_info(rdev);
1306                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1307
1308                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1309                         /* Use K8 direct mapping for fast fb access. */
1310                         rdev->fastfb_working = false;
1311                         h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1312                         l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1313                         k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1314 #if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1315                         if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1316 #endif
1317                         {
1318                                 /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1319                                 * memory is present.
1320                                 */
1321                                 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1322                                         DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1323                                                 (unsigned long long)rdev->mc.aper_base, k8_addr);
1324                                         rdev->mc.aper_base = (resource_size_t)k8_addr;
1325                                         rdev->fastfb_working = true;
1326                                 }
1327                         }
1328                 }
1329         }
1330
1331         radeon_update_bandwidth_info(rdev);
1332         return 0;
1333 }
1334
1335 int r600_vram_scratch_init(struct radeon_device *rdev)
1336 {
1337         int r;
1338
1339         if (rdev->vram_scratch.robj == NULL) {
1340                 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
1341                                      PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
1342                                      NULL, &rdev->vram_scratch.robj);
1343                 if (r) {
1344                         return r;
1345                 }
1346         }
1347
1348         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1349         if (unlikely(r != 0))
1350                 return r;
1351         r = radeon_bo_pin(rdev->vram_scratch.robj,
1352                           RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr);
1353         if (r) {
1354                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1355                 return r;
1356         }
1357         r = radeon_bo_kmap(rdev->vram_scratch.robj,
1358                                 (void **)&rdev->vram_scratch.ptr);
1359         if (r)
1360                 radeon_bo_unpin(rdev->vram_scratch.robj);
1361         radeon_bo_unreserve(rdev->vram_scratch.robj);
1362
1363         return r;
1364 }
1365
1366 void r600_vram_scratch_fini(struct radeon_device *rdev)
1367 {
1368         int r;
1369
1370         if (rdev->vram_scratch.robj == NULL) {
1371                 return;
1372         }
1373         r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
1374         if (likely(r == 0)) {
1375                 radeon_bo_kunmap(rdev->vram_scratch.robj);
1376                 radeon_bo_unpin(rdev->vram_scratch.robj);
1377                 radeon_bo_unreserve(rdev->vram_scratch.robj);
1378         }
1379         radeon_bo_unref(&rdev->vram_scratch.robj);
1380 }
1381
1382 void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1383 {
1384         u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1385
1386         if (hung)
1387                 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1388         else
1389                 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1390
1391         WREG32(R600_BIOS_3_SCRATCH, tmp);
1392 }
1393
1394 static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1395 {
1396         dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
1397                  RREG32(R_008010_GRBM_STATUS));
1398         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
1399                  RREG32(R_008014_GRBM_STATUS2));
1400         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
1401                  RREG32(R_000E50_SRBM_STATUS));
1402         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1403                  RREG32(CP_STALLED_STAT1));
1404         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1405                  RREG32(CP_STALLED_STAT2));
1406         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
1407                  RREG32(CP_BUSY_STAT));
1408         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
1409                  RREG32(CP_STAT));
1410         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
1411                 RREG32(DMA_STATUS_REG));
1412 }
1413
1414 static bool r600_is_display_hung(struct radeon_device *rdev)
1415 {
1416         u32 crtc_hung = 0;
1417         u32 crtc_status[2];
1418         u32 i, j, tmp;
1419
1420         for (i = 0; i < rdev->num_crtc; i++) {
1421                 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1422                         crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1423                         crtc_hung |= (1 << i);
1424                 }
1425         }
1426
1427         for (j = 0; j < 10; j++) {
1428                 for (i = 0; i < rdev->num_crtc; i++) {
1429                         if (crtc_hung & (1 << i)) {
1430                                 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1431                                 if (tmp != crtc_status[i])
1432                                         crtc_hung &= ~(1 << i);
1433                         }
1434                 }
1435                 if (crtc_hung == 0)
1436                         return false;
1437                 udelay(100);
1438         }
1439
1440         return true;
1441 }
1442
1443 u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1444 {
1445         u32 reset_mask = 0;
1446         u32 tmp;
1447
1448         /* GRBM_STATUS */
1449         tmp = RREG32(R_008010_GRBM_STATUS);
1450         if (rdev->family >= CHIP_RV770) {
1451                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1452                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1453                     G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1454                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1455                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1456                         reset_mask |= RADEON_RESET_GFX;
1457         } else {
1458                 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1459                     G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1460                     G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1461                     G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1462                     G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1463                         reset_mask |= RADEON_RESET_GFX;
1464         }
1465
1466         if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1467             G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1468                 reset_mask |= RADEON_RESET_CP;
1469
1470         if (G_008010_GRBM_EE_BUSY(tmp))
1471                 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1472
1473         /* DMA_STATUS_REG */
1474         tmp = RREG32(DMA_STATUS_REG);
1475         if (!(tmp & DMA_IDLE))
1476                 reset_mask |= RADEON_RESET_DMA;
1477
1478         /* SRBM_STATUS */
1479         tmp = RREG32(R_000E50_SRBM_STATUS);
1480         if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1481                 reset_mask |= RADEON_RESET_RLC;
1482
1483         if (G_000E50_IH_BUSY(tmp))
1484                 reset_mask |= RADEON_RESET_IH;
1485
1486         if (G_000E50_SEM_BUSY(tmp))
1487                 reset_mask |= RADEON_RESET_SEM;
1488
1489         if (G_000E50_GRBM_RQ_PENDING(tmp))
1490                 reset_mask |= RADEON_RESET_GRBM;
1491
1492         if (G_000E50_VMC_BUSY(tmp))
1493                 reset_mask |= RADEON_RESET_VMC;
1494
1495         if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1496             G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1497             G_000E50_MCDW_BUSY(tmp))
1498                 reset_mask |= RADEON_RESET_MC;
1499
1500         if (r600_is_display_hung(rdev))
1501                 reset_mask |= RADEON_RESET_DISPLAY;
1502
1503         /* Skip MC reset as it's mostly likely not hung, just busy */
1504         if (reset_mask & RADEON_RESET_MC) {
1505                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1506                 reset_mask &= ~RADEON_RESET_MC;
1507         }
1508
1509         return reset_mask;
1510 }
1511
1512 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1513 {
1514         struct rv515_mc_save save;
1515         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1516         u32 tmp;
1517
1518         if (reset_mask == 0)
1519                 return;
1520
1521         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1522
1523         r600_print_gpu_status_regs(rdev);
1524
1525         /* Disable CP parsing/prefetching */
1526         if (rdev->family >= CHIP_RV770)
1527                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1528         else
1529                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1530
1531         /* disable the RLC */
1532         WREG32(RLC_CNTL, 0);
1533
1534         if (reset_mask & RADEON_RESET_DMA) {
1535                 /* Disable DMA */
1536                 tmp = RREG32(DMA_RB_CNTL);
1537                 tmp &= ~DMA_RB_ENABLE;
1538                 WREG32(DMA_RB_CNTL, tmp);
1539         }
1540
1541         mdelay(50);
1542
1543         rv515_mc_stop(rdev, &save);
1544         if (r600_mc_wait_for_idle(rdev)) {
1545                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1546         }
1547
1548         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1549                 if (rdev->family >= CHIP_RV770)
1550                         grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1551                                 S_008020_SOFT_RESET_CB(1) |
1552                                 S_008020_SOFT_RESET_PA(1) |
1553                                 S_008020_SOFT_RESET_SC(1) |
1554                                 S_008020_SOFT_RESET_SPI(1) |
1555                                 S_008020_SOFT_RESET_SX(1) |
1556                                 S_008020_SOFT_RESET_SH(1) |
1557                                 S_008020_SOFT_RESET_TC(1) |
1558                                 S_008020_SOFT_RESET_TA(1) |
1559                                 S_008020_SOFT_RESET_VC(1) |
1560                                 S_008020_SOFT_RESET_VGT(1);
1561                 else
1562                         grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1563                                 S_008020_SOFT_RESET_DB(1) |
1564                                 S_008020_SOFT_RESET_CB(1) |
1565                                 S_008020_SOFT_RESET_PA(1) |
1566                                 S_008020_SOFT_RESET_SC(1) |
1567                                 S_008020_SOFT_RESET_SMX(1) |
1568                                 S_008020_SOFT_RESET_SPI(1) |
1569                                 S_008020_SOFT_RESET_SX(1) |
1570                                 S_008020_SOFT_RESET_SH(1) |
1571                                 S_008020_SOFT_RESET_TC(1) |
1572                                 S_008020_SOFT_RESET_TA(1) |
1573                                 S_008020_SOFT_RESET_VC(1) |
1574                                 S_008020_SOFT_RESET_VGT(1);
1575         }
1576
1577         if (reset_mask & RADEON_RESET_CP) {
1578                 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1579                         S_008020_SOFT_RESET_VGT(1);
1580
1581                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1582         }
1583
1584         if (reset_mask & RADEON_RESET_DMA) {
1585                 if (rdev->family >= CHIP_RV770)
1586                         srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1587                 else
1588                         srbm_soft_reset |= SOFT_RESET_DMA;
1589         }
1590
1591         if (reset_mask & RADEON_RESET_RLC)
1592                 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1593
1594         if (reset_mask & RADEON_RESET_SEM)
1595                 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1596
1597         if (reset_mask & RADEON_RESET_IH)
1598                 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1599
1600         if (reset_mask & RADEON_RESET_GRBM)
1601                 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1602
1603         if (!(rdev->flags & RADEON_IS_IGP)) {
1604                 if (reset_mask & RADEON_RESET_MC)
1605                         srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1606         }
1607
1608         if (reset_mask & RADEON_RESET_VMC)
1609                 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1610
1611         if (grbm_soft_reset) {
1612                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1613                 tmp |= grbm_soft_reset;
1614                 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1615                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1616                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1617
1618                 udelay(50);
1619
1620                 tmp &= ~grbm_soft_reset;
1621                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1622                 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1623         }
1624
1625         if (srbm_soft_reset) {
1626                 tmp = RREG32(SRBM_SOFT_RESET);
1627                 tmp |= srbm_soft_reset;
1628                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1629                 WREG32(SRBM_SOFT_RESET, tmp);
1630                 tmp = RREG32(SRBM_SOFT_RESET);
1631
1632                 udelay(50);
1633
1634                 tmp &= ~srbm_soft_reset;
1635                 WREG32(SRBM_SOFT_RESET, tmp);
1636                 tmp = RREG32(SRBM_SOFT_RESET);
1637         }
1638
1639         /* Wait a little for things to settle down */
1640         mdelay(1);
1641
1642         rv515_mc_resume(rdev, &save);
1643         udelay(50);
1644
1645         r600_print_gpu_status_regs(rdev);
1646 }
1647
1648 static void r600_gpu_pci_config_reset(struct radeon_device *rdev)
1649 {
1650         struct rv515_mc_save save;
1651         u32 tmp, i;
1652
1653         dev_info(rdev->dev, "GPU pci config reset\n");
1654
1655         /* disable dpm? */
1656
1657         /* Disable CP parsing/prefetching */
1658         if (rdev->family >= CHIP_RV770)
1659                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1660         else
1661                 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1662
1663         /* disable the RLC */
1664         WREG32(RLC_CNTL, 0);
1665
1666         /* Disable DMA */
1667         tmp = RREG32(DMA_RB_CNTL);
1668         tmp &= ~DMA_RB_ENABLE;
1669         WREG32(DMA_RB_CNTL, tmp);
1670
1671         mdelay(50);
1672
1673         /* set mclk/sclk to bypass */
1674         if (rdev->family >= CHIP_RV770)
1675                 rv770_set_clk_bypass_mode(rdev);
1676         /* disable BM */
1677         pci_clear_master(rdev->pdev);
1678         /* disable mem access */
1679         rv515_mc_stop(rdev, &save);
1680         if (r600_mc_wait_for_idle(rdev)) {
1681                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1682         }
1683
1684         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1685         tmp = RREG32(BUS_CNTL);
1686         tmp |= VGA_COHE_SPEC_TIMER_DIS;
1687         WREG32(BUS_CNTL, tmp);
1688
1689         tmp = RREG32(BIF_SCRATCH0);
1690
1691         /* reset */
1692         radeon_pci_config_reset(rdev);
1693         mdelay(1);
1694
1695         /* BIF reset workaround.  Not sure if this is needed on 6xx */
1696         tmp = SOFT_RESET_BIF;
1697         WREG32(SRBM_SOFT_RESET, tmp);
1698         mdelay(1);
1699         WREG32(SRBM_SOFT_RESET, 0);
1700
1701         /* wait for asic to come out of reset */
1702         for (i = 0; i < rdev->usec_timeout; i++) {
1703                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
1704                         break;
1705                 udelay(1);
1706         }
1707 }
1708
1709 int r600_asic_reset(struct radeon_device *rdev)
1710 {
1711         u32 reset_mask;
1712
1713         reset_mask = r600_gpu_check_soft_reset(rdev);
1714
1715         if (reset_mask)
1716                 r600_set_bios_scratch_engine_hung(rdev, true);
1717
1718         /* try soft reset */
1719         r600_gpu_soft_reset(rdev, reset_mask);
1720
1721         reset_mask = r600_gpu_check_soft_reset(rdev);
1722
1723         /* try pci config reset */
1724         if (reset_mask && radeon_hard_reset)
1725                 r600_gpu_pci_config_reset(rdev);
1726
1727         reset_mask = r600_gpu_check_soft_reset(rdev);
1728
1729         if (!reset_mask)
1730                 r600_set_bios_scratch_engine_hung(rdev, false);
1731
1732         return 0;
1733 }
1734
1735 /**
1736  * r600_gfx_is_lockup - Check if the GFX engine is locked up
1737  *
1738  * @rdev: radeon_device pointer
1739  * @ring: radeon_ring structure holding ring information
1740  *
1741  * Check if the GFX engine is locked up.
1742  * Returns true if the engine appears to be locked up, false if not.
1743  */
1744 bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1745 {
1746         u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1747
1748         if (!(reset_mask & (RADEON_RESET_GFX |
1749                             RADEON_RESET_COMPUTE |
1750                             RADEON_RESET_CP))) {
1751                 radeon_ring_lockup_update(rdev, ring);
1752                 return false;
1753         }
1754         return radeon_ring_test_lockup(rdev, ring);
1755 }
1756
1757 u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1758                               u32 tiling_pipe_num,
1759                               u32 max_rb_num,
1760                               u32 total_max_rb_num,
1761                               u32 disabled_rb_mask)
1762 {
1763         u32 rendering_pipe_num, rb_num_width, req_rb_num;
1764         u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1765         u32 data = 0, mask = 1 << (max_rb_num - 1);
1766         unsigned i, j;
1767
1768         /* mask out the RBs that don't exist on that asic */
1769         tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1770         /* make sure at least one RB is available */
1771         if ((tmp & 0xff) != 0xff)
1772                 disabled_rb_mask = tmp;
1773
1774         rendering_pipe_num = 1 << tiling_pipe_num;
1775         req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
1776         BUG_ON(rendering_pipe_num < req_rb_num);
1777
1778         pipe_rb_ratio = rendering_pipe_num / req_rb_num;
1779         pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
1780
1781         if (rdev->family <= CHIP_RV740) {
1782                 /* r6xx/r7xx */
1783                 rb_num_width = 2;
1784         } else {
1785                 /* eg+ */
1786                 rb_num_width = 4;
1787         }
1788
1789         for (i = 0; i < max_rb_num; i++) {
1790                 if (!(mask & disabled_rb_mask)) {
1791                         for (j = 0; j < pipe_rb_ratio; j++) {
1792                                 data <<= rb_num_width;
1793                                 data |= max_rb_num - i - 1;
1794                         }
1795                         if (pipe_rb_remain) {
1796                                 data <<= rb_num_width;
1797                                 data |= max_rb_num - i - 1;
1798                                 pipe_rb_remain--;
1799                         }
1800                 }
1801                 mask >>= 1;
1802         }
1803
1804         return data;
1805 }
1806
1807 int r600_count_pipe_bits(uint32_t val)
1808 {
1809         return hweight32(val);
1810 }
1811
1812 static void r600_gpu_init(struct radeon_device *rdev)
1813 {
1814         u32 tiling_config;
1815         u32 ramcfg;
1816         u32 cc_rb_backend_disable;
1817         u32 cc_gc_shader_pipe_config;
1818         u32 tmp;
1819         int i, j;
1820         u32 sq_config;
1821         u32 sq_gpr_resource_mgmt_1 = 0;
1822         u32 sq_gpr_resource_mgmt_2 = 0;
1823         u32 sq_thread_resource_mgmt = 0;
1824         u32 sq_stack_resource_mgmt_1 = 0;
1825         u32 sq_stack_resource_mgmt_2 = 0;
1826         u32 disabled_rb_mask;
1827
1828         rdev->config.r600.tiling_group_size = 256;
1829         switch (rdev->family) {
1830         case CHIP_R600:
1831                 rdev->config.r600.max_pipes = 4;
1832                 rdev->config.r600.max_tile_pipes = 8;
1833                 rdev->config.r600.max_simds = 4;
1834                 rdev->config.r600.max_backends = 4;
1835                 rdev->config.r600.max_gprs = 256;
1836                 rdev->config.r600.max_threads = 192;
1837                 rdev->config.r600.max_stack_entries = 256;
1838                 rdev->config.r600.max_hw_contexts = 8;
1839                 rdev->config.r600.max_gs_threads = 16;
1840                 rdev->config.r600.sx_max_export_size = 128;
1841                 rdev->config.r600.sx_max_export_pos_size = 16;
1842                 rdev->config.r600.sx_max_export_smx_size = 128;
1843                 rdev->config.r600.sq_num_cf_insts = 2;
1844                 break;
1845         case CHIP_RV630:
1846         case CHIP_RV635:
1847                 rdev->config.r600.max_pipes = 2;
1848                 rdev->config.r600.max_tile_pipes = 2;
1849                 rdev->config.r600.max_simds = 3;
1850                 rdev->config.r600.max_backends = 1;
1851                 rdev->config.r600.max_gprs = 128;
1852                 rdev->config.r600.max_threads = 192;
1853                 rdev->config.r600.max_stack_entries = 128;
1854                 rdev->config.r600.max_hw_contexts = 8;
1855                 rdev->config.r600.max_gs_threads = 4;
1856                 rdev->config.r600.sx_max_export_size = 128;
1857                 rdev->config.r600.sx_max_export_pos_size = 16;
1858                 rdev->config.r600.sx_max_export_smx_size = 128;
1859                 rdev->config.r600.sq_num_cf_insts = 2;
1860                 break;
1861         case CHIP_RV610:
1862         case CHIP_RV620:
1863         case CHIP_RS780:
1864         case CHIP_RS880:
1865                 rdev->config.r600.max_pipes = 1;
1866                 rdev->config.r600.max_tile_pipes = 1;
1867                 rdev->config.r600.max_simds = 2;
1868                 rdev->config.r600.max_backends = 1;
1869                 rdev->config.r600.max_gprs = 128;
1870                 rdev->config.r600.max_threads = 192;
1871                 rdev->config.r600.max_stack_entries = 128;
1872                 rdev->config.r600.max_hw_contexts = 4;
1873                 rdev->config.r600.max_gs_threads = 4;
1874                 rdev->config.r600.sx_max_export_size = 128;
1875                 rdev->config.r600.sx_max_export_pos_size = 16;
1876                 rdev->config.r600.sx_max_export_smx_size = 128;
1877                 rdev->config.r600.sq_num_cf_insts = 1;
1878                 break;
1879         case CHIP_RV670:
1880                 rdev->config.r600.max_pipes = 4;
1881                 rdev->config.r600.max_tile_pipes = 4;
1882                 rdev->config.r600.max_simds = 4;
1883                 rdev->config.r600.max_backends = 4;
1884                 rdev->config.r600.max_gprs = 192;
1885                 rdev->config.r600.max_threads = 192;
1886                 rdev->config.r600.max_stack_entries = 256;
1887                 rdev->config.r600.max_hw_contexts = 8;
1888                 rdev->config.r600.max_gs_threads = 16;
1889                 rdev->config.r600.sx_max_export_size = 128;
1890                 rdev->config.r600.sx_max_export_pos_size = 16;
1891                 rdev->config.r600.sx_max_export_smx_size = 128;
1892                 rdev->config.r600.sq_num_cf_insts = 2;
1893                 break;
1894         default:
1895                 break;
1896         }
1897
1898         /* Initialize HDP */
1899         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1900                 WREG32((0x2c14 + j), 0x00000000);
1901                 WREG32((0x2c18 + j), 0x00000000);
1902                 WREG32((0x2c1c + j), 0x00000000);
1903                 WREG32((0x2c20 + j), 0x00000000);
1904                 WREG32((0x2c24 + j), 0x00000000);
1905         }
1906
1907         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1908
1909         /* Setup tiling */
1910         tiling_config = 0;
1911         ramcfg = RREG32(RAMCFG);
1912         switch (rdev->config.r600.max_tile_pipes) {
1913         case 1:
1914                 tiling_config |= PIPE_TILING(0);
1915                 break;
1916         case 2:
1917                 tiling_config |= PIPE_TILING(1);
1918                 break;
1919         case 4:
1920                 tiling_config |= PIPE_TILING(2);
1921                 break;
1922         case 8:
1923                 tiling_config |= PIPE_TILING(3);
1924                 break;
1925         default:
1926                 break;
1927         }
1928         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1929         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1930         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1931         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1932
1933         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1934         if (tmp > 3) {
1935                 tiling_config |= ROW_TILING(3);
1936                 tiling_config |= SAMPLE_SPLIT(3);
1937         } else {
1938                 tiling_config |= ROW_TILING(tmp);
1939                 tiling_config |= SAMPLE_SPLIT(tmp);
1940         }
1941         tiling_config |= BANK_SWAPS(1);
1942
1943         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1944         tmp = R6XX_MAX_BACKENDS -
1945                 r600_count_pipe_bits((cc_rb_backend_disable >> 16) & R6XX_MAX_BACKENDS_MASK);
1946         if (tmp < rdev->config.r600.max_backends) {
1947                 rdev->config.r600.max_backends = tmp;
1948         }
1949
1950         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;
1951         tmp = R6XX_MAX_PIPES -
1952                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R6XX_MAX_PIPES_MASK);
1953         if (tmp < rdev->config.r600.max_pipes) {
1954                 rdev->config.r600.max_pipes = tmp;
1955         }
1956         tmp = R6XX_MAX_SIMDS -
1957                 r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R6XX_MAX_SIMDS_MASK);
1958         if (tmp < rdev->config.r600.max_simds) {
1959                 rdev->config.r600.max_simds = tmp;
1960         }
1961
1962         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;
1963         tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1964         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends,
1965                                         R6XX_MAX_BACKENDS, disabled_rb_mask);
1966         tiling_config |= tmp << 16;
1967         rdev->config.r600.backend_map = tmp;
1968
1969         rdev->config.r600.tile_config = tiling_config;
1970         WREG32(GB_TILING_CONFIG, tiling_config);
1971         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1972         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1973         WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff);
1974
1975         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1976         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1977         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1978
1979         /* Setup some CP states */
1980         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1981         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1982
1983         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1984                              SYNC_WALKER | SYNC_ALIGNER));
1985         /* Setup various GPU states */
1986         if (rdev->family == CHIP_RV670)
1987                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1988
1989         tmp = RREG32(SX_DEBUG_1);
1990         tmp |= SMX_EVENT_RELEASE;
1991         if ((rdev->family > CHIP_R600))
1992                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1993         WREG32(SX_DEBUG_1, tmp);
1994
1995         if (((rdev->family) == CHIP_R600) ||
1996             ((rdev->family) == CHIP_RV630) ||
1997             ((rdev->family) == CHIP_RV610) ||
1998             ((rdev->family) == CHIP_RV620) ||
1999             ((rdev->family) == CHIP_RS780) ||
2000             ((rdev->family) == CHIP_RS880)) {
2001                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
2002         } else {
2003                 WREG32(DB_DEBUG, 0);
2004         }
2005         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
2006                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
2007
2008         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2009         WREG32(VGT_NUM_INSTANCES, 0);
2010
2011         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
2012         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
2013
2014         tmp = RREG32(SQ_MS_FIFO_SIZES);
2015         if (((rdev->family) == CHIP_RV610) ||
2016             ((rdev->family) == CHIP_RV620) ||
2017             ((rdev->family) == CHIP_RS780) ||
2018             ((rdev->family) == CHIP_RS880)) {
2019                 tmp = (CACHE_FIFO_SIZE(0xa) |
2020                        FETCH_FIFO_HIWATER(0xa) |
2021                        DONE_FIFO_HIWATER(0xe0) |
2022                        ALU_UPDATE_FIFO_HIWATER(0x8));
2023         } else if (((rdev->family) == CHIP_R600) ||
2024                    ((rdev->family) == CHIP_RV630)) {
2025                 tmp &= ~DONE_FIFO_HIWATER(0xff);
2026                 tmp |= DONE_FIFO_HIWATER(0x4);
2027         }
2028         WREG32(SQ_MS_FIFO_SIZES, tmp);
2029
2030         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
2031          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
2032          */
2033         sq_config = RREG32(SQ_CONFIG);
2034         sq_config &= ~(PS_PRIO(3) |
2035                        VS_PRIO(3) |
2036                        GS_PRIO(3) |
2037                        ES_PRIO(3));
2038         sq_config |= (DX9_CONSTS |
2039                       VC_ENABLE |
2040                       PS_PRIO(0) |
2041                       VS_PRIO(1) |
2042                       GS_PRIO(2) |
2043                       ES_PRIO(3));
2044
2045         if ((rdev->family) == CHIP_R600) {
2046                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
2047                                           NUM_VS_GPRS(124) |
2048                                           NUM_CLAUSE_TEMP_GPRS(4));
2049                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
2050                                           NUM_ES_GPRS(0));
2051                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
2052                                            NUM_VS_THREADS(48) |
2053                                            NUM_GS_THREADS(4) |
2054                                            NUM_ES_THREADS(4));
2055                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
2056                                             NUM_VS_STACK_ENTRIES(128));
2057                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
2058                                             NUM_ES_STACK_ENTRIES(0));
2059         } else if (((rdev->family) == CHIP_RV610) ||
2060                    ((rdev->family) == CHIP_RV620) ||
2061                    ((rdev->family) == CHIP_RS780) ||
2062                    ((rdev->family) == CHIP_RS880)) {
2063                 /* no vertex cache */
2064                 sq_config &= ~VC_ENABLE;
2065
2066                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2067                                           NUM_VS_GPRS(44) |
2068                                           NUM_CLAUSE_TEMP_GPRS(2));
2069                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2070                                           NUM_ES_GPRS(17));
2071                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2072                                            NUM_VS_THREADS(78) |
2073                                            NUM_GS_THREADS(4) |
2074                                            NUM_ES_THREADS(31));
2075                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2076                                             NUM_VS_STACK_ENTRIES(40));
2077                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2078                                             NUM_ES_STACK_ENTRIES(16));
2079         } else if (((rdev->family) == CHIP_RV630) ||
2080                    ((rdev->family) == CHIP_RV635)) {
2081                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2082                                           NUM_VS_GPRS(44) |
2083                                           NUM_CLAUSE_TEMP_GPRS(2));
2084                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
2085                                           NUM_ES_GPRS(18));
2086                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2087                                            NUM_VS_THREADS(78) |
2088                                            NUM_GS_THREADS(4) |
2089                                            NUM_ES_THREADS(31));
2090                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
2091                                             NUM_VS_STACK_ENTRIES(40));
2092                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
2093                                             NUM_ES_STACK_ENTRIES(16));
2094         } else if ((rdev->family) == CHIP_RV670) {
2095                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
2096                                           NUM_VS_GPRS(44) |
2097                                           NUM_CLAUSE_TEMP_GPRS(2));
2098                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
2099                                           NUM_ES_GPRS(17));
2100                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
2101                                            NUM_VS_THREADS(78) |
2102                                            NUM_GS_THREADS(4) |
2103                                            NUM_ES_THREADS(31));
2104                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
2105                                             NUM_VS_STACK_ENTRIES(64));
2106                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
2107                                             NUM_ES_STACK_ENTRIES(64));
2108         }
2109
2110         WREG32(SQ_CONFIG, sq_config);
2111         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
2112         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
2113         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2114         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2115         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2116
2117         if (((rdev->family) == CHIP_RV610) ||
2118             ((rdev->family) == CHIP_RV620) ||
2119             ((rdev->family) == CHIP_RS780) ||
2120             ((rdev->family) == CHIP_RS880)) {
2121                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
2122         } else {
2123                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
2124         }
2125
2126         /* More default values. 2D/3D driver should adjust as needed */
2127         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
2128                                          S1_X(0x4) | S1_Y(0xc)));
2129         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
2130                                          S1_X(0x2) | S1_Y(0x2) |
2131                                          S2_X(0xa) | S2_Y(0x6) |
2132                                          S3_X(0x6) | S3_Y(0xa)));
2133         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
2134                                              S1_X(0x4) | S1_Y(0xc) |
2135                                              S2_X(0x1) | S2_Y(0x6) |
2136                                              S3_X(0xa) | S3_Y(0xe)));
2137         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
2138                                              S5_X(0x0) | S5_Y(0x0) |
2139                                              S6_X(0xb) | S6_Y(0x4) |
2140                                              S7_X(0x7) | S7_Y(0x8)));
2141
2142         WREG32(VGT_STRMOUT_EN, 0);
2143         tmp = rdev->config.r600.max_pipes * 16;
2144         switch (rdev->family) {
2145         case CHIP_RV610:
2146         case CHIP_RV620:
2147         case CHIP_RS780:
2148         case CHIP_RS880:
2149                 tmp += 32;
2150                 break;
2151         case CHIP_RV670:
2152                 tmp += 128;
2153                 break;
2154         default:
2155                 break;
2156         }
2157         if (tmp > 256) {
2158                 tmp = 256;
2159         }
2160         WREG32(VGT_ES_PER_GS, 128);
2161         WREG32(VGT_GS_PER_ES, tmp);
2162         WREG32(VGT_GS_PER_VS, 2);
2163         WREG32(VGT_GS_VERTEX_REUSE, 16);
2164
2165         /* more default values. 2D/3D driver should adjust as needed */
2166         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2167         WREG32(VGT_STRMOUT_EN, 0);
2168         WREG32(SX_MISC, 0);
2169         WREG32(PA_SC_MODE_CNTL, 0);
2170         WREG32(PA_SC_AA_CONFIG, 0);
2171         WREG32(PA_SC_LINE_STIPPLE, 0);
2172         WREG32(SPI_INPUT_Z, 0);
2173         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
2174         WREG32(CB_COLOR7_FRAG, 0);
2175
2176         /* Clear render buffer base addresses */
2177         WREG32(CB_COLOR0_BASE, 0);
2178         WREG32(CB_COLOR1_BASE, 0);
2179         WREG32(CB_COLOR2_BASE, 0);
2180         WREG32(CB_COLOR3_BASE, 0);
2181         WREG32(CB_COLOR4_BASE, 0);
2182         WREG32(CB_COLOR5_BASE, 0);
2183         WREG32(CB_COLOR6_BASE, 0);
2184         WREG32(CB_COLOR7_BASE, 0);
2185         WREG32(CB_COLOR7_FRAG, 0);
2186
2187         switch (rdev->family) {
2188         case CHIP_RV610:
2189         case CHIP_RV620:
2190         case CHIP_RS780:
2191         case CHIP_RS880:
2192                 tmp = TC_L2_SIZE(8);
2193                 break;
2194         case CHIP_RV630:
2195         case CHIP_RV635:
2196                 tmp = TC_L2_SIZE(4);
2197                 break;
2198         case CHIP_R600:
2199                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
2200                 break;
2201         default:
2202                 tmp = TC_L2_SIZE(0);
2203                 break;
2204         }
2205         WREG32(TC_CNTL, tmp);
2206
2207         tmp = RREG32(HDP_HOST_PATH_CNTL);
2208         WREG32(HDP_HOST_PATH_CNTL, tmp);
2209
2210         tmp = RREG32(ARB_POP);
2211         tmp |= ENABLE_TC128;
2212         WREG32(ARB_POP, tmp);
2213
2214         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
2215         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
2216                                NUM_CLIP_SEQ(3)));
2217         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
2218         WREG32(VC_ENHANCE, 0);
2219 }
2220
2221
2222 /*
2223  * Indirect registers accessor
2224  */
2225 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
2226 {
2227         unsigned long flags;
2228         u32 r;
2229
2230         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2231         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2232         (void)RREG32(PCIE_PORT_INDEX);
2233         r = RREG32(PCIE_PORT_DATA);
2234         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2235         return r;
2236 }
2237
2238 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
2239 {
2240         unsigned long flags;
2241
2242         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
2243         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
2244         (void)RREG32(PCIE_PORT_INDEX);
2245         WREG32(PCIE_PORT_DATA, (v));
2246         (void)RREG32(PCIE_PORT_DATA);
2247         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
2248 }
2249
2250 /*
2251  * CP & Ring
2252  */
2253 void r600_cp_stop(struct radeon_device *rdev)
2254 {
2255         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2256                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2257         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
2258         WREG32(SCRATCH_UMSK, 0);
2259         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
2260 }
2261
2262 int r600_init_microcode(struct radeon_device *rdev)
2263 {
2264         const char *chip_name;
2265         const char *rlc_chip_name;
2266         const char *smc_chip_name = "RV770";
2267         size_t pfp_req_size, me_req_size, rlc_req_size, smc_req_size = 0;
2268         char fw_name[30];
2269         int err;
2270
2271         DRM_DEBUG("\n");
2272
2273         switch (rdev->family) {
2274         case CHIP_R600:
2275                 chip_name = "R600";
2276                 rlc_chip_name = "R600";
2277                 break;
2278         case CHIP_RV610:
2279                 chip_name = "RV610";
2280                 rlc_chip_name = "R600";
2281                 break;
2282         case CHIP_RV630:
2283                 chip_name = "RV630";
2284                 rlc_chip_name = "R600";
2285                 break;
2286         case CHIP_RV620:
2287                 chip_name = "RV620";
2288                 rlc_chip_name = "R600";
2289                 break;
2290         case CHIP_RV635:
2291                 chip_name = "RV635";
2292                 rlc_chip_name = "R600";
2293                 break;
2294         case CHIP_RV670:
2295                 chip_name = "RV670";
2296                 rlc_chip_name = "R600";
2297                 break;
2298         case CHIP_RS780:
2299         case CHIP_RS880:
2300                 chip_name = "RS780";
2301                 rlc_chip_name = "R600";
2302                 break;
2303         case CHIP_RV770:
2304                 chip_name = "RV770";
2305                 rlc_chip_name = "R700";
2306                 smc_chip_name = "RV770";
2307                 smc_req_size = ALIGN(RV770_SMC_UCODE_SIZE, 4);
2308                 break;
2309         case CHIP_RV730:
2310                 chip_name = "RV730";
2311                 rlc_chip_name = "R700";
2312                 smc_chip_name = "RV730";
2313                 smc_req_size = ALIGN(RV730_SMC_UCODE_SIZE, 4);
2314                 break;
2315         case CHIP_RV710:
2316                 chip_name = "RV710";
2317                 rlc_chip_name = "R700";
2318                 smc_chip_name = "RV710";
2319                 smc_req_size = ALIGN(RV710_SMC_UCODE_SIZE, 4);
2320                 break;
2321         case CHIP_RV740:
2322                 chip_name = "RV730";
2323                 rlc_chip_name = "R700";
2324                 smc_chip_name = "RV740";
2325                 smc_req_size = ALIGN(RV740_SMC_UCODE_SIZE, 4);
2326                 break;
2327         case CHIP_CEDAR:
2328                 chip_name = "CEDAR";
2329                 rlc_chip_name = "CEDAR";
2330                 smc_chip_name = "CEDAR";
2331                 smc_req_size = ALIGN(CEDAR_SMC_UCODE_SIZE, 4);
2332                 break;
2333         case CHIP_REDWOOD:
2334                 chip_name = "REDWOOD";
2335                 rlc_chip_name = "REDWOOD";
2336                 smc_chip_name = "REDWOOD";
2337                 smc_req_size = ALIGN(REDWOOD_SMC_UCODE_SIZE, 4);
2338                 break;
2339         case CHIP_JUNIPER:
2340                 chip_name = "JUNIPER";
2341                 rlc_chip_name = "JUNIPER";
2342                 smc_chip_name = "JUNIPER";
2343                 smc_req_size = ALIGN(JUNIPER_SMC_UCODE_SIZE, 4);
2344                 break;
2345         case CHIP_CYPRESS:
2346         case CHIP_HEMLOCK:
2347                 chip_name = "CYPRESS";
2348                 rlc_chip_name = "CYPRESS";
2349                 smc_chip_name = "CYPRESS";
2350                 smc_req_size = ALIGN(CYPRESS_SMC_UCODE_SIZE, 4);
2351                 break;
2352         case CHIP_PALM:
2353                 chip_name = "PALM";
2354                 rlc_chip_name = "SUMO";
2355                 break;
2356         case CHIP_SUMO:
2357                 chip_name = "SUMO";
2358                 rlc_chip_name = "SUMO";
2359                 break;
2360         case CHIP_SUMO2:
2361                 chip_name = "SUMO2";
2362                 rlc_chip_name = "SUMO";
2363                 break;
2364         default: BUG();
2365         }
2366
2367         if (rdev->family >= CHIP_CEDAR) {
2368                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2369                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2370                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2371         } else if (rdev->family >= CHIP_RV770) {
2372                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2373                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2374                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2375         } else {
2376                 pfp_req_size = R600_PFP_UCODE_SIZE * 4;
2377                 me_req_size = R600_PM4_UCODE_SIZE * 12;
2378                 rlc_req_size = R600_RLC_UCODE_SIZE * 4;
2379         }
2380
2381         DRM_INFO("Loading %s Microcode\n", chip_name);
2382
2383         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2384         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
2385         if (err)
2386                 goto out;
2387         if (rdev->pfp_fw->size != pfp_req_size) {
2388                 printk(KERN_ERR
2389                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2390                        rdev->pfp_fw->size, fw_name);
2391                 err = -EINVAL;
2392                 goto out;
2393         }
2394
2395         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2396         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
2397         if (err)
2398                 goto out;
2399         if (rdev->me_fw->size != me_req_size) {
2400                 printk(KERN_ERR
2401                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2402                        rdev->me_fw->size, fw_name);
2403                 err = -EINVAL;
2404         }
2405
2406         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2407         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
2408         if (err)
2409                 goto out;
2410         if (rdev->rlc_fw->size != rlc_req_size) {
2411                 printk(KERN_ERR
2412                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2413                        rdev->rlc_fw->size, fw_name);
2414                 err = -EINVAL;
2415         }
2416
2417         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) {
2418                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", smc_chip_name);
2419                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
2420                 if (err) {
2421                         printk(KERN_ERR
2422                                "smc: error loading firmware \"%s\"\n",
2423                                fw_name);
2424                         release_firmware(rdev->smc_fw);
2425                         rdev->smc_fw = NULL;
2426                         err = 0;
2427                 } else if (rdev->smc_fw->size != smc_req_size) {
2428                         printk(KERN_ERR
2429                                "smc: Bogus length %zu in firmware \"%s\"\n",
2430                                rdev->smc_fw->size, fw_name);
2431                         err = -EINVAL;
2432                 }
2433         }
2434
2435 out:
2436         if (err) {
2437                 if (err != -EINVAL)
2438                         printk(KERN_ERR
2439                                "r600_cp: Failed to load firmware \"%s\"\n",
2440                                fw_name);
2441                 release_firmware(rdev->pfp_fw);
2442                 rdev->pfp_fw = NULL;
2443                 release_firmware(rdev->me_fw);
2444                 rdev->me_fw = NULL;
2445                 release_firmware(rdev->rlc_fw);
2446                 rdev->rlc_fw = NULL;
2447                 release_firmware(rdev->smc_fw);
2448                 rdev->smc_fw = NULL;
2449         }
2450         return err;
2451 }
2452
2453 u32 r600_gfx_get_rptr(struct radeon_device *rdev,
2454                       struct radeon_ring *ring)
2455 {
2456         u32 rptr;
2457
2458         if (rdev->wb.enabled)
2459                 rptr = rdev->wb.wb[ring->rptr_offs/4];
2460         else
2461                 rptr = RREG32(R600_CP_RB_RPTR);
2462
2463         return rptr;
2464 }
2465
2466 u32 r600_gfx_get_wptr(struct radeon_device *rdev,
2467                       struct radeon_ring *ring)
2468 {
2469         u32 wptr;
2470
2471         wptr = RREG32(R600_CP_RB_WPTR);
2472
2473         return wptr;
2474 }
2475
2476 void r600_gfx_set_wptr(struct radeon_device *rdev,
2477                        struct radeon_ring *ring)
2478 {
2479         WREG32(R600_CP_RB_WPTR, ring->wptr);
2480         (void)RREG32(R600_CP_RB_WPTR);
2481 }
2482
2483 static int r600_cp_load_microcode(struct radeon_device *rdev)
2484 {
2485         const __be32 *fw_data;
2486         int i;
2487
2488         if (!rdev->me_fw || !rdev->pfp_fw)
2489                 return -EINVAL;
2490
2491         r600_cp_stop(rdev);
2492
2493         WREG32(CP_RB_CNTL,
2494 #ifdef __BIG_ENDIAN
2495                BUF_SWAP_32BIT |
2496 #endif
2497                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2498
2499         /* Reset cp */
2500         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2501         RREG32(GRBM_SOFT_RESET);
2502         mdelay(15);
2503         WREG32(GRBM_SOFT_RESET, 0);
2504
2505         WREG32(CP_ME_RAM_WADDR, 0);
2506
2507         fw_data = (const __be32 *)rdev->me_fw->data;
2508         WREG32(CP_ME_RAM_WADDR, 0);
2509         for (i = 0; i < R600_PM4_UCODE_SIZE * 3; i++)
2510                 WREG32(CP_ME_RAM_DATA,
2511                        be32_to_cpup(fw_data++));
2512
2513         fw_data = (const __be32 *)rdev->pfp_fw->data;
2514         WREG32(CP_PFP_UCODE_ADDR, 0);
2515         for (i = 0; i < R600_PFP_UCODE_SIZE; i++)
2516                 WREG32(CP_PFP_UCODE_DATA,
2517                        be32_to_cpup(fw_data++));
2518
2519         WREG32(CP_PFP_UCODE_ADDR, 0);
2520         WREG32(CP_ME_RAM_WADDR, 0);
2521         WREG32(CP_ME_RAM_RADDR, 0);
2522         return 0;
2523 }
2524
2525 int r600_cp_start(struct radeon_device *rdev)
2526 {
2527         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2528         int r;
2529         uint32_t cp_me;
2530
2531         r = radeon_ring_lock(rdev, ring, 7);
2532         if (r) {
2533                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2534                 return r;
2535         }
2536         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2537         radeon_ring_write(ring, 0x1);
2538         if (rdev->family >= CHIP_RV770) {
2539                 radeon_ring_write(ring, 0x0);
2540                 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1);
2541         } else {
2542                 radeon_ring_write(ring, 0x3);
2543                 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1);
2544         }
2545         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2546         radeon_ring_write(ring, 0);
2547         radeon_ring_write(ring, 0);
2548         radeon_ring_unlock_commit(rdev, ring);
2549
2550         cp_me = 0xff;
2551         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2552         return 0;
2553 }
2554
2555 int r600_cp_resume(struct radeon_device *rdev)
2556 {
2557         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2558         u32 tmp;
2559         u32 rb_bufsz;
2560         int r;
2561
2562         /* Reset cp */
2563         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2564         RREG32(GRBM_SOFT_RESET);
2565         mdelay(15);
2566         WREG32(GRBM_SOFT_RESET, 0);
2567
2568         /* Set ring buffer size */
2569         rb_bufsz = order_base_2(ring->ring_size / 8);
2570         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2571 #ifdef __BIG_ENDIAN
2572         tmp |= BUF_SWAP_32BIT;
2573 #endif
2574         WREG32(CP_RB_CNTL, tmp);
2575         WREG32(CP_SEM_WAIT_TIMER, 0x0);
2576
2577         /* Set the write pointer delay */
2578         WREG32(CP_RB_WPTR_DELAY, 0);
2579
2580         /* Initialize the ring buffer's read and write pointers */
2581         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2582         WREG32(CP_RB_RPTR_WR, 0);
2583         ring->wptr = 0;
2584         WREG32(CP_RB_WPTR, ring->wptr);
2585
2586         /* set the wb address whether it's enabled or not */
2587         WREG32(CP_RB_RPTR_ADDR,
2588                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2589         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2590         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2591
2592         if (rdev->wb.enabled)
2593                 WREG32(SCRATCH_UMSK, 0xff);
2594         else {
2595                 tmp |= RB_NO_UPDATE;
2596                 WREG32(SCRATCH_UMSK, 0);
2597         }
2598
2599         mdelay(1);
2600         WREG32(CP_RB_CNTL, tmp);
2601
2602         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2603         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2604
2605         r600_cp_start(rdev);
2606         ring->ready = true;
2607         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2608         if (r) {
2609                 ring->ready = false;
2610                 return r;
2611         }
2612
2613         if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
2614                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2615
2616         return 0;
2617 }
2618
2619 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size)
2620 {
2621         u32 rb_bufsz;
2622         int r;
2623
2624         /* Align ring size */
2625         rb_bufsz = order_base_2(ring_size / 8);
2626         ring_size = (1 << (rb_bufsz + 1)) * 4;
2627         ring->ring_size = ring_size;
2628         ring->align_mask = 16 - 1;
2629
2630         if (radeon_ring_supports_scratch_reg(rdev, ring)) {
2631                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
2632                 if (r) {
2633                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
2634                         ring->rptr_save_reg = 0;
2635                 }
2636         }
2637 }
2638
2639 void r600_cp_fini(struct radeon_device *rdev)
2640 {
2641         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2642         r600_cp_stop(rdev);
2643         radeon_ring_fini(rdev, ring);
2644         radeon_scratch_free(rdev, ring->rptr_save_reg);
2645 }
2646
2647 /*
2648  * GPU scratch registers helpers function.
2649  */
2650 void r600_scratch_init(struct radeon_device *rdev)
2651 {
2652         int i;
2653
2654         rdev->scratch.num_reg = 7;
2655         rdev->scratch.reg_base = SCRATCH_REG0;
2656         for (i = 0; i < rdev->scratch.num_reg; i++) {
2657                 rdev->scratch.free[i] = true;
2658                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2659         }
2660 }
2661
2662 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
2663 {
2664         uint32_t scratch;
2665         uint32_t tmp = 0;
2666         unsigned i;
2667         int r;
2668
2669         r = radeon_scratch_get(rdev, &scratch);
2670         if (r) {
2671                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2672                 return r;
2673         }
2674         WREG32(scratch, 0xCAFEDEAD);
2675         r = radeon_ring_lock(rdev, ring, 3);
2676         if (r) {
2677                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
2678                 radeon_scratch_free(rdev, scratch);
2679                 return r;
2680         }
2681         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2682         radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2683         radeon_ring_write(ring, 0xDEADBEEF);
2684         radeon_ring_unlock_commit(rdev, ring);
2685         for (i = 0; i < rdev->usec_timeout; i++) {
2686                 tmp = RREG32(scratch);
2687                 if (tmp == 0xDEADBEEF)
2688                         break;
2689                 DRM_UDELAY(1);
2690         }
2691         if (i < rdev->usec_timeout) {
2692                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2693         } else {
2694                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2695                           ring->idx, scratch, tmp);
2696                 r = -EINVAL;
2697         }
2698         radeon_scratch_free(rdev, scratch);
2699         return r;
2700 }
2701
2702 /*
2703  * CP fences/semaphores
2704  */
2705
2706 void r600_fence_ring_emit(struct radeon_device *rdev,
2707                           struct radeon_fence *fence)
2708 {
2709         struct radeon_ring *ring = &rdev->ring[fence->ring];
2710         u32 cp_coher_cntl = PACKET3_TC_ACTION_ENA | PACKET3_VC_ACTION_ENA |
2711                 PACKET3_SH_ACTION_ENA;
2712
2713         if (rdev->family >= CHIP_RV770)
2714                 cp_coher_cntl |= PACKET3_FULL_CACHE_ENA;
2715
2716         if (rdev->wb.use_event) {
2717                 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2718                 /* flush read cache over gart */
2719                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2720                 radeon_ring_write(ring, cp_coher_cntl);
2721                 radeon_ring_write(ring, 0xFFFFFFFF);
2722                 radeon_ring_write(ring, 0);
2723                 radeon_ring_write(ring, 10); /* poll interval */
2724                 /* EVENT_WRITE_EOP - flush caches, send int */
2725                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2726                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2727                 radeon_ring_write(ring, addr & 0xffffffff);
2728                 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2729                 radeon_ring_write(ring, fence->seq);
2730                 radeon_ring_write(ring, 0);
2731         } else {
2732                 /* flush read cache over gart */
2733                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2734                 radeon_ring_write(ring, cp_coher_cntl);
2735                 radeon_ring_write(ring, 0xFFFFFFFF);
2736                 radeon_ring_write(ring, 0);
2737                 radeon_ring_write(ring, 10); /* poll interval */
2738                 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2739                 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2740                 /* wait for 3D idle clean */
2741                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2742                 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2743                 radeon_ring_write(ring, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2744                 /* Emit fence sequence & fire IRQ */
2745                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2746                 radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2747                 radeon_ring_write(ring, fence->seq);
2748                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2749                 radeon_ring_write(ring, PACKET0(CP_INT_STATUS, 0));
2750                 radeon_ring_write(ring, RB_INT_STAT);
2751         }
2752 }
2753
2754 bool r600_semaphore_ring_emit(struct radeon_device *rdev,
2755                               struct radeon_ring *ring,
2756                               struct radeon_semaphore *semaphore,
2757                               bool emit_wait)
2758 {
2759         uint64_t addr = semaphore->gpu_addr;
2760         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2761
2762         if (rdev->family < CHIP_CAYMAN)
2763                 sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
2764
2765         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2766         radeon_ring_write(ring, addr & 0xffffffff);
2767         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
2768
2769         return true;
2770 }
2771
2772 /**
2773  * r600_copy_cpdma - copy pages using the CP DMA engine
2774  *
2775  * @rdev: radeon_device pointer
2776  * @src_offset: src GPU address
2777  * @dst_offset: dst GPU address
2778  * @num_gpu_pages: number of GPU pages to xfer
2779  * @fence: radeon fence object
2780  *
2781  * Copy GPU paging using the CP DMA engine (r6xx+).
2782  * Used by the radeon ttm implementation to move pages if
2783  * registered as the asic copy callback.
2784  */
2785 int r600_copy_cpdma(struct radeon_device *rdev,
2786                     uint64_t src_offset, uint64_t dst_offset,
2787                     unsigned num_gpu_pages,
2788                     struct radeon_fence **fence)
2789 {
2790         struct radeon_semaphore *sem = NULL;
2791         int ring_index = rdev->asic->copy.blit_ring_index;
2792         struct radeon_ring *ring = &rdev->ring[ring_index];
2793         u32 size_in_bytes, cur_size_in_bytes, tmp;
2794         int i, num_loops;
2795         int r = 0;
2796
2797         r = radeon_semaphore_create(rdev, &sem);
2798         if (r) {
2799                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2800                 return r;
2801         }
2802
2803         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2804         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2805         r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
2806         if (r) {
2807                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2808                 radeon_semaphore_free(rdev, &sem, NULL);
2809                 return r;
2810         }
2811
2812         radeon_semaphore_sync_to(sem, *fence);
2813         radeon_semaphore_sync_rings(rdev, sem, ring->idx);
2814
2815         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2816         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2817         radeon_ring_write(ring, WAIT_3D_IDLE_bit);
2818         for (i = 0; i < num_loops; i++) {
2819                 cur_size_in_bytes = size_in_bytes;
2820                 if (cur_size_in_bytes > 0x1fffff)
2821                         cur_size_in_bytes = 0x1fffff;
2822                 size_in_bytes -= cur_size_in_bytes;
2823                 tmp = upper_32_bits(src_offset) & 0xff;
2824                 if (size_in_bytes == 0)
2825                         tmp |= PACKET3_CP_DMA_CP_SYNC;
2826                 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
2827                 radeon_ring_write(ring, src_offset & 0xffffffff);
2828                 radeon_ring_write(ring, tmp);
2829                 radeon_ring_write(ring, dst_offset & 0xffffffff);
2830                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
2831                 radeon_ring_write(ring, cur_size_in_bytes);
2832                 src_offset += cur_size_in_bytes;
2833                 dst_offset += cur_size_in_bytes;
2834         }
2835         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2836         radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2837         radeon_ring_write(ring, WAIT_CP_DMA_IDLE_bit);
2838
2839         r = radeon_fence_emit(rdev, fence, ring->idx);
2840         if (r) {
2841                 radeon_ring_unlock_undo(rdev, ring);
2842                 radeon_semaphore_free(rdev, &sem, NULL);
2843                 return r;
2844         }
2845
2846         radeon_ring_unlock_commit(rdev, ring);
2847         radeon_semaphore_free(rdev, &sem, *fence);
2848
2849         return r;
2850 }
2851
2852 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2853                          uint32_t tiling_flags, uint32_t pitch,
2854                          uint32_t offset, uint32_t obj_size)
2855 {
2856         /* FIXME: implement */
2857         return 0;
2858 }
2859
2860 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2861 {
2862         /* FIXME: implement */
2863 }
2864
2865 static int r600_startup(struct radeon_device *rdev)
2866 {
2867         struct radeon_ring *ring;
2868         int r;
2869
2870         /* enable pcie gen2 link */
2871         r600_pcie_gen2_enable(rdev);
2872
2873         /* scratch needs to be initialized before MC */
2874         r = r600_vram_scratch_init(rdev);
2875         if (r)
2876                 return r;
2877
2878         r600_mc_program(rdev);
2879
2880         if (rdev->flags & RADEON_IS_AGP) {
2881                 r600_agp_enable(rdev);
2882         } else {
2883                 r = r600_pcie_gart_enable(rdev);
2884                 if (r)
2885                         return r;
2886         }
2887         r600_gpu_init(rdev);
2888
2889         /* allocate wb buffer */
2890         r = radeon_wb_init(rdev);
2891         if (r)
2892                 return r;
2893
2894         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2895         if (r) {
2896                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2897                 return r;
2898         }
2899
2900         /* Enable IRQ */
2901         if (!rdev->irq.installed) {
2902                 r = radeon_irq_kms_init(rdev);
2903                 if (r)
2904                         return r;
2905         }
2906
2907         r = r600_irq_init(rdev);
2908         if (r) {
2909                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2910                 radeon_irq_kms_fini(rdev);
2911                 return r;
2912         }
2913         r600_irq_set(rdev);
2914
2915         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2916         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2917                              RADEON_CP_PACKET2);
2918         if (r)
2919                 return r;
2920
2921         r = r600_cp_load_microcode(rdev);
2922         if (r)
2923                 return r;
2924         r = r600_cp_resume(rdev);
2925         if (r)
2926                 return r;
2927
2928         r = radeon_ib_pool_init(rdev);
2929         if (r) {
2930                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2931                 return r;
2932         }
2933
2934         r = r600_audio_init(rdev);
2935         if (r) {
2936                 DRM_ERROR("radeon: audio init failed\n");
2937                 return r;
2938         }
2939
2940         return 0;
2941 }
2942
2943 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2944 {
2945         uint32_t temp;
2946
2947         temp = RREG32(CONFIG_CNTL);
2948         if (state == false) {
2949                 temp &= ~(1<<0);
2950                 temp |= (1<<1);
2951         } else {
2952                 temp &= ~(1<<1);
2953         }
2954         WREG32(CONFIG_CNTL, temp);
2955 }
2956
2957 int r600_resume(struct radeon_device *rdev)
2958 {
2959         int r;
2960
2961         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2962          * posting will perform necessary task to bring back GPU into good
2963          * shape.
2964          */
2965         /* post card */
2966         atom_asic_init(rdev->mode_info.atom_context);
2967
2968         if (rdev->pm.pm_method == PM_METHOD_DPM)
2969                 radeon_pm_resume(rdev);
2970
2971         rdev->accel_working = true;
2972         r = r600_startup(rdev);
2973         if (r) {
2974                 DRM_ERROR("r600 startup failed on resume\n");
2975                 rdev->accel_working = false;
2976                 return r;
2977         }
2978
2979         return r;
2980 }
2981
2982 int r600_suspend(struct radeon_device *rdev)
2983 {
2984         radeon_pm_suspend(rdev);
2985         r600_audio_fini(rdev);
2986         r600_cp_stop(rdev);
2987         r600_irq_suspend(rdev);
2988         radeon_wb_disable(rdev);
2989         r600_pcie_gart_disable(rdev);
2990
2991         return 0;
2992 }
2993
2994 /* Plan is to move initialization in that function and use
2995  * helper function so that radeon_device_init pretty much
2996  * do nothing more than calling asic specific function. This
2997  * should also allow to remove a bunch of callback function
2998  * like vram_info.
2999  */
3000 int r600_init(struct radeon_device *rdev)
3001 {
3002         int r;
3003
3004         if (r600_debugfs_mc_info_init(rdev)) {
3005                 DRM_ERROR("Failed to register debugfs file for mc !\n");
3006         }
3007         /* Read BIOS */
3008         if (!radeon_get_bios(rdev)) {
3009                 if (ASIC_IS_AVIVO(rdev))
3010                         return -EINVAL;
3011         }
3012         /* Must be an ATOMBIOS */
3013         if (!rdev->is_atom_bios) {
3014                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
3015                 return -EINVAL;
3016         }
3017         r = radeon_atombios_init(rdev);
3018         if (r)
3019                 return r;
3020         /* Post card if necessary */
3021         if (!radeon_card_posted(rdev)) {
3022                 if (!rdev->bios) {
3023                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3024                         return -EINVAL;
3025                 }
3026                 DRM_INFO("GPU not posted. posting now...\n");
3027                 atom_asic_init(rdev->mode_info.atom_context);
3028         }
3029         /* Initialize scratch registers */
3030         r600_scratch_init(rdev);
3031         /* Initialize surface registers */
3032         radeon_surface_init(rdev);
3033         /* Initialize clocks */
3034         radeon_get_clock_info(rdev->ddev);
3035         /* Fence driver */
3036         r = radeon_fence_driver_init(rdev);
3037         if (r)
3038                 return r;
3039         if (rdev->flags & RADEON_IS_AGP) {
3040                 r = radeon_agp_init(rdev);
3041                 if (r)
3042                         radeon_agp_disable(rdev);
3043         }
3044         r = r600_mc_init(rdev);
3045         if (r)
3046                 return r;
3047         /* Memory manager */
3048         r = radeon_bo_init(rdev);
3049         if (r)
3050                 return r;
3051
3052         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3053                 r = r600_init_microcode(rdev);
3054                 if (r) {
3055                         DRM_ERROR("Failed to load firmware!\n");
3056                         return r;
3057                 }
3058         }
3059
3060         /* Initialize power management */
3061         radeon_pm_init(rdev);
3062
3063         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3064         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3065
3066         rdev->ih.ring_obj = NULL;
3067         r600_ih_ring_init(rdev, 64 * 1024);
3068
3069         r = r600_pcie_gart_init(rdev);
3070         if (r)
3071                 return r;
3072
3073         rdev->accel_working = true;
3074         r = r600_startup(rdev);
3075         if (r) {
3076                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3077                 r600_cp_fini(rdev);
3078                 r600_irq_fini(rdev);
3079                 radeon_wb_fini(rdev);
3080                 radeon_ib_pool_fini(rdev);
3081                 radeon_irq_kms_fini(rdev);
3082                 r600_pcie_gart_fini(rdev);
3083                 rdev->accel_working = false;
3084         }
3085
3086         return 0;
3087 }
3088
3089 void r600_fini(struct radeon_device *rdev)
3090 {
3091         radeon_pm_fini(rdev);
3092         r600_audio_fini(rdev);
3093         r600_cp_fini(rdev);
3094         r600_irq_fini(rdev);
3095         radeon_wb_fini(rdev);
3096         radeon_ib_pool_fini(rdev);
3097         radeon_irq_kms_fini(rdev);
3098         r600_pcie_gart_fini(rdev);
3099         r600_vram_scratch_fini(rdev);
3100         radeon_agp_fini(rdev);
3101         radeon_gem_fini(rdev);
3102         radeon_fence_driver_fini(rdev);
3103         radeon_bo_fini(rdev);
3104         radeon_atombios_fini(rdev);
3105         kfree(rdev->bios);
3106         rdev->bios = NULL;
3107 }
3108
3109
3110 /*
3111  * CS stuff
3112  */
3113 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3114 {
3115         struct radeon_ring *ring = &rdev->ring[ib->ring];
3116         u32 next_rptr;
3117
3118         if (ring->rptr_save_reg) {
3119                 next_rptr = ring->wptr + 3 + 4;
3120                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3121                 radeon_ring_write(ring, ((ring->rptr_save_reg -
3122                                          PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
3123                 radeon_ring_write(ring, next_rptr);
3124         } else if (rdev->wb.enabled) {
3125                 next_rptr = ring->wptr + 5 + 4;
3126                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
3127                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3128                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
3129                 radeon_ring_write(ring, next_rptr);
3130                 radeon_ring_write(ring, 0);
3131         }
3132
3133         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3134         radeon_ring_write(ring,
3135 #ifdef __BIG_ENDIAN
3136                           (2 << 0) |
3137 #endif
3138                           (ib->gpu_addr & 0xFFFFFFFC));
3139         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
3140         radeon_ring_write(ring, ib->length_dw);
3141 }
3142
3143 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3144 {
3145         struct radeon_ib ib;
3146         uint32_t scratch;
3147         uint32_t tmp = 0;
3148         unsigned i;
3149         int r;
3150
3151         r = radeon_scratch_get(rdev, &scratch);
3152         if (r) {
3153                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3154                 return r;
3155         }
3156         WREG32(scratch, 0xCAFEDEAD);
3157         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3158         if (r) {
3159                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3160                 goto free_scratch;
3161         }
3162         ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
3163         ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3164         ib.ptr[2] = 0xDEADBEEF;
3165         ib.length_dw = 3;
3166         r = radeon_ib_schedule(rdev, &ib, NULL);
3167         if (r) {
3168                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3169                 goto free_ib;
3170         }
3171         r = radeon_fence_wait(ib.fence, false);
3172         if (r) {
3173                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3174                 goto free_ib;
3175         }
3176         for (i = 0; i < rdev->usec_timeout; i++) {
3177                 tmp = RREG32(scratch);
3178                 if (tmp == 0xDEADBEEF)
3179                         break;
3180                 DRM_UDELAY(1);
3181         }
3182         if (i < rdev->usec_timeout) {
3183                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3184         } else {
3185                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3186                           scratch, tmp);
3187                 r = -EINVAL;
3188         }
3189 free_ib:
3190         radeon_ib_free(rdev, &ib);
3191 free_scratch:
3192         radeon_scratch_free(rdev, scratch);
3193         return r;
3194 }
3195
3196 /*
3197  * Interrupts
3198  *
3199  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
3200  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
3201  * writing to the ring and the GPU consuming, the GPU writes to the ring
3202  * and host consumes.  As the host irq handler processes interrupts, it
3203  * increments the rptr.  When the rptr catches up with the wptr, all the
3204  * current interrupts have been processed.
3205  */
3206
3207 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
3208 {
3209         u32 rb_bufsz;
3210
3211         /* Align ring size */
3212         rb_bufsz = order_base_2(ring_size / 4);
3213         ring_size = (1 << rb_bufsz) * 4;
3214         rdev->ih.ring_size = ring_size;
3215         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
3216         rdev->ih.rptr = 0;
3217 }
3218
3219 int r600_ih_ring_alloc(struct radeon_device *rdev)
3220 {
3221         int r;
3222
3223         /* Allocate ring buffer */
3224         if (rdev->ih.ring_obj == NULL) {
3225                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
3226                                      PAGE_SIZE, true,
3227                                      RADEON_GEM_DOMAIN_GTT,
3228                                      NULL, &rdev->ih.ring_obj);
3229                 if (r) {
3230                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
3231                         return r;
3232                 }
3233                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3234                 if (unlikely(r != 0))
3235                         return r;
3236                 r = radeon_bo_pin(rdev->ih.ring_obj,
3237                                   RADEON_GEM_DOMAIN_GTT,
3238                                   &rdev->ih.gpu_addr);
3239                 if (r) {
3240                         radeon_bo_unreserve(rdev->ih.ring_obj);
3241                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
3242                         return r;
3243                 }
3244                 r = radeon_bo_kmap(rdev->ih.ring_obj,
3245                                    (void **)&rdev->ih.ring);
3246                 radeon_bo_unreserve(rdev->ih.ring_obj);
3247                 if (r) {
3248                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
3249                         return r;
3250                 }
3251         }
3252         return 0;
3253 }
3254
3255 void r600_ih_ring_fini(struct radeon_device *rdev)
3256 {
3257         int r;
3258         if (rdev->ih.ring_obj) {
3259                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
3260                 if (likely(r == 0)) {
3261                         radeon_bo_kunmap(rdev->ih.ring_obj);
3262                         radeon_bo_unpin(rdev->ih.ring_obj);
3263                         radeon_bo_unreserve(rdev->ih.ring_obj);
3264                 }
3265                 radeon_bo_unref(&rdev->ih.ring_obj);
3266                 rdev->ih.ring = NULL;
3267                 rdev->ih.ring_obj = NULL;
3268         }
3269 }
3270
3271 void r600_rlc_stop(struct radeon_device *rdev)
3272 {
3273
3274         if ((rdev->family >= CHIP_RV770) &&
3275             (rdev->family <= CHIP_RV740)) {
3276                 /* r7xx asics need to soft reset RLC before halting */
3277                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
3278                 RREG32(SRBM_SOFT_RESET);
3279                 mdelay(15);
3280                 WREG32(SRBM_SOFT_RESET, 0);
3281                 RREG32(SRBM_SOFT_RESET);
3282         }
3283
3284         WREG32(RLC_CNTL, 0);
3285 }
3286
3287 static void r600_rlc_start(struct radeon_device *rdev)
3288 {
3289         WREG32(RLC_CNTL, RLC_ENABLE);
3290 }
3291
3292 static int r600_rlc_resume(struct radeon_device *rdev)
3293 {
3294         u32 i;
3295         const __be32 *fw_data;
3296
3297         if (!rdev->rlc_fw)
3298                 return -EINVAL;
3299
3300         r600_rlc_stop(rdev);
3301
3302         WREG32(RLC_HB_CNTL, 0);
3303
3304         WREG32(RLC_HB_BASE, 0);
3305         WREG32(RLC_HB_RPTR, 0);
3306         WREG32(RLC_HB_WPTR, 0);
3307         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
3308         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
3309         WREG32(RLC_MC_CNTL, 0);
3310         WREG32(RLC_UCODE_CNTL, 0);
3311
3312         fw_data = (const __be32 *)rdev->rlc_fw->data;
3313         if (rdev->family >= CHIP_RV770) {
3314                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
3315                         WREG32(RLC_UCODE_ADDR, i);
3316                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3317                 }
3318         } else {
3319                 for (i = 0; i < R600_RLC_UCODE_SIZE; i++) {
3320                         WREG32(RLC_UCODE_ADDR, i);
3321                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
3322                 }
3323         }
3324         WREG32(RLC_UCODE_ADDR, 0);
3325
3326         r600_rlc_start(rdev);
3327
3328         return 0;
3329 }
3330
3331 static void r600_enable_interrupts(struct radeon_device *rdev)
3332 {
3333         u32 ih_cntl = RREG32(IH_CNTL);
3334         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3335
3336         ih_cntl |= ENABLE_INTR;
3337         ih_rb_cntl |= IH_RB_ENABLE;
3338         WREG32(IH_CNTL, ih_cntl);
3339         WREG32(IH_RB_CNTL, ih_rb_cntl);
3340         rdev->ih.enabled = true;
3341 }
3342
3343 void r600_disable_interrupts(struct radeon_device *rdev)
3344 {
3345         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3346         u32 ih_cntl = RREG32(IH_CNTL);
3347
3348         ih_rb_cntl &= ~IH_RB_ENABLE;
3349         ih_cntl &= ~ENABLE_INTR;
3350         WREG32(IH_RB_CNTL, ih_rb_cntl);
3351         WREG32(IH_CNTL, ih_cntl);
3352         /* set rptr, wptr to 0 */
3353         WREG32(IH_RB_RPTR, 0);
3354         WREG32(IH_RB_WPTR, 0);
3355         rdev->ih.enabled = false;
3356         rdev->ih.rptr = 0;
3357 }
3358
3359 static void r600_disable_interrupt_state(struct radeon_device *rdev)
3360 {
3361         u32 tmp;
3362
3363         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3364         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3365         WREG32(DMA_CNTL, tmp);
3366         WREG32(GRBM_INT_CNTL, 0);
3367         WREG32(DxMODE_INT_MASK, 0);
3368         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
3369         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
3370         if (ASIC_IS_DCE3(rdev)) {
3371                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
3372                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
3373                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3374                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3375                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3376                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3377                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3378                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3379                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3380                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3381                 if (ASIC_IS_DCE32(rdev)) {
3382                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3383                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3384                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3385                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3386                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3387                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3388                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3389                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3390                 } else {
3391                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3392                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3393                         tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3394                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3395                 }
3396         } else {
3397                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
3398                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
3399                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3400                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3401                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3402                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3403                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
3404                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3405                 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3406                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3407                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3408                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3409         }
3410 }
3411
3412 int r600_irq_init(struct radeon_device *rdev)
3413 {
3414         int ret = 0;
3415         int rb_bufsz;
3416         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3417
3418         /* allocate ring */
3419         ret = r600_ih_ring_alloc(rdev);
3420         if (ret)
3421                 return ret;
3422
3423         /* disable irqs */
3424         r600_disable_interrupts(rdev);
3425
3426         /* init rlc */
3427         if (rdev->family >= CHIP_CEDAR)
3428                 ret = evergreen_rlc_resume(rdev);
3429         else
3430                 ret = r600_rlc_resume(rdev);
3431         if (ret) {
3432                 r600_ih_ring_fini(rdev);
3433                 return ret;
3434         }
3435
3436         /* setup interrupt control */
3437         /* set dummy read address to ring address */
3438         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3439         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3440         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3441          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3442          */
3443         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3444         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3445         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3446         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3447
3448         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3449         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
3450
3451         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3452                       IH_WPTR_OVERFLOW_CLEAR |
3453                       (rb_bufsz << 1));
3454
3455         if (rdev->wb.enabled)
3456                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3457
3458         /* set the writeback address whether it's enabled or not */
3459         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3460         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3461
3462         WREG32(IH_RB_CNTL, ih_rb_cntl);
3463
3464         /* set rptr, wptr to 0 */
3465         WREG32(IH_RB_RPTR, 0);
3466         WREG32(IH_RB_WPTR, 0);
3467
3468         /* Default settings for IH_CNTL (disabled at first) */
3469         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
3470         /* RPTR_REARM only works if msi's are enabled */
3471         if (rdev->msi_enabled)
3472                 ih_cntl |= RPTR_REARM;
3473         WREG32(IH_CNTL, ih_cntl);
3474
3475         /* force the active interrupt state to all disabled */
3476         if (rdev->family >= CHIP_CEDAR)
3477                 evergreen_disable_interrupt_state(rdev);
3478         else
3479                 r600_disable_interrupt_state(rdev);
3480
3481         /* at this point everything should be setup correctly to enable master */
3482         pci_set_master(rdev->pdev);
3483
3484         /* enable irqs */
3485         r600_enable_interrupts(rdev);
3486
3487         return ret;
3488 }
3489
3490 void r600_irq_suspend(struct radeon_device *rdev)
3491 {
3492         r600_irq_disable(rdev);
3493         r600_rlc_stop(rdev);
3494 }
3495
3496 void r600_irq_fini(struct radeon_device *rdev)
3497 {
3498         r600_irq_suspend(rdev);
3499         r600_ih_ring_fini(rdev);
3500 }
3501
3502 int r600_irq_set(struct radeon_device *rdev)
3503 {
3504         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3505         u32 mode_int = 0;
3506         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3507         u32 grbm_int_cntl = 0;
3508         u32 hdmi0, hdmi1;
3509         u32 dma_cntl;
3510         u32 thermal_int = 0;
3511
3512         if (!rdev->irq.installed) {
3513                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3514                 return -EINVAL;
3515         }
3516         /* don't enable anything if the ih is disabled */
3517         if (!rdev->ih.enabled) {
3518                 r600_disable_interrupts(rdev);
3519                 /* force the active interrupt state to all disabled */
3520                 r600_disable_interrupt_state(rdev);
3521                 return 0;
3522         }
3523
3524         if (ASIC_IS_DCE3(rdev)) {
3525                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3526                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3527                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3528                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3529                 if (ASIC_IS_DCE32(rdev)) {
3530                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3531                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3532                         hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3533                         hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
3534                 } else {
3535                         hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3536                         hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3537                 }
3538         } else {
3539                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3540                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3541                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3542                 hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3543                 hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
3544         }
3545
3546         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
3547
3548         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3549                 thermal_int = RREG32(CG_THERMAL_INT) &
3550                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3551         } else if (rdev->family >= CHIP_RV770) {
3552                 thermal_int = RREG32(RV770_CG_THERMAL_INT) &
3553                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
3554         }
3555         if (rdev->irq.dpm_thermal) {
3556                 DRM_DEBUG("dpm thermal\n");
3557                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
3558         }
3559
3560         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3561                 DRM_DEBUG("r600_irq_set: sw int\n");
3562                 cp_int_cntl |= RB_INT_ENABLE;
3563                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3564         }
3565
3566         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3567                 DRM_DEBUG("r600_irq_set: sw int dma\n");
3568                 dma_cntl |= TRAP_ENABLE;
3569         }
3570
3571         if (rdev->irq.crtc_vblank_int[0] ||
3572             atomic_read(&rdev->irq.pflip[0])) {
3573                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3574                 mode_int |= D1MODE_VBLANK_INT_MASK;
3575         }
3576         if (rdev->irq.crtc_vblank_int[1] ||
3577             atomic_read(&rdev->irq.pflip[1])) {
3578                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3579                 mode_int |= D2MODE_VBLANK_INT_MASK;
3580         }
3581         if (rdev->irq.hpd[0]) {
3582                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3583                 hpd1 |= DC_HPDx_INT_EN;
3584         }
3585         if (rdev->irq.hpd[1]) {
3586                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3587                 hpd2 |= DC_HPDx_INT_EN;
3588         }
3589         if (rdev->irq.hpd[2]) {
3590                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3591                 hpd3 |= DC_HPDx_INT_EN;
3592         }
3593         if (rdev->irq.hpd[3]) {
3594                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3595                 hpd4 |= DC_HPDx_INT_EN;
3596         }
3597         if (rdev->irq.hpd[4]) {
3598                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3599                 hpd5 |= DC_HPDx_INT_EN;
3600         }
3601         if (rdev->irq.hpd[5]) {
3602                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3603                 hpd6 |= DC_HPDx_INT_EN;
3604         }
3605         if (rdev->irq.afmt[0]) {
3606                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3607                 hdmi0 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3608         }
3609         if (rdev->irq.afmt[1]) {
3610                 DRM_DEBUG("r600_irq_set: hdmi 0\n");
3611                 hdmi1 |= HDMI0_AZ_FORMAT_WTRIG_MASK;
3612         }
3613
3614         WREG32(CP_INT_CNTL, cp_int_cntl);
3615         WREG32(DMA_CNTL, dma_cntl);
3616         WREG32(DxMODE_INT_MASK, mode_int);
3617         WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3618         WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
3619         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3620         if (ASIC_IS_DCE3(rdev)) {
3621                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3622                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3623                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3624                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3625                 if (ASIC_IS_DCE32(rdev)) {
3626                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3627                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3628                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0);
3629                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1);
3630                 } else {
3631                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3632                         WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3633                 }
3634         } else {
3635                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3636                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3637                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3638                 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
3639                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1);
3640         }
3641         if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) {
3642                 WREG32(CG_THERMAL_INT, thermal_int);
3643         } else if (rdev->family >= CHIP_RV770) {
3644                 WREG32(RV770_CG_THERMAL_INT, thermal_int);
3645         }
3646
3647         return 0;
3648 }
3649
3650 static void r600_irq_ack(struct radeon_device *rdev)
3651 {
3652         u32 tmp;
3653
3654         if (ASIC_IS_DCE3(rdev)) {
3655                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3656                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3657                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3658                 if (ASIC_IS_DCE32(rdev)) {
3659                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);
3660                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);
3661                 } else {
3662                         rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3663                         rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);
3664                 }
3665         } else {
3666                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3667                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3668                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3669                 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);
3670                 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);
3671         }
3672         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3673         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3674
3675         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3676                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3677         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3678                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3679         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3680                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3681         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3682                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3683         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3684                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3685         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3686                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3687         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3688                 if (ASIC_IS_DCE3(rdev)) {
3689                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3690                         tmp |= DC_HPDx_INT_ACK;
3691                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3692                 } else {
3693                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3694                         tmp |= DC_HPDx_INT_ACK;
3695                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3696                 }
3697         }
3698         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3699                 if (ASIC_IS_DCE3(rdev)) {
3700                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3701                         tmp |= DC_HPDx_INT_ACK;
3702                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3703                 } else {
3704                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3705                         tmp |= DC_HPDx_INT_ACK;
3706                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3707                 }
3708         }
3709         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3710                 if (ASIC_IS_DCE3(rdev)) {
3711                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3712                         tmp |= DC_HPDx_INT_ACK;
3713                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3714                 } else {
3715                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3716                         tmp |= DC_HPDx_INT_ACK;
3717                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3718                 }
3719         }
3720         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3721                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3722                 tmp |= DC_HPDx_INT_ACK;
3723                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3724         }
3725         if (ASIC_IS_DCE32(rdev)) {
3726                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3727                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3728                         tmp |= DC_HPDx_INT_ACK;
3729                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3730                 }
3731                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3732                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3733                         tmp |= DC_HPDx_INT_ACK;
3734                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3735                 }
3736                 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) {
3737                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);
3738                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3739                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp);
3740                 }
3741                 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) {
3742                         tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);
3743                         tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
3744                         WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp);
3745                 }
3746         } else {
3747                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3748                         tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);
3749                         tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3750                         WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp);
3751                 }
3752                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3753                         if (ASIC_IS_DCE3(rdev)) {
3754                                 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);
3755                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3756                                 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp);
3757                         } else {
3758                                 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);
3759                                 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK;
3760                                 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp);
3761                         }
3762                 }
3763         }
3764 }
3765
3766 void r600_irq_disable(struct radeon_device *rdev)
3767 {
3768         r600_disable_interrupts(rdev);
3769         /* Wait and acknowledge irq */
3770         mdelay(1);
3771         r600_irq_ack(rdev);
3772         r600_disable_interrupt_state(rdev);
3773 }
3774
3775 static u32 r600_get_ih_wptr(struct radeon_device *rdev)
3776 {
3777         u32 wptr, tmp;
3778
3779         if (rdev->wb.enabled)
3780                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3781         else
3782                 wptr = RREG32(IH_RB_WPTR);
3783
3784         if (wptr & RB_OVERFLOW) {
3785                 /* When a ring buffer overflow happen start parsing interrupt
3786                  * from the last not overwritten vector (wptr + 16). Hopefully
3787                  * this should allow us to catchup.
3788                  */
3789                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3790                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3791                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3792                 tmp = RREG32(IH_RB_CNTL);
3793                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3794                 WREG32(IH_RB_CNTL, tmp);
3795         }
3796         return (wptr & rdev->ih.ptr_mask);
3797 }
3798
3799 /*        r600 IV Ring
3800  * Each IV ring entry is 128 bits:
3801  * [7:0]    - interrupt source id
3802  * [31:8]   - reserved
3803  * [59:32]  - interrupt source data
3804  * [127:60]  - reserved
3805  *
3806  * The basic interrupt vector entries
3807  * are decoded as follows:
3808  * src_id  src_data  description
3809  *      1         0  D1 Vblank
3810  *      1         1  D1 Vline
3811  *      5         0  D2 Vblank
3812  *      5         1  D2 Vline
3813  *     19         0  FP Hot plug detection A
3814  *     19         1  FP Hot plug detection B
3815  *     19         2  DAC A auto-detection
3816  *     19         3  DAC B auto-detection
3817  *     21         4  HDMI block A
3818  *     21         5  HDMI block B
3819  *    176         -  CP_INT RB
3820  *    177         -  CP_INT IB1
3821  *    178         -  CP_INT IB2
3822  *    181         -  EOP Interrupt
3823  *    233         -  GUI Idle
3824  *
3825  * Note, these are based on r600 and may need to be
3826  * adjusted or added to on newer asics
3827  */
3828
3829 int r600_irq_process(struct radeon_device *rdev)
3830 {
3831         u32 wptr;
3832         u32 rptr;
3833         u32 src_id, src_data;
3834         u32 ring_index;
3835         bool queue_hotplug = false;
3836         bool queue_hdmi = false;
3837         bool queue_thermal = false;
3838
3839         if (!rdev->ih.enabled || rdev->shutdown)
3840                 return IRQ_NONE;
3841
3842         /* No MSIs, need a dummy read to flush PCI DMAs */
3843         if (!rdev->msi_enabled)
3844                 RREG32(IH_RB_WPTR);
3845
3846         wptr = r600_get_ih_wptr(rdev);
3847
3848 restart_ih:
3849         /* is somebody else already processing irqs? */
3850         if (atomic_xchg(&rdev->ih.lock, 1))
3851                 return IRQ_NONE;
3852
3853         rptr = rdev->ih.rptr;
3854         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3855
3856         /* Order reading of wptr vs. reading of IH ring data */
3857         rmb();
3858
3859         /* display interrupts */
3860         r600_irq_ack(rdev);
3861
3862         while (rptr != wptr) {
3863                 /* wptr/rptr are in bytes! */
3864                 ring_index = rptr / 4;
3865                 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3866                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3867
3868                 switch (src_id) {
3869                 case 1: /* D1 vblank/vline */
3870                         switch (src_data) {
3871                         case 0: /* D1 vblank */
3872                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3873                                         if (rdev->irq.crtc_vblank_int[0]) {
3874                                                 drm_handle_vblank(rdev->ddev, 0);
3875                                                 rdev->pm.vblank_sync = true;
3876                                                 wake_up(&rdev->irq.vblank_queue);
3877                                         }
3878                                         if (atomic_read(&rdev->irq.pflip[0]))
3879                                                 radeon_crtc_handle_flip(rdev, 0);
3880                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3881                                         DRM_DEBUG("IH: D1 vblank\n");
3882                                 }
3883                                 break;
3884                         case 1: /* D1 vline */
3885                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3886                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3887                                         DRM_DEBUG("IH: D1 vline\n");
3888                                 }
3889                                 break;
3890                         default:
3891                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3892                                 break;
3893                         }
3894                         break;
3895                 case 5: /* D2 vblank/vline */
3896                         switch (src_data) {
3897                         case 0: /* D2 vblank */
3898                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3899                                         if (rdev->irq.crtc_vblank_int[1]) {
3900                                                 drm_handle_vblank(rdev->ddev, 1);
3901                                                 rdev->pm.vblank_sync = true;
3902                                                 wake_up(&rdev->irq.vblank_queue);
3903                                         }
3904                                         if (atomic_read(&rdev->irq.pflip[1]))
3905                                                 radeon_crtc_handle_flip(rdev, 1);
3906                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3907                                         DRM_DEBUG("IH: D2 vblank\n");
3908                                 }
3909                                 break;
3910                         case 1: /* D1 vline */
3911                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3912                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3913                                         DRM_DEBUG("IH: D2 vline\n");
3914                                 }
3915                                 break;
3916                         default:
3917                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3918                                 break;
3919                         }
3920                         break;
3921                 case 9: /* D1 pflip */
3922                         DRM_DEBUG("IH: D1 flip\n");
3923                         radeon_crtc_handle_flip(rdev, 0);
3924                         break;
3925                 case 11: /* D2 pflip */
3926                         DRM_DEBUG("IH: D2 flip\n");
3927                         radeon_crtc_handle_flip(rdev, 1);
3928                         break;
3929                 case 19: /* HPD/DAC hotplug */
3930                         switch (src_data) {
3931                         case 0:
3932                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3933                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3934                                         queue_hotplug = true;
3935                                         DRM_DEBUG("IH: HPD1\n");
3936                                 }
3937                                 break;
3938                         case 1:
3939                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3940                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3941                                         queue_hotplug = true;
3942                                         DRM_DEBUG("IH: HPD2\n");
3943                                 }
3944                                 break;
3945                         case 4:
3946                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3947                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3948                                         queue_hotplug = true;
3949                                         DRM_DEBUG("IH: HPD3\n");
3950                                 }
3951                                 break;
3952                         case 5:
3953                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3954                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3955                                         queue_hotplug = true;
3956                                         DRM_DEBUG("IH: HPD4\n");
3957                                 }
3958                                 break;
3959                         case 10:
3960                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3961                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3962                                         queue_hotplug = true;
3963                                         DRM_DEBUG("IH: HPD5\n");
3964                                 }
3965                                 break;
3966                         case 12:
3967                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3968                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3969                                         queue_hotplug = true;
3970                                         DRM_DEBUG("IH: HPD6\n");
3971                                 }
3972                                 break;
3973                         default:
3974                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3975                                 break;
3976                         }
3977                         break;
3978                 case 21: /* hdmi */
3979                         switch (src_data) {
3980                         case 4:
3981                                 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) {
3982                                         rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3983                                         queue_hdmi = true;
3984                                         DRM_DEBUG("IH: HDMI0\n");
3985                                 }
3986                                 break;
3987                         case 5:
3988                                 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) {
3989                                         rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG;
3990                                         queue_hdmi = true;
3991                                         DRM_DEBUG("IH: HDMI1\n");
3992                                 }
3993                                 break;
3994                         default:
3995                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3996                                 break;
3997                         }
3998                         break;
3999                 case 124: /* UVD */
4000                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
4001                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
4002                         break;
4003                 case 176: /* CP_INT in ring buffer */
4004                 case 177: /* CP_INT in IB1 */
4005                 case 178: /* CP_INT in IB2 */
4006                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
4007                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4008                         break;
4009                 case 181: /* CP EOP event */
4010                         DRM_DEBUG("IH: CP EOP\n");
4011                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4012                         break;
4013                 case 224: /* DMA trap event */
4014                         DRM_DEBUG("IH: DMA trap\n");
4015                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4016                         break;
4017                 case 230: /* thermal low to high */
4018                         DRM_DEBUG("IH: thermal low to high\n");
4019                         rdev->pm.dpm.thermal.high_to_low = false;
4020                         queue_thermal = true;
4021                         break;
4022                 case 231: /* thermal high to low */
4023                         DRM_DEBUG("IH: thermal high to low\n");
4024                         rdev->pm.dpm.thermal.high_to_low = true;
4025                         queue_thermal = true;
4026                         break;
4027                 case 233: /* GUI IDLE */
4028                         DRM_DEBUG("IH: GUI idle\n");
4029                         break;
4030                 default:
4031                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4032                         break;
4033                 }
4034
4035                 /* wptr/rptr are in bytes! */
4036                 rptr += 16;
4037                 rptr &= rdev->ih.ptr_mask;
4038         }
4039         if (queue_hotplug)
4040                 schedule_work(&rdev->hotplug_work);
4041         if (queue_hdmi)
4042                 schedule_work(&rdev->audio_work);
4043         if (queue_thermal && rdev->pm.dpm_enabled)
4044                 schedule_work(&rdev->pm.dpm.thermal.work);
4045         rdev->ih.rptr = rptr;
4046         WREG32(IH_RB_RPTR, rdev->ih.rptr);
4047         atomic_set(&rdev->ih.lock, 0);
4048
4049         /* make sure wptr hasn't changed while processing */
4050         wptr = r600_get_ih_wptr(rdev);
4051         if (wptr != rptr)
4052                 goto restart_ih;
4053
4054         return IRQ_HANDLED;
4055 }
4056
4057 /*
4058  * Debugfs info
4059  */
4060 #if defined(CONFIG_DEBUG_FS)
4061
4062 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
4063 {
4064         struct drm_info_node *node = (struct drm_info_node *) m->private;
4065         struct drm_device *dev = node->minor->dev;
4066         struct radeon_device *rdev = dev->dev_private;
4067
4068         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
4069         DREG32_SYS(m, rdev, VM_L2_STATUS);
4070         return 0;
4071 }
4072
4073 static struct drm_info_list r600_mc_info_list[] = {
4074         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
4075 };
4076 #endif
4077
4078 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
4079 {
4080 #if defined(CONFIG_DEBUG_FS)
4081         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
4082 #else
4083         return 0;
4084 #endif
4085 }
4086
4087 /**
4088  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
4089  * rdev: radeon device structure
4090  * bo: buffer object struct which userspace is waiting for idle
4091  *
4092  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
4093  * through ring buffer, this leads to corruption in rendering, see
4094  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
4095  * directly perform HDP flush by writing register through MMIO.
4096  */
4097 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
4098 {
4099         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
4100          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
4101          * This seems to cause problems on some AGP cards. Just use the old
4102          * method for them.
4103          */
4104         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
4105             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
4106                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
4107                 u32 tmp;
4108
4109                 WREG32(HDP_DEBUG1, 0);
4110                 tmp = readl((void __iomem *)ptr);
4111         } else
4112                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
4113 }
4114
4115 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
4116 {
4117         u32 link_width_cntl, mask;
4118
4119         if (rdev->flags & RADEON_IS_IGP)
4120                 return;
4121
4122         if (!(rdev->flags & RADEON_IS_PCIE))
4123                 return;
4124
4125         /* x2 cards have a special sequence */
4126         if (ASIC_IS_X2(rdev))
4127                 return;
4128
4129         radeon_gui_idle(rdev);
4130
4131         switch (lanes) {
4132         case 0:
4133                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
4134                 break;
4135         case 1:
4136                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
4137                 break;
4138         case 2:
4139                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
4140                 break;
4141         case 4:
4142                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
4143                 break;
4144         case 8:
4145                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
4146                 break;
4147         case 12:
4148                 /* not actually supported */
4149                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
4150                 break;
4151         case 16:
4152                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
4153                 break;
4154         default:
4155                 DRM_ERROR("invalid pcie lane request: %d\n", lanes);
4156                 return;
4157         }
4158
4159         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4160         link_width_cntl &= ~RADEON_PCIE_LC_LINK_WIDTH_MASK;
4161         link_width_cntl |= mask << RADEON_PCIE_LC_LINK_WIDTH_SHIFT;
4162         link_width_cntl |= (RADEON_PCIE_LC_RECONFIG_NOW |
4163                             R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
4164
4165         WREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4166 }
4167
4168 int r600_get_pcie_lanes(struct radeon_device *rdev)
4169 {
4170         u32 link_width_cntl;
4171
4172         if (rdev->flags & RADEON_IS_IGP)
4173                 return 0;
4174
4175         if (!(rdev->flags & RADEON_IS_PCIE))
4176                 return 0;
4177
4178         /* x2 cards have a special sequence */
4179         if (ASIC_IS_X2(rdev))
4180                 return 0;
4181
4182         radeon_gui_idle(rdev);
4183
4184         link_width_cntl = RREG32_PCIE_PORT(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
4185
4186         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
4187         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4188                 return 1;
4189         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4190                 return 2;
4191         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4192                 return 4;
4193         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4194                 return 8;
4195         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4196                 /* not actually supported */
4197                 return 12;
4198         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4199         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4200         default:
4201                 return 16;
4202         }
4203 }
4204
4205 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
4206 {
4207         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
4208         u16 link_cntl2;
4209
4210         if (radeon_pcie_gen2 == 0)
4211                 return;
4212
4213         if (rdev->flags & RADEON_IS_IGP)
4214                 return;
4215
4216         if (!(rdev->flags & RADEON_IS_PCIE))
4217                 return;
4218
4219         /* x2 cards have a special sequence */
4220         if (ASIC_IS_X2(rdev))
4221                 return;
4222
4223         /* only RV6xx+ chips are supported */
4224         if (rdev->family <= CHIP_R600)
4225                 return;
4226
4227         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
4228                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
4229                 return;
4230
4231         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4232         if (speed_cntl & LC_CURRENT_DATA_RATE) {
4233                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
4234                 return;
4235         }
4236
4237         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
4238
4239         /* 55 nm r6xx asics */
4240         if ((rdev->family == CHIP_RV670) ||
4241             (rdev->family == CHIP_RV620) ||
4242             (rdev->family == CHIP_RV635)) {
4243                 /* advertise upconfig capability */
4244                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4245                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4246                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4247                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4248                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
4249                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
4250                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
4251                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
4252                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
4253                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4254                 } else {
4255                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4256                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4257                 }
4258         }
4259
4260         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4261         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
4262             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
4263
4264                 /* 55 nm r6xx asics */
4265                 if ((rdev->family == CHIP_RV670) ||
4266                     (rdev->family == CHIP_RV620) ||
4267                     (rdev->family == CHIP_RV635)) {
4268                         WREG32(MM_CFGREGS_CNTL, 0x8);
4269                         link_cntl2 = RREG32(0x4088);
4270                         WREG32(MM_CFGREGS_CNTL, 0);
4271                         /* not supported yet */
4272                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
4273                                 return;
4274                 }
4275
4276                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
4277                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
4278                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
4279                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
4280                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
4281                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4282
4283                 tmp = RREG32(0x541c);
4284                 WREG32(0x541c, tmp | 0x8);
4285                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
4286                 link_cntl2 = RREG16(0x4088);
4287                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
4288                 link_cntl2 |= 0x2;
4289                 WREG16(0x4088, link_cntl2);
4290                 WREG32(MM_CFGREGS_CNTL, 0);
4291
4292                 if ((rdev->family == CHIP_RV670) ||
4293                     (rdev->family == CHIP_RV620) ||
4294                     (rdev->family == CHIP_RV635)) {
4295                         training_cntl = RREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL);
4296                         training_cntl &= ~LC_POINT_7_PLUS_EN;
4297                         WREG32_PCIE_PORT(PCIE_LC_TRAINING_CNTL, training_cntl);
4298                 } else {
4299                         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4300                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
4301                         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4302                 }
4303
4304                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
4305                 speed_cntl |= LC_GEN2_EN_STRAP;
4306                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
4307
4308         } else {
4309                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
4310                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
4311                 if (1)
4312                         link_width_cntl |= LC_UPCONFIGURE_DIS;
4313                 else
4314                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
4315                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
4316         }
4317 }
4318
4319 /**
4320  * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4321  *
4322  * @rdev: radeon_device pointer
4323  *
4324  * Fetches a GPU clock counter snapshot (R6xx-cayman).
4325  * Returns the 64 bit clock counter snapshot.
4326  */
4327 uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev)
4328 {
4329         uint64_t clock;
4330
4331         mutex_lock(&rdev->gpu_clock_mutex);
4332         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4333         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
4334                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4335         mutex_unlock(&rdev->gpu_clock_mutex);
4336         return clock;
4337 }