drivers/gpu/drm/radeon/radeon_combios.c

   1 /*
   2  * Copyright 2004 ATI Technologies Inc., Markham, Ontario
   3  * Copyright 2007-8 Advanced Micro Devices, Inc.
   4  * Copyright 2008 Red Hat Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon.h"
  30 #include "atom.h"
  31
  32 #ifdef CONFIG_PPC_PMAC
  33 /* not sure which of these are needed */
  34 #include <asm/machdep.h>
  35 #include <asm/pmac_feature.h>
  36 #include <asm/prom.h>
  37 #include <asm/pci-bridge.h>
  38 #endif /* CONFIG_PPC_PMAC */
  39
  40 /* from radeon_encoder.c */
  41 extern uint32_t
  42 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
  43                       uint8_t dac);
  44 extern void radeon_link_encoder_connector(struct drm_device *dev);
  45
  46 /* from radeon_connector.c */
  47 extern void
  48 radeon_add_legacy_connector(struct drm_device *dev,
  49                             uint32_t connector_id,
  50                             uint32_t supported_device,
  51                             int connector_type,
  52                             struct radeon_i2c_bus_rec *i2c_bus);
  53
  54 /* from radeon_legacy_encoder.c */
  55 extern void
  56 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
  57                           uint32_t supported_device);
  58
  59 /* old legacy ATI BIOS routines */
  60
  61 /* COMBIOS table offsets */
  62 enum radeon_combios_table_offset {
  63         /* absolute offset tables */
  64         COMBIOS_ASIC_INIT_1_TABLE,
  65         COMBIOS_BIOS_SUPPORT_TABLE,
  66         COMBIOS_DAC_PROGRAMMING_TABLE,
  67         COMBIOS_MAX_COLOR_DEPTH_TABLE,
  68         COMBIOS_CRTC_INFO_TABLE,
  69         COMBIOS_PLL_INFO_TABLE,
  70         COMBIOS_TV_INFO_TABLE,
  71         COMBIOS_DFP_INFO_TABLE,
  72         COMBIOS_HW_CONFIG_INFO_TABLE,
  73         COMBIOS_MULTIMEDIA_INFO_TABLE,
  74         COMBIOS_TV_STD_PATCH_TABLE,
  75         COMBIOS_LCD_INFO_TABLE,
  76         COMBIOS_MOBILE_INFO_TABLE,
  77         COMBIOS_PLL_INIT_TABLE,
  78         COMBIOS_MEM_CONFIG_TABLE,
  79         COMBIOS_SAVE_MASK_TABLE,
  80         COMBIOS_HARDCODED_EDID_TABLE,
  81         COMBIOS_ASIC_INIT_2_TABLE,
  82         COMBIOS_CONNECTOR_INFO_TABLE,
  83         COMBIOS_DYN_CLK_1_TABLE,
  84         COMBIOS_RESERVED_MEM_TABLE,
  85         COMBIOS_EXT_TMDS_INFO_TABLE,
  86         COMBIOS_MEM_CLK_INFO_TABLE,
  87         COMBIOS_EXT_DAC_INFO_TABLE,
  88         COMBIOS_MISC_INFO_TABLE,
  89         COMBIOS_CRT_INFO_TABLE,
  90         COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,
  91         COMBIOS_COMPONENT_VIDEO_INFO_TABLE,
  92         COMBIOS_FAN_SPEED_INFO_TABLE,
  93         COMBIOS_OVERDRIVE_INFO_TABLE,
  94         COMBIOS_OEM_INFO_TABLE,
  95         COMBIOS_DYN_CLK_2_TABLE,
  96         COMBIOS_POWER_CONNECTOR_INFO_TABLE,
  97         COMBIOS_I2C_INFO_TABLE,
  98         /* relative offset tables */
  99         COMBIOS_ASIC_INIT_3_TABLE,      /* offset from misc info */
 100         COMBIOS_ASIC_INIT_4_TABLE,      /* offset from misc info */
 101         COMBIOS_DETECTED_MEM_TABLE,     /* offset from misc info */
 102         COMBIOS_ASIC_INIT_5_TABLE,      /* offset from misc info */
 103         COMBIOS_RAM_RESET_TABLE,        /* offset from mem config */
 104         COMBIOS_POWERPLAY_INFO_TABLE,   /* offset from mobile info */
 105         COMBIOS_GPIO_INFO_TABLE,        /* offset from mobile info */
 106         COMBIOS_LCD_DDC_INFO_TABLE,     /* offset from mobile info */
 107         COMBIOS_TMDS_POWER_TABLE,       /* offset from mobile info */
 108         COMBIOS_TMDS_POWER_ON_TABLE,    /* offset from tmds power */
 109         COMBIOS_TMDS_POWER_OFF_TABLE,   /* offset from tmds power */
 110 };
 111
 112 enum radeon_combios_ddc {
 113         DDC_NONE_DETECTED,
 114         DDC_MONID,
 115         DDC_DVI,
 116         DDC_VGA,
 117         DDC_CRT2,
 118         DDC_LCD,
 119         DDC_GPIO,
 120 };
 121
 122 enum radeon_combios_connector {
 123         CONNECTOR_NONE_LEGACY,
 124         CONNECTOR_PROPRIETARY_LEGACY,
 125         CONNECTOR_CRT_LEGACY,
 126         CONNECTOR_DVI_I_LEGACY,
 127         CONNECTOR_DVI_D_LEGACY,
 128         CONNECTOR_CTV_LEGACY,
 129         CONNECTOR_STV_LEGACY,
 130         CONNECTOR_UNSUPPORTED_LEGACY
 131 };
 132
 133 const int legacy_connector_convert[] = {
 134         DRM_MODE_CONNECTOR_Unknown,
 135         DRM_MODE_CONNECTOR_DVID,
 136         DRM_MODE_CONNECTOR_VGA,
 137         DRM_MODE_CONNECTOR_DVII,
 138         DRM_MODE_CONNECTOR_DVID,
 139         DRM_MODE_CONNECTOR_Composite,
 140         DRM_MODE_CONNECTOR_SVIDEO,
 141         DRM_MODE_CONNECTOR_Unknown,
 142 };
 143
 144 static uint16_t combios_get_table_offset(struct drm_device *dev,
 145                                          enum radeon_combios_table_offset table)
 146 {
 147         struct radeon_device *rdev = dev->dev_private;
 148         int rev;
 149         uint16_t offset = 0, check_offset;
 150
 151         switch (table) {
 152                 /* absolute offset tables */
 153         case COMBIOS_ASIC_INIT_1_TABLE:
 154                 check_offset = RBIOS16(rdev->bios_header_start + 0xc);
 155                 if (check_offset)
 156                         offset = check_offset;
 157                 break;
 158         case COMBIOS_BIOS_SUPPORT_TABLE:
 159                 check_offset = RBIOS16(rdev->bios_header_start + 0x14);
 160                 if (check_offset)
 161                         offset = check_offset;
 162                 break;
 163         case COMBIOS_DAC_PROGRAMMING_TABLE:
 164                 check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
 165                 if (check_offset)
 166                         offset = check_offset;
 167                 break;
 168         case COMBIOS_MAX_COLOR_DEPTH_TABLE:
 169                 check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
 170                 if (check_offset)
 171                         offset = check_offset;
 172                 break;
 173         case COMBIOS_CRTC_INFO_TABLE:
 174                 check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
 175                 if (check_offset)
 176                         offset = check_offset;
 177                 break;
 178         case COMBIOS_PLL_INFO_TABLE:
 179                 check_offset = RBIOS16(rdev->bios_header_start + 0x30);
 180                 if (check_offset)
 181                         offset = check_offset;
 182                 break;
 183         case COMBIOS_TV_INFO_TABLE:
 184                 check_offset = RBIOS16(rdev->bios_header_start + 0x32);
 185                 if (check_offset)
 186                         offset = check_offset;
 187                 break;
 188         case COMBIOS_DFP_INFO_TABLE:
 189                 check_offset = RBIOS16(rdev->bios_header_start + 0x34);
 190                 if (check_offset)
 191                         offset = check_offset;
 192                 break;
 193         case COMBIOS_HW_CONFIG_INFO_TABLE:
 194                 check_offset = RBIOS16(rdev->bios_header_start + 0x36);
 195                 if (check_offset)
 196                         offset = check_offset;
 197                 break;
 198         case COMBIOS_MULTIMEDIA_INFO_TABLE:
 199                 check_offset = RBIOS16(rdev->bios_header_start + 0x38);
 200                 if (check_offset)
 201                         offset = check_offset;
 202                 break;
 203         case COMBIOS_TV_STD_PATCH_TABLE:
 204                 check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
 205                 if (check_offset)
 206                         offset = check_offset;
 207                 break;
 208         case COMBIOS_LCD_INFO_TABLE:
 209                 check_offset = RBIOS16(rdev->bios_header_start + 0x40);
 210                 if (check_offset)
 211                         offset = check_offset;
 212                 break;
 213         case COMBIOS_MOBILE_INFO_TABLE:
 214                 check_offset = RBIOS16(rdev->bios_header_start + 0x42);
 215                 if (check_offset)
 216                         offset = check_offset;
 217                 break;
 218         case COMBIOS_PLL_INIT_TABLE:
 219                 check_offset = RBIOS16(rdev->bios_header_start + 0x46);
 220                 if (check_offset)
 221                         offset = check_offset;
 222                 break;
 223         case COMBIOS_MEM_CONFIG_TABLE:
 224                 check_offset = RBIOS16(rdev->bios_header_start + 0x48);
 225                 if (check_offset)
 226                         offset = check_offset;
 227                 break;
 228         case COMBIOS_SAVE_MASK_TABLE:
 229                 check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
 230                 if (check_offset)
 231                         offset = check_offset;
 232                 break;
 233         case COMBIOS_HARDCODED_EDID_TABLE:
 234                 check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
 235                 if (check_offset)
 236                         offset = check_offset;
 237                 break;
 238         case COMBIOS_ASIC_INIT_2_TABLE:
 239                 check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
 240                 if (check_offset)
 241                         offset = check_offset;
 242                 break;
 243         case COMBIOS_CONNECTOR_INFO_TABLE:
 244                 check_offset = RBIOS16(rdev->bios_header_start + 0x50);
 245                 if (check_offset)
 246                         offset = check_offset;
 247                 break;
 248         case COMBIOS_DYN_CLK_1_TABLE:
 249                 check_offset = RBIOS16(rdev->bios_header_start + 0x52);
 250                 if (check_offset)
 251                         offset = check_offset;
 252                 break;
 253         case COMBIOS_RESERVED_MEM_TABLE:
 254                 check_offset = RBIOS16(rdev->bios_header_start + 0x54);
 255                 if (check_offset)
 256                         offset = check_offset;
 257                 break;
 258         case COMBIOS_EXT_TMDS_INFO_TABLE:
 259                 check_offset = RBIOS16(rdev->bios_header_start + 0x58);
 260                 if (check_offset)
 261                         offset = check_offset;
 262                 break;
 263         case COMBIOS_MEM_CLK_INFO_TABLE:
 264                 check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
 265                 if (check_offset)
 266                         offset = check_offset;
 267                 break;
 268         case COMBIOS_EXT_DAC_INFO_TABLE:
 269                 check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
 270                 if (check_offset)
 271                         offset = check_offset;
 272                 break;
 273         case COMBIOS_MISC_INFO_TABLE:
 274                 check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
 275                 if (check_offset)
 276                         offset = check_offset;
 277                 break;
 278         case COMBIOS_CRT_INFO_TABLE:
 279                 check_offset = RBIOS16(rdev->bios_header_start + 0x60);
 280                 if (check_offset)
 281                         offset = check_offset;
 282                 break;
 283         case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
 284                 check_offset = RBIOS16(rdev->bios_header_start + 0x62);
 285                 if (check_offset)
 286                         offset = check_offset;
 287                 break;
 288         case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
 289                 check_offset = RBIOS16(rdev->bios_header_start + 0x64);
 290                 if (check_offset)
 291                         offset = check_offset;
 292                 break;
 293         case COMBIOS_FAN_SPEED_INFO_TABLE:
 294                 check_offset = RBIOS16(rdev->bios_header_start + 0x66);
 295                 if (check_offset)
 296                         offset = check_offset;
 297                 break;
 298         case COMBIOS_OVERDRIVE_INFO_TABLE:
 299                 check_offset = RBIOS16(rdev->bios_header_start + 0x68);
 300                 if (check_offset)
 301                         offset = check_offset;
 302                 break;
 303         case COMBIOS_OEM_INFO_TABLE:
 304                 check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
 305                 if (check_offset)
 306                         offset = check_offset;
 307                 break;
 308         case COMBIOS_DYN_CLK_2_TABLE:
 309                 check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
 310                 if (check_offset)
 311                         offset = check_offset;
 312                 break;
 313         case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
 314                 check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
 315                 if (check_offset)
 316                         offset = check_offset;
 317                 break;
 318         case COMBIOS_I2C_INFO_TABLE:
 319                 check_offset = RBIOS16(rdev->bios_header_start + 0x70);
 320                 if (check_offset)
 321                         offset = check_offset;
 322                 break;
 323                 /* relative offset tables */
 324         case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
 325                 check_offset =
 326                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 327                 if (check_offset) {
 328                         rev = RBIOS8(check_offset);
 329                         if (rev > 0) {
 330                                 check_offset = RBIOS16(check_offset + 0x3);
 331                                 if (check_offset)
 332                                         offset = check_offset;
 333                         }
 334                 }
 335                 break;
 336         case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */
 337                 check_offset =
 338                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 339                 if (check_offset) {
 340                         rev = RBIOS8(check_offset);
 341                         if (rev > 0) {
 342                                 check_offset = RBIOS16(check_offset + 0x5);
 343                                 if (check_offset)
 344                                         offset = check_offset;
 345                         }
 346                 }
 347                 break;
 348         case COMBIOS_DETECTED_MEM_TABLE:        /* offset from misc info */
 349                 check_offset =
 350                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 351                 if (check_offset) {
 352                         rev = RBIOS8(check_offset);
 353                         if (rev > 0) {
 354                                 check_offset = RBIOS16(check_offset + 0x7);
 355                                 if (check_offset)
 356                                         offset = check_offset;
 357                         }
 358                 }
 359                 break;
 360         case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */
 361                 check_offset =
 362                     combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);
 363                 if (check_offset) {
 364                         rev = RBIOS8(check_offset);
 365                         if (rev == 2) {
 366                                 check_offset = RBIOS16(check_offset + 0x9);
 367                                 if (check_offset)
 368                                         offset = check_offset;
 369                         }
 370                 }
 371                 break;
 372         case COMBIOS_RAM_RESET_TABLE:   /* offset from mem config */
 373                 check_offset =
 374                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
 375                 if (check_offset) {
 376                         while (RBIOS8(check_offset++));
 377                         check_offset += 2;
 378                         if (check_offset)
 379                                 offset = check_offset;
 380                 }
 381                 break;
 382         case COMBIOS_POWERPLAY_INFO_TABLE:      /* offset from mobile info */
 383                 check_offset =
 384                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 385                 if (check_offset) {
 386                         check_offset = RBIOS16(check_offset + 0x11);
 387                         if (check_offset)
 388                                 offset = check_offset;
 389                 }
 390                 break;
 391         case COMBIOS_GPIO_INFO_TABLE:   /* offset from mobile info */
 392                 check_offset =
 393                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 394                 if (check_offset) {
 395                         check_offset = RBIOS16(check_offset + 0x13);
 396                         if (check_offset)
 397                                 offset = check_offset;
 398                 }
 399                 break;
 400         case COMBIOS_LCD_DDC_INFO_TABLE:        /* offset from mobile info */
 401                 check_offset =
 402                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 403                 if (check_offset) {
 404                         check_offset = RBIOS16(check_offset + 0x15);
 405                         if (check_offset)
 406                                 offset = check_offset;
 407                 }
 408                 break;
 409         case COMBIOS_TMDS_POWER_TABLE:  /* offset from mobile info */
 410                 check_offset =
 411                     combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);
 412                 if (check_offset) {
 413                         check_offset = RBIOS16(check_offset + 0x17);
 414                         if (check_offset)
 415                                 offset = check_offset;
 416                 }
 417                 break;
 418         case COMBIOS_TMDS_POWER_ON_TABLE:       /* offset from tmds power */
 419                 check_offset =
 420                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 421                 if (check_offset) {
 422                         check_offset = RBIOS16(check_offset + 0x2);
 423                         if (check_offset)
 424                                 offset = check_offset;
 425                 }
 426                 break;
 427         case COMBIOS_TMDS_POWER_OFF_TABLE:      /* offset from tmds power */
 428                 check_offset =
 429                     combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);
 430                 if (check_offset) {
 431                         check_offset = RBIOS16(check_offset + 0x4);
 432                         if (check_offset)
 433                                 offset = check_offset;
 434                 }
 435                 break;
 436         default:
 437                 break;
 438         }
 439
 440         return offset;
 441
 442 }
 443
 444 struct radeon_i2c_bus_rec combios_setup_i2c_bus(int ddc_line)
 445 {
 446         struct radeon_i2c_bus_rec i2c;
 447
 448         i2c.mask_clk_mask = RADEON_GPIO_EN_1;
 449         i2c.mask_data_mask = RADEON_GPIO_EN_0;
 450         i2c.a_clk_mask = RADEON_GPIO_A_1;
 451         i2c.a_data_mask = RADEON_GPIO_A_0;
 452         i2c.put_clk_mask = RADEON_GPIO_EN_1;
 453         i2c.put_data_mask = RADEON_GPIO_EN_0;
 454         i2c.get_clk_mask = RADEON_GPIO_Y_1;
 455         i2c.get_data_mask = RADEON_GPIO_Y_0;
 456         if ((ddc_line == RADEON_LCD_GPIO_MASK) ||
 457             (ddc_line == RADEON_MDGPIO_EN_REG)) {
 458                 i2c.mask_clk_reg = ddc_line;
 459                 i2c.mask_data_reg = ddc_line;
 460                 i2c.a_clk_reg = ddc_line;
 461                 i2c.a_data_reg = ddc_line;
 462                 i2c.put_clk_reg = ddc_line;
 463                 i2c.put_data_reg = ddc_line;
 464                 i2c.get_clk_reg = ddc_line + 4;
 465                 i2c.get_data_reg = ddc_line + 4;
 466         } else {
 467                 i2c.mask_clk_reg = ddc_line;
 468                 i2c.mask_data_reg = ddc_line;
 469                 i2c.a_clk_reg = ddc_line;
 470                 i2c.a_data_reg = ddc_line;
 471                 i2c.put_clk_reg = ddc_line;
 472                 i2c.put_data_reg = ddc_line;
 473                 i2c.get_clk_reg = ddc_line;
 474                 i2c.get_data_reg = ddc_line;
 475         }
 476
 477         if (ddc_line)
 478                 i2c.valid = true;
 479         else
 480                 i2c.valid = false;
 481
 482         return i2c;
 483 }
 484
 485 bool radeon_combios_get_clock_info(struct drm_device *dev)
 486 {
 487         struct radeon_device *rdev = dev->dev_private;
 488         uint16_t pll_info;
 489         struct radeon_pll *p1pll = &rdev->clock.p1pll;
 490         struct radeon_pll *p2pll = &rdev->clock.p2pll;
 491         struct radeon_pll *spll = &rdev->clock.spll;
 492         struct radeon_pll *mpll = &rdev->clock.mpll;
 493         int8_t rev;
 494         uint16_t sclk, mclk;
 495
 496         if (rdev->bios == NULL)
 497                 return NULL;
 498
 499         pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);
 500         if (pll_info) {
 501                 rev = RBIOS8(pll_info);
 502
 503                 /* pixel clocks */
 504                 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
 505                 p1pll->reference_div = RBIOS16(pll_info + 0x10);
 506                 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
 507                 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
 508
 509                 if (rev > 9) {
 510                         p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
 511                         p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
 512                 } else {
 513                         p1pll->pll_in_min = 40;
 514                         p1pll->pll_in_max = 500;
 515                 }
 516                 *p2pll = *p1pll;
 517
 518                 /* system clock */
 519                 spll->reference_freq = RBIOS16(pll_info + 0x1a);
 520                 spll->reference_div = RBIOS16(pll_info + 0x1c);
 521                 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
 522                 spll->pll_out_max = RBIOS32(pll_info + 0x22);
 523
 524                 if (rev > 10) {
 525                         spll->pll_in_min = RBIOS32(pll_info + 0x48);
 526                         spll->pll_in_max = RBIOS32(pll_info + 0x4c);
 527                 } else {
 528                         /* ??? */
 529                         spll->pll_in_min = 40;
 530                         spll->pll_in_max = 500;
 531                 }
 532
 533                 /* memory clock */
 534                 mpll->reference_freq = RBIOS16(pll_info + 0x26);
 535                 mpll->reference_div = RBIOS16(pll_info + 0x28);
 536                 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
 537                 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
 538
 539                 if (rev > 10) {
 540                         mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
 541                         mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
 542                 } else {
 543                         /* ??? */
 544                         mpll->pll_in_min = 40;
 545                         mpll->pll_in_max = 500;
 546                 }
 547
 548                 /* default sclk/mclk */
 549                 sclk = RBIOS16(pll_info + 0xa);
 550                 mclk = RBIOS16(pll_info + 0x8);
 551                 if (sclk == 0)
 552                         sclk = 200 * 100;
 553                 if (mclk == 0)
 554                         mclk = 200 * 100;
 555
 556                 rdev->clock.default_sclk = sclk;
 557                 rdev->clock.default_mclk = mclk;
 558
 559                 return true;
 560         }
 561         return false;
 562 }
 563
 564 struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
 565                                                                        radeon_encoder
 566                                                                        *encoder)
 567 {
 568         struct drm_device *dev = encoder->base.dev;
 569         struct radeon_device *rdev = dev->dev_private;
 570         uint16_t dac_info;
 571         uint8_t rev, bg, dac;
 572         struct radeon_encoder_primary_dac *p_dac = NULL;
 573
 574         if (rdev->bios == NULL)
 575                 return NULL;
 576
 577         /* check CRT table */
 578         dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 579         if (dac_info) {
 580                 p_dac =
 581                     kzalloc(sizeof(struct radeon_encoder_primary_dac),
 582                             GFP_KERNEL);
 583
 584                 if (!p_dac)
 585                         return NULL;
 586
 587                 rev = RBIOS8(dac_info) & 0x3;
 588                 if (rev < 2) {
 589                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 590                         dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;
 591                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 592                 } else {
 593                         bg = RBIOS8(dac_info + 0x2) & 0xf;
 594                         dac = RBIOS8(dac_info + 0x3) & 0xf;
 595                         p_dac->ps2_pdac_adj = (bg << 8) | (dac);
 596                 }
 597
 598         }
 599
 600         return p_dac;
 601 }
 602
 603 static enum radeon_tv_std
 604 radeon_combios_get_tv_info(struct radeon_encoder *encoder)
 605 {
 606         struct drm_device *dev = encoder->base.dev;
 607         struct radeon_device *rdev = dev->dev_private;
 608         uint16_t tv_info;
 609         enum radeon_tv_std tv_std = TV_STD_NTSC;
 610
 611         tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 612         if (tv_info) {
 613                 if (RBIOS8(tv_info + 6) == 'T') {
 614                         switch (RBIOS8(tv_info + 7) & 0xf) {
 615                         case 1:
 616                                 tv_std = TV_STD_NTSC;
 617                                 DRM_INFO("Default TV standard: NTSC\n");
 618                                 break;
 619                         case 2:
 620                                 tv_std = TV_STD_PAL;
 621                                 DRM_INFO("Default TV standard: PAL\n");
 622                                 break;
 623                         case 3:
 624                                 tv_std = TV_STD_PAL_M;
 625                                 DRM_INFO("Default TV standard: PAL-M\n");
 626                                 break;
 627                         case 4:
 628                                 tv_std = TV_STD_PAL_60;
 629                                 DRM_INFO("Default TV standard: PAL-60\n");
 630                                 break;
 631                         case 5:
 632                                 tv_std = TV_STD_NTSC_J;
 633                                 DRM_INFO("Default TV standard: NTSC-J\n");
 634                                 break;
 635                         case 6:
 636                                 tv_std = TV_STD_SCART_PAL;
 637                                 DRM_INFO("Default TV standard: SCART-PAL\n");
 638                                 break;
 639                         default:
 640                                 tv_std = TV_STD_NTSC;
 641                                 DRM_INFO
 642                                     ("Unknown TV standard; defaulting to NTSC\n");
 643                                 break;
 644                         }
 645
 646                         switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {
 647                         case 0:
 648                                 DRM_INFO("29.498928713 MHz TV ref clk\n");
 649                                 break;
 650                         case 1:
 651                                 DRM_INFO("28.636360000 MHz TV ref clk\n");
 652                                 break;
 653                         case 2:
 654                                 DRM_INFO("14.318180000 MHz TV ref clk\n");
 655                                 break;
 656                         case 3:
 657                                 DRM_INFO("27.000000000 MHz TV ref clk\n");
 658                                 break;
 659                         default:
 660                                 break;
 661                         }
 662                 }
 663         }
 664         return tv_std;
 665 }
 666
 667 static const uint32_t default_tvdac_adj[CHIP_LAST] = {
 668         0x00000000,             /* r100  */
 669         0x00280000,             /* rv100 */
 670         0x00000000,             /* rs100 */
 671         0x00880000,             /* rv200 */
 672         0x00000000,             /* rs200 */
 673         0x00000000,             /* r200  */
 674         0x00770000,             /* rv250 */
 675         0x00290000,             /* rs300 */
 676         0x00560000,             /* rv280 */
 677         0x00780000,             /* r300  */
 678         0x00770000,             /* r350  */
 679         0x00780000,             /* rv350 */
 680         0x00780000,             /* rv380 */
 681         0x01080000,             /* r420  */
 682         0x01080000,             /* r423  */
 683         0x01080000,             /* rv410 */
 684         0x00780000,             /* rs400 */
 685         0x00780000,             /* rs480 */
 686 };
 687
 688 static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,
 689                                                      struct radeon_encoder_tv_dac *tv_dac)
 690 {
 691         tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
 692         if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
 693                 tv_dac->ps2_tvdac_adj = 0x00880000;
 694         tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 695         tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 696         return;
 697 }
 698
 699 struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
 700                                                              radeon_encoder
 701                                                              *encoder)
 702 {
 703         struct drm_device *dev = encoder->base.dev;
 704         struct radeon_device *rdev = dev->dev_private;
 705         uint16_t dac_info;
 706         uint8_t rev, bg, dac;
 707         struct radeon_encoder_tv_dac *tv_dac = NULL;
 708         int found = 0;
 709
 710         tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 711         if (!tv_dac)
 712                 return NULL;
 713
 714         if (rdev->bios == NULL)
 715                 goto out;
 716
 717         /* first check TV table */
 718         dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
 719         if (dac_info) {
 720                 rev = RBIOS8(dac_info + 0x3);
 721                 if (rev > 4) {
 722                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 723                         dac = RBIOS8(dac_info + 0xd) & 0xf;
 724                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 725
 726                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 727                         dac = RBIOS8(dac_info + 0xf) & 0xf;
 728                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 729
 730                         bg = RBIOS8(dac_info + 0x10) & 0xf;
 731                         dac = RBIOS8(dac_info + 0x11) & 0xf;
 732                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 733                         found = 1;
 734                 } else if (rev > 1) {
 735                         bg = RBIOS8(dac_info + 0xc) & 0xf;
 736                         dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;
 737                         tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
 738
 739                         bg = RBIOS8(dac_info + 0xd) & 0xf;
 740                         dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;
 741                         tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
 742
 743                         bg = RBIOS8(dac_info + 0xe) & 0xf;
 744                         dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;
 745                         tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
 746                         found = 1;
 747                 }
 748                 tv_dac->tv_std = radeon_combios_get_tv_info(encoder);
 749         }
 750         if (!found) {
 751                 /* then check CRT table */
 752                 dac_info =
 753                     combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
 754                 if (dac_info) {
 755                         rev = RBIOS8(dac_info) & 0x3;
 756                         if (rev < 2) {
 757                                 bg = RBIOS8(dac_info + 0x3) & 0xf;
 758                                 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;
 759                                 tv_dac->ps2_tvdac_adj =
 760                                     (bg << 16) | (dac << 20);
 761                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 762                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 763                                 found = 1;
 764                         } else {
 765                                 bg = RBIOS8(dac_info + 0x4) & 0xf;
 766                                 dac = RBIOS8(dac_info + 0x5) & 0xf;
 767                                 tv_dac->ps2_tvdac_adj =
 768                                     (bg << 16) | (dac << 20);
 769                                 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
 770                                 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
 771                                 found = 1;
 772                         }
 773                 } else {
 774                         DRM_INFO("No TV DAC info found in BIOS\n");
 775                 }
 776         }
 777
 778 out:
 779         if (!found) /* fallback to defaults */
 780                 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);
 781
 782         return tv_dac;
 783 }
 784
 785 static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
 786                                                                          radeon_device
 787                                                                          *rdev)
 788 {
 789         struct radeon_encoder_lvds *lvds = NULL;
 790         uint32_t fp_vert_stretch, fp_horz_stretch;
 791         uint32_t ppll_div_sel, ppll_val;
 792         uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 793
 794         lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 795
 796         if (!lvds)
 797                 return NULL;
 798
 799         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);
 800         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);
 801
 802         /* These should be fail-safe defaults, fingers crossed */
 803         lvds->panel_pwr_delay = 200;
 804         lvds->panel_vcc_delay = 2000;
 805
 806         lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 807         lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
 808         lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
 809
 810         if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
 811                 lvds->native_mode.vdisplay =
 812                     ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
 813                      RADEON_VERT_PANEL_SHIFT) + 1;
 814         else
 815                 lvds->native_mode.vdisplay =
 816                     (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
 817
 818         if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
 819                 lvds->native_mode.hdisplay =
 820                     (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
 821                       RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
 822         else
 823                 lvds->native_mode.hdisplay =
 824                     ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
 825
 826         if ((lvds->native_mode.hdisplay < 640) ||
 827             (lvds->native_mode.vdisplay < 480)) {
 828                 lvds->native_mode.hdisplay = 640;
 829                 lvds->native_mode.vdisplay = 480;
 830         }
 831
 832         ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
 833         ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);
 834         if ((ppll_val & 0x000707ff) == 0x1bb)
 835                 lvds->use_bios_dividers = false;
 836         else {
 837                 lvds->panel_ref_divider =
 838                     RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;
 839                 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
 840                 lvds->panel_fb_divider = ppll_val & 0x7ff;
 841
 842                 if ((lvds->panel_ref_divider != 0) &&
 843                     (lvds->panel_fb_divider > 3))
 844                         lvds->use_bios_dividers = true;
 845         }
 846         lvds->panel_vcc_delay = 200;
 847
 848         DRM_INFO("Panel info derived from registers\n");
 849         DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
 850                  lvds->native_mode.vdisplay);
 851
 852         return lvds;
 853 }
 854
 855 struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
 856                                                          *encoder)
 857 {
 858         struct drm_device *dev = encoder->base.dev;
 859         struct radeon_device *rdev = dev->dev_private;
 860         uint16_t lcd_info;
 861         uint32_t panel_setup;
 862         char stmp[30];
 863         int tmp, i;
 864         struct radeon_encoder_lvds *lvds = NULL;
 865
 866         if (rdev->bios == NULL) {
 867                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
 868                 goto out;
 869         }
 870
 871         lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 872
 873         if (lcd_info) {
 874                 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 875
 876                 if (!lvds)
 877                         return NULL;
 878
 879                 for (i = 0; i < 24; i++)
 880                         stmp[i] = RBIOS8(lcd_info + i + 1);
 881                 stmp[24] = 0;
 882
 883                 DRM_INFO("Panel ID String: %s\n", stmp);
 884
 885                 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
 886                 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
 887
 888                 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
 889                          lvds->native_mode.vdisplay);
 890
 891                 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
 892                 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
 893                         lvds->panel_vcc_delay = 2000;
 894
 895                 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
 896                 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
 897                 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
 898
 899                 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
 900                 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
 901                 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
 902                 if ((lvds->panel_ref_divider != 0) &&
 903                     (lvds->panel_fb_divider > 3))
 904                         lvds->use_bios_dividers = true;
 905
 906                 panel_setup = RBIOS32(lcd_info + 0x39);
 907                 lvds->lvds_gen_cntl = 0xff00;
 908                 if (panel_setup & 0x1)
 909                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
 910
 911                 if ((panel_setup >> 4) & 0x1)
 912                         lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
 913
 914                 switch ((panel_setup >> 8) & 0x7) {
 915                 case 0:
 916                         lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
 917                         break;
 918                 case 1:
 919                         lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
 920                         break;
 921                 case 2:
 922                         lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
 923                         break;
 924                 default:
 925                         break;
 926                 }
 927
 928                 if ((panel_setup >> 16) & 0x1)
 929                         lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
 930
 931                 if ((panel_setup >> 17) & 0x1)
 932                         lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
 933
 934                 if ((panel_setup >> 18) & 0x1)
 935                         lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
 936
 937                 if ((panel_setup >> 23) & 0x1)
 938                         lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
 939
 940                 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
 941
 942                 for (i = 0; i < 32; i++) {
 943                         tmp = RBIOS16(lcd_info + 64 + i * 2);
 944                         if (tmp == 0)
 945                                 break;
 946
 947                         if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
 948                             (RBIOS16(tmp + 2) ==
 949                              lvds->native_mode.vdisplay)) {
 950                                 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
 951                                 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
 952                                 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
 953                                                                RBIOS16(tmp + 21)) * 8;
 954
 955                                 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
 956                                 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
 957                                 lvds->native_mode.vsync_end =
 958                                         ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
 959                                         (RBIOS16(tmp + 28) & 0x7ff);
 960
 961                                 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
 962                                 lvds->native_mode.flags = 0;
 963                                 /* set crtc values */
 964                                 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
 965
 966                         }
 967                 }
 968         } else {
 969                 DRM_INFO("No panel info found in BIOS\n");
 970                 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
 971         }
 972 out:
 973         if (lvds)
 974                 encoder->native_mode = lvds->native_mode;
 975         return lvds;
 976 }
 977
 978 static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {
 979         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R100  */
 980         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV100 */
 981         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS100 */
 982         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RV200 */
 983         {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_RS200 */
 984         {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}},  /* CHIP_R200  */
 985         {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}},  /* CHIP_RV250 */
 986         {{0, 0}, {0, 0}, {0, 0}, {0, 0}},       /* CHIP_RS300 */
 987         {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}},    /* CHIP_RV280 */
 988         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R300  */
 989         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R350  */
 990         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV350 */
 991         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RV380 */
 992         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R420  */
 993         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_R423  */
 994         {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}},        /* CHIP_RV410 */
 995         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS400 */
 996         {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}},      /* CHIP_RS480 */
 997 };
 998
 999 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1000                                             struct radeon_encoder_int_tmds *tmds)
1001 {
1002         struct drm_device *dev = encoder->base.dev;
1003         struct radeon_device *rdev = dev->dev_private;
1004         int i;
1005
1006         for (i = 0; i < 4; i++) {
1007                 tmds->tmds_pll[i].value =
1008                         default_tmds_pll[rdev->family][i].value;
1009                 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1010         }
1011
1012         return true;
1013 }
1014
1015 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1016                                               struct radeon_encoder_int_tmds *tmds)
1017 {
1018         struct drm_device *dev = encoder->base.dev;
1019         struct radeon_device *rdev = dev->dev_private;
1020         uint16_t tmds_info;
1021         int i, n;
1022         uint8_t ver;
1023
1024         if (rdev->bios == NULL)
1025                 return false;
1026
1027         tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1028
1029         if (tmds_info) {
1030
1031                 ver = RBIOS8(tmds_info);
1032                 DRM_INFO("DFP table revision: %d\n", ver);
1033                 if (ver == 3) {
1034                         n = RBIOS8(tmds_info + 5) + 1;
1035                         if (n > 4)
1036                                 n = 4;
1037                         for (i = 0; i < n; i++) {
1038                                 tmds->tmds_pll[i].value =
1039                                     RBIOS32(tmds_info + i * 10 + 0x08);
1040                                 tmds->tmds_pll[i].freq =
1041                                     RBIOS16(tmds_info + i * 10 + 0x10);
1042                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1043                                           tmds->tmds_pll[i].freq,
1044                                           tmds->tmds_pll[i].value);
1045                         }
1046                 } else if (ver == 4) {
1047                         int stride = 0;
1048                         n = RBIOS8(tmds_info + 5) + 1;
1049                         if (n > 4)
1050                                 n = 4;
1051                         for (i = 0; i < n; i++) {
1052                                 tmds->tmds_pll[i].value =
1053                                     RBIOS32(tmds_info + stride + 0x08);
1054                                 tmds->tmds_pll[i].freq =
1055                                     RBIOS16(tmds_info + stride + 0x10);
1056                                 if (i == 0)
1057                                         stride += 10;
1058                                 else
1059                                         stride += 6;
1060                                 DRM_DEBUG("TMDS PLL From COMBIOS %u %x\n",
1061                                           tmds->tmds_pll[i].freq,
1062                                           tmds->tmds_pll[i].value);
1063                         }
1064                 }
1065         } else
1066                 DRM_INFO("No TMDS info found in BIOS\n");
1067         return true;
1068 }
1069
1070 struct radeon_encoder_int_tmds *radeon_combios_get_tmds_info(struct radeon_encoder *encoder)
1071 {
1072         struct radeon_encoder_int_tmds *tmds = NULL;
1073         bool ret;
1074
1075         tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1076
1077         if (!tmds)
1078                 return NULL;
1079
1080         ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1081         if (ret == false)
1082                 radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1083
1084         return tmds;
1085 }
1086
1087 void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder)
1088 {
1089         struct drm_device *dev = encoder->base.dev;
1090         struct radeon_device *rdev = dev->dev_private;
1091         uint16_t ext_tmds_info;
1092         uint8_t ver;
1093
1094         if (rdev->bios == NULL)
1095                 return;
1096
1097         ext_tmds_info =
1098             combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1099         if (ext_tmds_info) {
1100                 ver = RBIOS8(ext_tmds_info);
1101                 DRM_INFO("External TMDS Table revision: %d\n", ver);
1102                 // TODO
1103         }
1104 }
1105
1106 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1107 {
1108         struct radeon_device *rdev = dev->dev_private;
1109         struct radeon_i2c_bus_rec ddc_i2c;
1110
1111         rdev->mode_info.connector_table = radeon_connector_table;
1112         if (rdev->mode_info.connector_table == CT_NONE) {
1113 #ifdef CONFIG_PPC_PMAC
1114                 if (machine_is_compatible("PowerBook3,3")) {
1115                         /* powerbook with VGA */
1116                         rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1117                 } else if (machine_is_compatible("PowerBook3,4") ||
1118                            machine_is_compatible("PowerBook3,5")) {
1119                         /* powerbook with internal tmds */
1120                         rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1121                 } else if (machine_is_compatible("PowerBook5,1") ||
1122                            machine_is_compatible("PowerBook5,2") ||
1123                            machine_is_compatible("PowerBook5,3") ||
1124                            machine_is_compatible("PowerBook5,4") ||
1125                            machine_is_compatible("PowerBook5,5")) {
1126                         /* powerbook with external single link tmds (sil164) */
1127                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1128                 } else if (machine_is_compatible("PowerBook5,6")) {
1129                         /* powerbook with external dual or single link tmds */
1130                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1131                 } else if (machine_is_compatible("PowerBook5,7") ||
1132                            machine_is_compatible("PowerBook5,8") ||
1133                            machine_is_compatible("PowerBook5,9")) {
1134                         /* PowerBook6,2 ? */
1135                         /* powerbook with external dual link tmds (sil1178?) */
1136                         rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1137                 } else if (machine_is_compatible("PowerBook4,1") ||
1138                            machine_is_compatible("PowerBook4,2") ||
1139                            machine_is_compatible("PowerBook4,3") ||
1140                            machine_is_compatible("PowerBook6,3") ||
1141                            machine_is_compatible("PowerBook6,5") ||
1142                            machine_is_compatible("PowerBook6,7")) {
1143                         /* ibook */
1144                         rdev->mode_info.connector_table = CT_IBOOK;
1145                 } else if (machine_is_compatible("PowerMac4,4")) {
1146                         /* emac */
1147                         rdev->mode_info.connector_table = CT_EMAC;
1148                 } else if (machine_is_compatible("PowerMac10,1")) {
1149                         /* mini with internal tmds */
1150                         rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1151                 } else if (machine_is_compatible("PowerMac10,2")) {
1152                         /* mini with external tmds */
1153                         rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1154                 } else if (machine_is_compatible("PowerMac12,1")) {
1155                         /* PowerMac8,1 ? */
1156                         /* imac g5 isight */
1157                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1158                 } else
1159 #endif /* CONFIG_PPC_PMAC */
1160                         rdev->mode_info.connector_table = CT_GENERIC;
1161         }
1162
1163         switch (rdev->mode_info.connector_table) {
1164         case CT_GENERIC:
1165                 DRM_INFO("Connector Table: %d (generic)\n",
1166                          rdev->mode_info.connector_table);
1167                 /* these are the most common settings */
1168                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1169                         /* VGA - primary dac */
1170                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1171                         radeon_add_legacy_encoder(dev,
1172                                                   radeon_get_encoder_id(dev,
1173                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1174                                                                         1),
1175                                                   ATOM_DEVICE_CRT1_SUPPORT);
1176                         radeon_add_legacy_connector(dev, 0,
1177                                                     ATOM_DEVICE_CRT1_SUPPORT,
1178                                                     DRM_MODE_CONNECTOR_VGA,
1179                                                     &ddc_i2c);
1180                 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1181                         /* LVDS */
1182                         ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
1183                         radeon_add_legacy_encoder(dev,
1184                                                   radeon_get_encoder_id(dev,
1185                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1186                                                                         0),
1187                                                   ATOM_DEVICE_LCD1_SUPPORT);
1188                         radeon_add_legacy_connector(dev, 0,
1189                                                     ATOM_DEVICE_LCD1_SUPPORT,
1190                                                     DRM_MODE_CONNECTOR_LVDS,
1191                                                     &ddc_i2c);
1192
1193                         /* VGA - primary dac */
1194                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1195                         radeon_add_legacy_encoder(dev,
1196                                                   radeon_get_encoder_id(dev,
1197                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1198                                                                         1),
1199                                                   ATOM_DEVICE_CRT1_SUPPORT);
1200                         radeon_add_legacy_connector(dev, 1,
1201                                                     ATOM_DEVICE_CRT1_SUPPORT,
1202                                                     DRM_MODE_CONNECTOR_VGA,
1203                                                     &ddc_i2c);
1204                 } else {
1205                         /* DVI-I - tv dac, int tmds */
1206                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1207                         radeon_add_legacy_encoder(dev,
1208                                                   radeon_get_encoder_id(dev,
1209                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1210                                                                         0),
1211                                                   ATOM_DEVICE_DFP1_SUPPORT);
1212                         radeon_add_legacy_encoder(dev,
1213                                                   radeon_get_encoder_id(dev,
1214                                                                         ATOM_DEVICE_CRT2_SUPPORT,
1215                                                                         2),
1216                                                   ATOM_DEVICE_CRT2_SUPPORT);
1217                         radeon_add_legacy_connector(dev, 0,
1218                                                     ATOM_DEVICE_DFP1_SUPPORT |
1219                                                     ATOM_DEVICE_CRT2_SUPPORT,
1220                                                     DRM_MODE_CONNECTOR_DVII,
1221                                                     &ddc_i2c);
1222
1223                         /* VGA - primary dac */
1224                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1225                         radeon_add_legacy_encoder(dev,
1226                                                   radeon_get_encoder_id(dev,
1227                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1228                                                                         1),
1229                                                   ATOM_DEVICE_CRT1_SUPPORT);
1230                         radeon_add_legacy_connector(dev, 1,
1231                                                     ATOM_DEVICE_CRT1_SUPPORT,
1232                                                     DRM_MODE_CONNECTOR_VGA,
1233                                                     &ddc_i2c);
1234                 }
1235
1236                 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1237                         /* TV - tv dac */
1238                         radeon_add_legacy_encoder(dev,
1239                                                   radeon_get_encoder_id(dev,
1240                                                                         ATOM_DEVICE_TV1_SUPPORT,
1241                                                                         2),
1242                                                   ATOM_DEVICE_TV1_SUPPORT);
1243                         radeon_add_legacy_connector(dev, 2,
1244                                                     ATOM_DEVICE_TV1_SUPPORT,
1245                                                     DRM_MODE_CONNECTOR_SVIDEO,
1246                                                     &ddc_i2c);
1247                 }
1248                 break;
1249         case CT_IBOOK:
1250                 DRM_INFO("Connector Table: %d (ibook)\n",
1251                          rdev->mode_info.connector_table);
1252                 /* LVDS */
1253                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1254                 radeon_add_legacy_encoder(dev,
1255                                           radeon_get_encoder_id(dev,
1256                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1257                                                                 0),
1258                                           ATOM_DEVICE_LCD1_SUPPORT);
1259                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1260                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1261                 /* VGA - TV DAC */
1262                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1263                 radeon_add_legacy_encoder(dev,
1264                                           radeon_get_encoder_id(dev,
1265                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1266                                                                 2),
1267                                           ATOM_DEVICE_CRT2_SUPPORT);
1268                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1269                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1270                 /* TV - TV DAC */
1271                 radeon_add_legacy_encoder(dev,
1272                                           radeon_get_encoder_id(dev,
1273                                                                 ATOM_DEVICE_TV1_SUPPORT,
1274                                                                 2),
1275                                           ATOM_DEVICE_TV1_SUPPORT);
1276                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1277                                             DRM_MODE_CONNECTOR_SVIDEO,
1278                                             &ddc_i2c);
1279                 break;
1280         case CT_POWERBOOK_EXTERNAL:
1281                 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
1282                          rdev->mode_info.connector_table);
1283                 /* LVDS */
1284                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1285                 radeon_add_legacy_encoder(dev,
1286                                           radeon_get_encoder_id(dev,
1287                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1288                                                                 0),
1289                                           ATOM_DEVICE_LCD1_SUPPORT);
1290                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1291                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1292                 /* DVI-I - primary dac, ext tmds */
1293                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1294                 radeon_add_legacy_encoder(dev,
1295                                           radeon_get_encoder_id(dev,
1296                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1297                                                                 0),
1298                                           ATOM_DEVICE_DFP2_SUPPORT);
1299                 radeon_add_legacy_encoder(dev,
1300                                           radeon_get_encoder_id(dev,
1301                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1302                                                                 1),
1303                                           ATOM_DEVICE_CRT1_SUPPORT);
1304                 radeon_add_legacy_connector(dev, 1,
1305                                             ATOM_DEVICE_DFP2_SUPPORT |
1306                                             ATOM_DEVICE_CRT1_SUPPORT,
1307                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1308                 /* TV - TV DAC */
1309                 radeon_add_legacy_encoder(dev,
1310                                           radeon_get_encoder_id(dev,
1311                                                                 ATOM_DEVICE_TV1_SUPPORT,
1312                                                                 2),
1313                                           ATOM_DEVICE_TV1_SUPPORT);
1314                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1315                                             DRM_MODE_CONNECTOR_SVIDEO,
1316                                             &ddc_i2c);
1317                 break;
1318         case CT_POWERBOOK_INTERNAL:
1319                 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
1320                          rdev->mode_info.connector_table);
1321                 /* LVDS */
1322                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1323                 radeon_add_legacy_encoder(dev,
1324                                           radeon_get_encoder_id(dev,
1325                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1326                                                                 0),
1327                                           ATOM_DEVICE_LCD1_SUPPORT);
1328                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1329                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1330                 /* DVI-I - primary dac, int tmds */
1331                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1332                 radeon_add_legacy_encoder(dev,
1333                                           radeon_get_encoder_id(dev,
1334                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1335                                                                 0),
1336                                           ATOM_DEVICE_DFP1_SUPPORT);
1337                 radeon_add_legacy_encoder(dev,
1338                                           radeon_get_encoder_id(dev,
1339                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1340                                                                 1),
1341                                           ATOM_DEVICE_CRT1_SUPPORT);
1342                 radeon_add_legacy_connector(dev, 1,
1343                                             ATOM_DEVICE_DFP1_SUPPORT |
1344                                             ATOM_DEVICE_CRT1_SUPPORT,
1345                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1346                 /* TV - TV DAC */
1347                 radeon_add_legacy_encoder(dev,
1348                                           radeon_get_encoder_id(dev,
1349                                                                 ATOM_DEVICE_TV1_SUPPORT,
1350                                                                 2),
1351                                           ATOM_DEVICE_TV1_SUPPORT);
1352                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1353                                             DRM_MODE_CONNECTOR_SVIDEO,
1354                                             &ddc_i2c);
1355                 break;
1356         case CT_POWERBOOK_VGA:
1357                 DRM_INFO("Connector Table: %d (powerbook vga)\n",
1358                          rdev->mode_info.connector_table);
1359                 /* LVDS */
1360                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1361                 radeon_add_legacy_encoder(dev,
1362                                           radeon_get_encoder_id(dev,
1363                                                                 ATOM_DEVICE_LCD1_SUPPORT,
1364                                                                 0),
1365                                           ATOM_DEVICE_LCD1_SUPPORT);
1366                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1367                                             DRM_MODE_CONNECTOR_LVDS, &ddc_i2c);
1368                 /* VGA - primary dac */
1369                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1370                 radeon_add_legacy_encoder(dev,
1371                                           radeon_get_encoder_id(dev,
1372                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1373                                                                 1),
1374                                           ATOM_DEVICE_CRT1_SUPPORT);
1375                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1376                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1377                 /* TV - TV DAC */
1378                 radeon_add_legacy_encoder(dev,
1379                                           radeon_get_encoder_id(dev,
1380                                                                 ATOM_DEVICE_TV1_SUPPORT,
1381                                                                 2),
1382                                           ATOM_DEVICE_TV1_SUPPORT);
1383                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1384                                             DRM_MODE_CONNECTOR_SVIDEO,
1385                                             &ddc_i2c);
1386                 break;
1387         case CT_MINI_EXTERNAL:
1388                 DRM_INFO("Connector Table: %d (mini external tmds)\n",
1389                          rdev->mode_info.connector_table);
1390                 /* DVI-I - tv dac, ext tmds */
1391                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1392                 radeon_add_legacy_encoder(dev,
1393                                           radeon_get_encoder_id(dev,
1394                                                                 ATOM_DEVICE_DFP2_SUPPORT,
1395                                                                 0),
1396                                           ATOM_DEVICE_DFP2_SUPPORT);
1397                 radeon_add_legacy_encoder(dev,
1398                                           radeon_get_encoder_id(dev,
1399                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1400                                                                 2),
1401                                           ATOM_DEVICE_CRT2_SUPPORT);
1402                 radeon_add_legacy_connector(dev, 0,
1403                                             ATOM_DEVICE_DFP2_SUPPORT |
1404                                             ATOM_DEVICE_CRT2_SUPPORT,
1405                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1406                 /* TV - TV DAC */
1407                 radeon_add_legacy_encoder(dev,
1408                                           radeon_get_encoder_id(dev,
1409                                                                 ATOM_DEVICE_TV1_SUPPORT,
1410                                                                 2),
1411                                           ATOM_DEVICE_TV1_SUPPORT);
1412                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1413                                             DRM_MODE_CONNECTOR_SVIDEO,
1414                                             &ddc_i2c);
1415                 break;
1416         case CT_MINI_INTERNAL:
1417                 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
1418                          rdev->mode_info.connector_table);
1419                 /* DVI-I - tv dac, int tmds */
1420                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1421                 radeon_add_legacy_encoder(dev,
1422                                           radeon_get_encoder_id(dev,
1423                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1424                                                                 0),
1425                                           ATOM_DEVICE_DFP1_SUPPORT);
1426                 radeon_add_legacy_encoder(dev,
1427                                           radeon_get_encoder_id(dev,
1428                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1429                                                                 2),
1430                                           ATOM_DEVICE_CRT2_SUPPORT);
1431                 radeon_add_legacy_connector(dev, 0,
1432                                             ATOM_DEVICE_DFP1_SUPPORT |
1433                                             ATOM_DEVICE_CRT2_SUPPORT,
1434                                             DRM_MODE_CONNECTOR_DVII, &ddc_i2c);
1435                 /* TV - TV DAC */
1436                 radeon_add_legacy_encoder(dev,
1437                                           radeon_get_encoder_id(dev,
1438                                                                 ATOM_DEVICE_TV1_SUPPORT,
1439                                                                 2),
1440                                           ATOM_DEVICE_TV1_SUPPORT);
1441                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1442                                             DRM_MODE_CONNECTOR_SVIDEO,
1443                                             &ddc_i2c);
1444                 break;
1445         case CT_IMAC_G5_ISIGHT:
1446                 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
1447                          rdev->mode_info.connector_table);
1448                 /* DVI-D - int tmds */
1449                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1450                 radeon_add_legacy_encoder(dev,
1451                                           radeon_get_encoder_id(dev,
1452                                                                 ATOM_DEVICE_DFP1_SUPPORT,
1453                                                                 0),
1454                                           ATOM_DEVICE_DFP1_SUPPORT);
1455                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1456                                             DRM_MODE_CONNECTOR_DVID, &ddc_i2c);
1457                 /* VGA - tv dac */
1458                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1459                 radeon_add_legacy_encoder(dev,
1460                                           radeon_get_encoder_id(dev,
1461                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1462                                                                 2),
1463                                           ATOM_DEVICE_CRT2_SUPPORT);
1464                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1465                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1466                 /* TV - TV DAC */
1467                 radeon_add_legacy_encoder(dev,
1468                                           radeon_get_encoder_id(dev,
1469                                                                 ATOM_DEVICE_TV1_SUPPORT,
1470                                                                 2),
1471                                           ATOM_DEVICE_TV1_SUPPORT);
1472                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1473                                             DRM_MODE_CONNECTOR_SVIDEO,
1474                                             &ddc_i2c);
1475                 break;
1476         case CT_EMAC:
1477                 DRM_INFO("Connector Table: %d (emac)\n",
1478                          rdev->mode_info.connector_table);
1479                 /* VGA - primary dac */
1480                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1481                 radeon_add_legacy_encoder(dev,
1482                                           radeon_get_encoder_id(dev,
1483                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1484                                                                 1),
1485                                           ATOM_DEVICE_CRT1_SUPPORT);
1486                 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1487                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1488                 /* VGA - tv dac */
1489                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1490                 radeon_add_legacy_encoder(dev,
1491                                           radeon_get_encoder_id(dev,
1492                                                                 ATOM_DEVICE_CRT2_SUPPORT,
1493                                                                 2),
1494                                           ATOM_DEVICE_CRT2_SUPPORT);
1495                 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1496                                             DRM_MODE_CONNECTOR_VGA, &ddc_i2c);
1497                 /* TV - TV DAC */
1498                 radeon_add_legacy_encoder(dev,
1499                                           radeon_get_encoder_id(dev,
1500                                                                 ATOM_DEVICE_TV1_SUPPORT,
1501                                                                 2),
1502                                           ATOM_DEVICE_TV1_SUPPORT);
1503                 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1504                                             DRM_MODE_CONNECTOR_SVIDEO,
1505                                             &ddc_i2c);
1506                 break;
1507         default:
1508                 DRM_INFO("Connector table: %d (invalid)\n",
1509                          rdev->mode_info.connector_table);
1510                 return false;
1511         }
1512
1513         radeon_link_encoder_connector(dev);
1514
1515         return true;
1516 }
1517
1518 static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1519                                        int bios_index,
1520                                        enum radeon_combios_connector
1521                                        *legacy_connector,
1522                                        struct radeon_i2c_bus_rec *ddc_i2c)
1523 {
1524         struct radeon_device *rdev = dev->dev_private;
1525
1526         /* XPRESS DDC quirks */
1527         if ((rdev->family == CHIP_RS400 ||
1528              rdev->family == CHIP_RS480) &&
1529             ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1530                 *ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_MONID);
1531         else if ((rdev->family == CHIP_RS400 ||
1532                   rdev->family == CHIP_RS480) &&
1533                  ddc_i2c->mask_clk_reg == RADEON_GPIO_MONID) {
1534                 ddc_i2c->valid = true;
1535                 ddc_i2c->mask_clk_mask = (0x20 << 8);
1536                 ddc_i2c->mask_data_mask = 0x80;
1537                 ddc_i2c->a_clk_mask = (0x20 << 8);
1538                 ddc_i2c->a_data_mask = 0x80;
1539                 ddc_i2c->put_clk_mask = (0x20 << 8);
1540                 ddc_i2c->put_data_mask = 0x80;
1541                 ddc_i2c->get_clk_mask = (0x20 << 8);
1542                 ddc_i2c->get_data_mask = 0x80;
1543                 ddc_i2c->mask_clk_reg = RADEON_GPIOPAD_MASK;
1544                 ddc_i2c->mask_data_reg = RADEON_GPIOPAD_MASK;
1545                 ddc_i2c->a_clk_reg = RADEON_GPIOPAD_A;
1546                 ddc_i2c->a_data_reg = RADEON_GPIOPAD_A;
1547                 ddc_i2c->put_clk_reg = RADEON_GPIOPAD_EN;
1548                 ddc_i2c->put_data_reg = RADEON_GPIOPAD_EN;
1549                 ddc_i2c->get_clk_reg = RADEON_LCD_GPIO_Y_REG;
1550                 ddc_i2c->get_data_reg = RADEON_LCD_GPIO_Y_REG;
1551         }
1552
1553         /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,
1554            one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
1555         if (dev->pdev->device == 0x515e &&
1556             dev->pdev->subsystem_vendor == 0x1014) {
1557                 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&
1558                     ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
1559                         return false;
1560         }
1561
1562         /* Some RV100 cards with 2 VGA ports show up with DVI+VGA */
1563         if (dev->pdev->device == 0x5159 &&
1564             dev->pdev->subsystem_vendor == 0x1002 &&
1565             dev->pdev->subsystem_device == 0x013a) {
1566                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1567                         *legacy_connector = CONNECTOR_CRT_LEGACY;
1568
1569         }
1570
1571         /* X300 card with extra non-existent DVI port */
1572         if (dev->pdev->device == 0x5B60 &&
1573             dev->pdev->subsystem_vendor == 0x17af &&
1574             dev->pdev->subsystem_device == 0x201e && bios_index == 2) {
1575                 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)
1576                         return false;
1577         }
1578
1579         return true;
1580 }
1581
1582 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1583 {
1584         struct radeon_device *rdev = dev->dev_private;
1585         uint32_t conn_info, entry, devices;
1586         uint16_t tmp;
1587         enum radeon_combios_ddc ddc_type;
1588         enum radeon_combios_connector connector;
1589         int i = 0;
1590         struct radeon_i2c_bus_rec ddc_i2c;
1591
1592         if (rdev->bios == NULL)
1593                 return false;
1594
1595         conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);
1596         if (conn_info) {
1597                 for (i = 0; i < 4; i++) {
1598                         entry = conn_info + 2 + i * 2;
1599
1600                         if (!RBIOS16(entry))
1601                                 break;
1602
1603                         tmp = RBIOS16(entry);
1604
1605                         connector = (tmp >> 12) & 0xf;
1606
1607                         ddc_type = (tmp >> 8) & 0xf;
1608                         switch (ddc_type) {
1609                         case DDC_MONID:
1610                                 ddc_i2c =
1611                                     combios_setup_i2c_bus(RADEON_GPIO_MONID);
1612                                 break;
1613                         case DDC_DVI:
1614                                 ddc_i2c =
1615                                     combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1616                                 break;
1617                         case DDC_VGA:
1618                                 ddc_i2c =
1619                                     combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1620                                 break;
1621                         case DDC_CRT2:
1622                                 ddc_i2c =
1623                                     combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1624                                 break;
1625                         default:
1626                                 break;
1627                         }
1628
1629                         if (!radeon_apply_legacy_quirks(dev, i, &connector,
1630                                                        &ddc_i2c))
1631                                 continue;
1632
1633                         switch (connector) {
1634                         case CONNECTOR_PROPRIETARY_LEGACY:
1635                                 if ((tmp >> 4) & 0x1)
1636                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1637                                 else
1638                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1639                                 radeon_add_legacy_encoder(dev,
1640                                                           radeon_get_encoder_id
1641                                                           (dev, devices, 0),
1642                                                           devices);
1643                                 radeon_add_legacy_connector(dev, i, devices,
1644                                                             legacy_connector_convert
1645                                                             [connector],
1646                                                             &ddc_i2c);
1647                                 break;
1648                         case CONNECTOR_CRT_LEGACY:
1649                                 if (tmp & 0x1) {
1650                                         devices = ATOM_DEVICE_CRT2_SUPPORT;
1651                                         radeon_add_legacy_encoder(dev,
1652                                                                   radeon_get_encoder_id
1653                                                                   (dev,
1654                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1655                                                                    2),
1656                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1657                                 } else {
1658                                         devices = ATOM_DEVICE_CRT1_SUPPORT;
1659                                         radeon_add_legacy_encoder(dev,
1660                                                                   radeon_get_encoder_id
1661                                                                   (dev,
1662                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1663                                                                    1),
1664                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1665                                 }
1666                                 radeon_add_legacy_connector(dev,
1667                                                             i,
1668                                                             devices,
1669                                                             legacy_connector_convert
1670                                                             [connector],
1671                                                             &ddc_i2c);
1672                                 break;
1673                         case CONNECTOR_DVI_I_LEGACY:
1674                                 devices = 0;
1675                                 if (tmp & 0x1) {
1676                                         devices |= ATOM_DEVICE_CRT2_SUPPORT;
1677                                         radeon_add_legacy_encoder(dev,
1678                                                                   radeon_get_encoder_id
1679                                                                   (dev,
1680                                                                    ATOM_DEVICE_CRT2_SUPPORT,
1681                                                                    2),
1682                                                                   ATOM_DEVICE_CRT2_SUPPORT);
1683                                 } else {
1684                                         devices |= ATOM_DEVICE_CRT1_SUPPORT;
1685                                         radeon_add_legacy_encoder(dev,
1686                                                                   radeon_get_encoder_id
1687                                                                   (dev,
1688                                                                    ATOM_DEVICE_CRT1_SUPPORT,
1689                                                                    1),
1690                                                                   ATOM_DEVICE_CRT1_SUPPORT);
1691                                 }
1692                                 if ((tmp >> 4) & 0x1) {
1693                                         devices |= ATOM_DEVICE_DFP2_SUPPORT;
1694                                         radeon_add_legacy_encoder(dev,
1695                                                                   radeon_get_encoder_id
1696                                                                   (dev,
1697                                                                    ATOM_DEVICE_DFP2_SUPPORT,
1698                                                                    0),
1699                                                                   ATOM_DEVICE_DFP2_SUPPORT);
1700                                 } else {
1701                                         devices |= ATOM_DEVICE_DFP1_SUPPORT;
1702                                         radeon_add_legacy_encoder(dev,
1703                                                                   radeon_get_encoder_id
1704                                                                   (dev,
1705                                                                    ATOM_DEVICE_DFP1_SUPPORT,
1706                                                                    0),
1707                                                                   ATOM_DEVICE_DFP1_SUPPORT);
1708                                 }
1709                                 radeon_add_legacy_connector(dev,
1710                                                             i,
1711                                                             devices,
1712                                                             legacy_connector_convert
1713                                                             [connector],
1714                                                             &ddc_i2c);
1715                                 break;
1716                         case CONNECTOR_DVI_D_LEGACY:
1717                                 if ((tmp >> 4) & 0x1)
1718                                         devices = ATOM_DEVICE_DFP2_SUPPORT;
1719                                 else
1720                                         devices = ATOM_DEVICE_DFP1_SUPPORT;
1721                                 radeon_add_legacy_encoder(dev,
1722                                                           radeon_get_encoder_id
1723                                                           (dev, devices, 0),
1724                                                           devices);
1725                                 radeon_add_legacy_connector(dev, i, devices,
1726                                                             legacy_connector_convert
1727                                                             [connector],
1728                                                             &ddc_i2c);
1729                                 break;
1730                         case CONNECTOR_CTV_LEGACY:
1731                         case CONNECTOR_STV_LEGACY:
1732                                 radeon_add_legacy_encoder(dev,
1733                                                           radeon_get_encoder_id
1734                                                           (dev,
1735                                                            ATOM_DEVICE_TV1_SUPPORT,
1736                                                            2),
1737                                                           ATOM_DEVICE_TV1_SUPPORT);
1738                                 radeon_add_legacy_connector(dev, i,
1739                                                             ATOM_DEVICE_TV1_SUPPORT,
1740                                                             legacy_connector_convert
1741                                                             [connector],
1742                                                             &ddc_i2c);
1743                                 break;
1744                         default:
1745                                 DRM_ERROR("Unknown connector type: %d\n",
1746                                           connector);
1747                                 continue;
1748                         }
1749
1750                 }
1751         } else {
1752                 uint16_t tmds_info =
1753                     combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);
1754                 if (tmds_info) {
1755                         DRM_DEBUG("Found DFP table, assuming DVI connector\n");
1756
1757                         radeon_add_legacy_encoder(dev,
1758                                                   radeon_get_encoder_id(dev,
1759                                                                         ATOM_DEVICE_CRT1_SUPPORT,
1760                                                                         1),
1761                                                   ATOM_DEVICE_CRT1_SUPPORT);
1762                         radeon_add_legacy_encoder(dev,
1763                                                   radeon_get_encoder_id(dev,
1764                                                                         ATOM_DEVICE_DFP1_SUPPORT,
1765                                                                         0),
1766                                                   ATOM_DEVICE_DFP1_SUPPORT);
1767
1768                         ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1769                         radeon_add_legacy_connector(dev,
1770                                                     0,
1771                                                     ATOM_DEVICE_CRT1_SUPPORT |
1772                                                     ATOM_DEVICE_DFP1_SUPPORT,
1773                                                     DRM_MODE_CONNECTOR_DVII,
1774                                                     &ddc_i2c);
1775                 } else {
1776                         uint16_t crt_info =
1777                                 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1778                         DRM_DEBUG("Found CRT table, assuming VGA connector\n");
1779                         if (crt_info) {
1780                                 radeon_add_legacy_encoder(dev,
1781                                                           radeon_get_encoder_id(dev,
1782                                                                                 ATOM_DEVICE_CRT1_SUPPORT,
1783                                                                                 1),
1784                                                           ATOM_DEVICE_CRT1_SUPPORT);
1785                                 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1786                                 radeon_add_legacy_connector(dev,
1787                                                             0,
1788                                                             ATOM_DEVICE_CRT1_SUPPORT,
1789                                                             DRM_MODE_CONNECTOR_VGA,
1790                                                             &ddc_i2c);
1791                         } else {
1792                                 DRM_DEBUG("No connector info found\n");
1793                                 return false;
1794                         }
1795                 }
1796         }
1797
1798         if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
1799                 uint16_t lcd_info =
1800                     combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
1801                 if (lcd_info) {
1802                         uint16_t lcd_ddc_info =
1803                             combios_get_table_offset(dev,
1804                                                      COMBIOS_LCD_DDC_INFO_TABLE);
1805
1806                         radeon_add_legacy_encoder(dev,
1807                                                   radeon_get_encoder_id(dev,
1808                                                                         ATOM_DEVICE_LCD1_SUPPORT,
1809                                                                         0),
1810                                                   ATOM_DEVICE_LCD1_SUPPORT);
1811
1812                         if (lcd_ddc_info) {
1813                                 ddc_type = RBIOS8(lcd_ddc_info + 2);
1814                                 switch (ddc_type) {
1815                                 case DDC_MONID:
1816                                         ddc_i2c =
1817                                             combios_setup_i2c_bus
1818                                             (RADEON_GPIO_MONID);
1819                                         break;
1820                                 case DDC_DVI:
1821                                         ddc_i2c =
1822                                             combios_setup_i2c_bus
1823                                             (RADEON_GPIO_DVI_DDC);
1824                                         break;
1825                                 case DDC_VGA:
1826                                         ddc_i2c =
1827                                             combios_setup_i2c_bus
1828                                             (RADEON_GPIO_VGA_DDC);
1829                                         break;
1830                                 case DDC_CRT2:
1831                                         ddc_i2c =
1832                                             combios_setup_i2c_bus
1833                                             (RADEON_GPIO_CRT2_DDC);
1834                                         break;
1835                                 case DDC_LCD:
1836                                         ddc_i2c =
1837                                             combios_setup_i2c_bus
1838                                             (RADEON_LCD_GPIO_MASK);
1839                                         ddc_i2c.mask_clk_mask =
1840                                             RBIOS32(lcd_ddc_info + 3);
1841                                         ddc_i2c.mask_data_mask =
1842                                             RBIOS32(lcd_ddc_info + 7);
1843                                         ddc_i2c.a_clk_mask =
1844                                             RBIOS32(lcd_ddc_info + 3);
1845                                         ddc_i2c.a_data_mask =
1846                                             RBIOS32(lcd_ddc_info + 7);
1847                                         ddc_i2c.put_clk_mask =
1848                                             RBIOS32(lcd_ddc_info + 3);
1849                                         ddc_i2c.put_data_mask =
1850                                             RBIOS32(lcd_ddc_info + 7);
1851                                         ddc_i2c.get_clk_mask =
1852                                             RBIOS32(lcd_ddc_info + 3);
1853                                         ddc_i2c.get_data_mask =
1854                                             RBIOS32(lcd_ddc_info + 7);
1855                                         break;
1856                                 case DDC_GPIO:
1857                                         ddc_i2c =
1858                                             combios_setup_i2c_bus
1859                                             (RADEON_MDGPIO_EN_REG);
1860                                         ddc_i2c.mask_clk_mask =
1861                                             RBIOS32(lcd_ddc_info + 3);
1862                                         ddc_i2c.mask_data_mask =
1863                                             RBIOS32(lcd_ddc_info + 7);
1864                                         ddc_i2c.a_clk_mask =
1865                                             RBIOS32(lcd_ddc_info + 3);
1866                                         ddc_i2c.a_data_mask =
1867                                             RBIOS32(lcd_ddc_info + 7);
1868                                         ddc_i2c.put_clk_mask =
1869                                             RBIOS32(lcd_ddc_info + 3);
1870                                         ddc_i2c.put_data_mask =
1871                                             RBIOS32(lcd_ddc_info + 7);
1872                                         ddc_i2c.get_clk_mask =
1873                                             RBIOS32(lcd_ddc_info + 3);
1874                                         ddc_i2c.get_data_mask =
1875                                             RBIOS32(lcd_ddc_info + 7);
1876                                         break;
1877                                 default:
1878                                         ddc_i2c.valid = false;
1879                                         break;
1880                                 }
1881                                 DRM_DEBUG("LCD DDC Info Table found!\n");
1882                         } else
1883                                 ddc_i2c.valid = false;
1884
1885                         radeon_add_legacy_connector(dev,
1886                                                     5,
1887                                                     ATOM_DEVICE_LCD1_SUPPORT,
1888                                                     DRM_MODE_CONNECTOR_LVDS,
1889                                                     &ddc_i2c);
1890                 }
1891         }
1892
1893         /* check TV table */
1894         if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1895                 uint32_t tv_info =
1896                     combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1897                 if (tv_info) {
1898                         if (RBIOS8(tv_info + 6) == 'T') {
1899                                 radeon_add_legacy_encoder(dev,
1900                                                           radeon_get_encoder_id
1901                                                           (dev,
1902                                                            ATOM_DEVICE_TV1_SUPPORT,
1903                                                            2),
1904                                                           ATOM_DEVICE_TV1_SUPPORT);
1905                                 radeon_add_legacy_connector(dev, 6,
1906                                                             ATOM_DEVICE_TV1_SUPPORT,
1907                                                             DRM_MODE_CONNECTOR_SVIDEO,
1908                                                             &ddc_i2c);
1909                         }
1910                 }
1911         }
1912
1913         radeon_link_encoder_connector(dev);
1914
1915         return true;
1916 }
1917
1918 static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
1919 {
1920         struct radeon_device *rdev = dev->dev_private;
1921
1922         if (offset) {
1923                 while (RBIOS16(offset)) {
1924                         uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);
1925                         uint32_t addr = (RBIOS16(offset) & 0x1fff);
1926                         uint32_t val, and_mask, or_mask;
1927                         uint32_t tmp;
1928
1929                         offset += 2;
1930                         switch (cmd) {
1931                         case 0:
1932                                 val = RBIOS32(offset);
1933                                 offset += 4;
1934                                 WREG32(addr, val);
1935                                 break;
1936                         case 1:
1937                                 val = RBIOS32(offset);
1938                                 offset += 4;
1939                                 WREG32(addr, val);
1940                                 break;
1941                         case 2:
1942                                 and_mask = RBIOS32(offset);
1943                                 offset += 4;
1944                                 or_mask = RBIOS32(offset);
1945                                 offset += 4;
1946                                 tmp = RREG32(addr);
1947                                 tmp &= and_mask;
1948                                 tmp |= or_mask;
1949                                 WREG32(addr, tmp);
1950                                 break;
1951                         case 3:
1952                                 and_mask = RBIOS32(offset);
1953                                 offset += 4;
1954                                 or_mask = RBIOS32(offset);
1955                                 offset += 4;
1956                                 tmp = RREG32(addr);
1957                                 tmp &= and_mask;
1958                                 tmp |= or_mask;
1959                                 WREG32(addr, tmp);
1960                                 break;
1961                         case 4:
1962                                 val = RBIOS16(offset);
1963                                 offset += 2;
1964                                 udelay(val);
1965                                 break;
1966                         case 5:
1967                                 val = RBIOS16(offset);
1968                                 offset += 2;
1969                                 switch (addr) {
1970                                 case 8:
1971                                         while (val--) {
1972                                                 if (!
1973                                                     (RREG32_PLL
1974                                                      (RADEON_CLK_PWRMGT_CNTL) &
1975                                                      RADEON_MC_BUSY))
1976                                                         break;
1977                                         }
1978                                         break;
1979                                 case 9:
1980                                         while (val--) {
1981                                                 if ((RREG32(RADEON_MC_STATUS) &
1982                                                      RADEON_MC_IDLE))
1983                                                         break;
1984                                         }
1985                                         break;
1986                                 default:
1987                                         break;
1988                                 }
1989                                 break;
1990                         default:
1991                                 break;
1992                         }
1993                 }
1994         }
1995 }
1996
1997 static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
1998 {
1999         struct radeon_device *rdev = dev->dev_private;
2000
2001         if (offset) {
2002                 while (RBIOS8(offset)) {
2003                         uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);
2004                         uint8_t addr = (RBIOS8(offset) & 0x3f);
2005                         uint32_t val, shift, tmp;
2006                         uint32_t and_mask, or_mask;
2007
2008                         offset++;
2009                         switch (cmd) {
2010                         case 0:
2011                                 val = RBIOS32(offset);
2012                                 offset += 4;
2013                                 WREG32_PLL(addr, val);
2014                                 break;
2015                         case 1:
2016                                 shift = RBIOS8(offset) * 8;
2017                                 offset++;
2018                                 and_mask = RBIOS8(offset) << shift;
2019                                 and_mask |= ~(0xff << shift);
2020                                 offset++;
2021                                 or_mask = RBIOS8(offset) << shift;
2022                                 offset++;
2023                                 tmp = RREG32_PLL(addr);
2024                                 tmp &= and_mask;
2025                                 tmp |= or_mask;
2026                                 WREG32_PLL(addr, tmp);
2027                                 break;
2028                         case 2:
2029                         case 3:
2030                                 tmp = 1000;
2031                                 switch (addr) {
2032                                 case 1:
2033                                         udelay(150);
2034                                         break;
2035                                 case 2:
2036                                         udelay(1000);
2037                                         break;
2038                                 case 3:
2039                                         while (tmp--) {
2040                                                 if (!
2041                                                     (RREG32_PLL
2042                                                      (RADEON_CLK_PWRMGT_CNTL) &
2043                                                      RADEON_MC_BUSY))
2044                                                         break;
2045                                         }
2046                                         break;
2047                                 case 4:
2048                                         while (tmp--) {
2049                                                 if (RREG32_PLL
2050                                                     (RADEON_CLK_PWRMGT_CNTL) &
2051                                                     RADEON_DLL_READY)
2052                                                         break;
2053                                         }
2054                                         break;
2055                                 case 5:
2056                                         tmp =
2057                                             RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);
2058                                         if (tmp & RADEON_CG_NO1_DEBUG_0) {
2059 #if 0
2060                                                 uint32_t mclk_cntl =
2061                                                     RREG32_PLL
2062                                                     (RADEON_MCLK_CNTL);
2063                                                 mclk_cntl &= 0xffff0000;
2064                                                 /*mclk_cntl |= 0x00001111;*//* ??? */
2065                                                 WREG32_PLL(RADEON_MCLK_CNTL,
2066                                                            mclk_cntl);
2067                                                 udelay(10000);
2068 #endif
2069                                                 WREG32_PLL
2070                                                     (RADEON_CLK_PWRMGT_CNTL,
2071                                                      tmp &
2072                                                      ~RADEON_CG_NO1_DEBUG_0);
2073                                                 udelay(10000);
2074                                         }
2075                                         break;
2076                                 default:
2077                                         break;
2078                                 }
2079                                 break;
2080                         default:
2081                                 break;
2082                         }
2083                 }
2084         }
2085 }
2086
2087 static void combios_parse_ram_reset_table(struct drm_device *dev,
2088                                           uint16_t offset)
2089 {
2090         struct radeon_device *rdev = dev->dev_private;
2091         uint32_t tmp;
2092
2093         if (offset) {
2094                 uint8_t val = RBIOS8(offset);
2095                 while (val != 0xff) {
2096                         offset++;
2097
2098                         if (val == 0x0f) {
2099                                 uint32_t channel_complete_mask;
2100
2101                                 if (ASIC_IS_R300(rdev))
2102                                         channel_complete_mask =
2103                                             R300_MEM_PWRUP_COMPLETE;
2104                                 else
2105                                         channel_complete_mask =
2106                                             RADEON_MEM_PWRUP_COMPLETE;
2107                                 tmp = 20000;
2108                                 while (tmp--) {
2109                                         if ((RREG32(RADEON_MEM_STR_CNTL) &
2110                                              channel_complete_mask) ==
2111                                             channel_complete_mask)
2112                                                 break;
2113                                 }
2114                         } else {
2115                                 uint32_t or_mask = RBIOS16(offset);
2116                                 offset += 2;
2117
2118                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2119                                 tmp &= RADEON_SDRAM_MODE_MASK;
2120                                 tmp |= or_mask;
2121                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2122
2123                                 or_mask = val << 24;
2124                                 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2125                                 tmp &= RADEON_B3MEM_RESET_MASK;
2126                                 tmp |= or_mask;
2127                                 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);
2128                         }
2129                         val = RBIOS8(offset);
2130                 }
2131         }
2132 }
2133
2134 static uint32_t combios_detect_ram(struct drm_device *dev, int ram,
2135                                    int mem_addr_mapping)
2136 {
2137         struct radeon_device *rdev = dev->dev_private;
2138         uint32_t mem_cntl;
2139         uint32_t mem_size;
2140         uint32_t addr = 0;
2141
2142         mem_cntl = RREG32(RADEON_MEM_CNTL);
2143         if (mem_cntl & RV100_HALF_MODE)
2144                 ram /= 2;
2145         mem_size = ram;
2146         mem_cntl &= ~(0xff << 8);
2147         mem_cntl |= (mem_addr_mapping & 0xff) << 8;
2148         WREG32(RADEON_MEM_CNTL, mem_cntl);
2149         RREG32(RADEON_MEM_CNTL);
2150
2151         /* sdram reset ? */
2152
2153         /* something like this????  */
2154         while (ram--) {
2155                 addr = ram * 1024 * 1024;
2156                 /* write to each page */
2157                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2158                 WREG32(RADEON_MM_DATA, 0xdeadbeef);
2159                 /* read back and verify */
2160                 WREG32(RADEON_MM_INDEX, (addr) | RADEON_MM_APER);
2161                 if (RREG32(RADEON_MM_DATA) != 0xdeadbeef)
2162                         return 0;
2163         }
2164
2165         return mem_size;
2166 }
2167
2168 static void combios_write_ram_size(struct drm_device *dev)
2169 {
2170         struct radeon_device *rdev = dev->dev_private;
2171         uint8_t rev;
2172         uint16_t offset;
2173         uint32_t mem_size = 0;
2174         uint32_t mem_cntl = 0;
2175
2176         /* should do something smarter here I guess... */
2177         if (rdev->flags & RADEON_IS_IGP)
2178                 return;
2179
2180         /* first check detected mem table */
2181         offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);
2182         if (offset) {
2183                 rev = RBIOS8(offset);
2184                 if (rev < 3) {
2185                         mem_cntl = RBIOS32(offset + 1);
2186                         mem_size = RBIOS16(offset + 5);
2187                         if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
2188                             ((dev->pdev->device != 0x515e)
2189                              && (dev->pdev->device != 0x5969)))
2190                                 WREG32(RADEON_MEM_CNTL, mem_cntl);
2191                 }
2192         }
2193
2194         if (!mem_size) {
2195                 offset =
2196                     combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);
2197                 if (offset) {
2198                         rev = RBIOS8(offset - 1);
2199                         if (rev < 1) {
2200                                 if (((rdev->flags & RADEON_FAMILY_MASK) <
2201                                      CHIP_R200)
2202                                     && ((dev->pdev->device != 0x515e)
2203                                         && (dev->pdev->device != 0x5969))) {
2204                                         int ram = 0;
2205                                         int mem_addr_mapping = 0;
2206
2207                                         while (RBIOS8(offset)) {
2208                                                 ram = RBIOS8(offset);
2209                                                 mem_addr_mapping =
2210                                                     RBIOS8(offset + 1);
2211                                                 if (mem_addr_mapping != 0x25)
2212                                                         ram *= 2;
2213                                                 mem_size =
2214                                                     combios_detect_ram(dev, ram,
2215                                                                        mem_addr_mapping);
2216                                                 if (mem_size)
2217                                                         break;
2218                                                 offset += 2;
2219                                         }
2220                                 } else
2221                                         mem_size = RBIOS8(offset);
2222                         } else {
2223                                 mem_size = RBIOS8(offset);
2224                                 mem_size *= 2;  /* convert to MB */
2225                         }
2226                 }
2227         }
2228
2229         mem_size *= (1024 * 1024);      /* convert to bytes */
2230         WREG32(RADEON_CONFIG_MEMSIZE, mem_size);
2231 }
2232
2233 void radeon_combios_dyn_clk_setup(struct drm_device *dev, int enable)
2234 {
2235         uint16_t dyn_clk_info =
2236             combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2237
2238         if (dyn_clk_info)
2239                 combios_parse_pll_table(dev, dyn_clk_info);
2240 }
2241
2242 void radeon_combios_asic_init(struct drm_device *dev)
2243 {
2244         struct radeon_device *rdev = dev->dev_private;
2245         uint16_t table;
2246
2247         /* port hardcoded mac stuff from radeonfb */
2248         if (rdev->bios == NULL)
2249                 return;
2250
2251         /* ASIC INIT 1 */
2252         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);
2253         if (table)
2254                 combios_parse_mmio_table(dev, table);
2255
2256         /* PLL INIT */
2257         table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);
2258         if (table)
2259                 combios_parse_pll_table(dev, table);
2260
2261         /* ASIC INIT 2 */
2262         table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);
2263         if (table)
2264                 combios_parse_mmio_table(dev, table);
2265
2266         if (!(rdev->flags & RADEON_IS_IGP)) {
2267                 /* ASIC INIT 4 */
2268                 table =
2269                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);
2270                 if (table)
2271                         combios_parse_mmio_table(dev, table);
2272
2273                 /* RAM RESET */
2274                 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);
2275                 if (table)
2276                         combios_parse_ram_reset_table(dev, table);
2277
2278                 /* ASIC INIT 3 */
2279                 table =
2280                     combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);
2281                 if (table)
2282                         combios_parse_mmio_table(dev, table);
2283
2284                 /* write CONFIG_MEMSIZE */
2285                 combios_write_ram_size(dev);
2286         }
2287
2288         /* DYN CLK 1 */
2289         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
2290         if (table)
2291                 combios_parse_pll_table(dev, table);
2292
2293 }
2294
2295 void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)
2296 {
2297         struct radeon_device *rdev = dev->dev_private;
2298         uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;
2299
2300         bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2301         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2302         bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);
2303
2304         /* let the bios control the backlight */
2305         bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;
2306
2307         /* tell the bios not to handle mode switching */
2308         bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |
2309                            RADEON_ACC_MODE_CHANGE);
2310
2311         /* tell the bios a driver is loaded */
2312         bios_7_scratch |= RADEON_DRV_LOADED;
2313
2314         WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2315         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2316         WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);
2317 }
2318
2319 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
2320 {
2321         struct drm_device *dev = encoder->dev;
2322         struct radeon_device *rdev = dev->dev_private;
2323         uint32_t bios_6_scratch;
2324
2325         bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2326
2327         if (lock)
2328                 bios_6_scratch |= RADEON_DRIVER_CRITICAL;
2329         else
2330                 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;
2331
2332         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2333 }
2334
2335 void
2336 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
2337                                       struct drm_encoder *encoder,
2338                                       bool connected)
2339 {
2340         struct drm_device *dev = connector->dev;
2341         struct radeon_device *rdev = dev->dev_private;
2342         struct radeon_connector *radeon_connector =
2343             to_radeon_connector(connector);
2344         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2345         uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);
2346         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2347
2348         if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2349             (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2350                 if (connected) {
2351                         DRM_DEBUG("TV1 connected\n");
2352                         /* fix me */
2353                         bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;
2354                         /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
2355                         bios_5_scratch |= RADEON_TV1_ON;
2356                         bios_5_scratch |= RADEON_ACC_REQ_TV1;
2357                 } else {
2358                         DRM_DEBUG("TV1 disconnected\n");
2359                         bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;
2360                         bios_5_scratch &= ~RADEON_TV1_ON;
2361                         bios_5_scratch &= ~RADEON_ACC_REQ_TV1;
2362                 }
2363         }
2364         if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2365             (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2366                 if (connected) {
2367                         DRM_DEBUG("LCD1 connected\n");
2368                         bios_4_scratch |= RADEON_LCD1_ATTACHED;
2369                         bios_5_scratch |= RADEON_LCD1_ON;
2370                         bios_5_scratch |= RADEON_ACC_REQ_LCD1;
2371                 } else {
2372                         DRM_DEBUG("LCD1 disconnected\n");
2373                         bios_4_scratch &= ~RADEON_LCD1_ATTACHED;
2374                         bios_5_scratch &= ~RADEON_LCD1_ON;
2375                         bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;
2376                 }
2377         }
2378         if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2379             (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2380                 if (connected) {
2381                         DRM_DEBUG("CRT1 connected\n");
2382                         bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;
2383                         bios_5_scratch |= RADEON_CRT1_ON;
2384                         bios_5_scratch |= RADEON_ACC_REQ_CRT1;
2385                 } else {
2386                         DRM_DEBUG("CRT1 disconnected\n");
2387                         bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;
2388                         bios_5_scratch &= ~RADEON_CRT1_ON;
2389                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;
2390                 }
2391         }
2392         if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2393             (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2394                 if (connected) {
2395                         DRM_DEBUG("CRT2 connected\n");
2396                         bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;
2397                         bios_5_scratch |= RADEON_CRT2_ON;
2398                         bios_5_scratch |= RADEON_ACC_REQ_CRT2;
2399                 } else {
2400                         DRM_DEBUG("CRT2 disconnected\n");
2401                         bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;
2402                         bios_5_scratch &= ~RADEON_CRT2_ON;
2403                         bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;
2404                 }
2405         }
2406         if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2407             (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2408                 if (connected) {
2409                         DRM_DEBUG("DFP1 connected\n");
2410                         bios_4_scratch |= RADEON_DFP1_ATTACHED;
2411                         bios_5_scratch |= RADEON_DFP1_ON;
2412                         bios_5_scratch |= RADEON_ACC_REQ_DFP1;
2413                 } else {
2414                         DRM_DEBUG("DFP1 disconnected\n");
2415                         bios_4_scratch &= ~RADEON_DFP1_ATTACHED;
2416                         bios_5_scratch &= ~RADEON_DFP1_ON;
2417                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;
2418                 }
2419         }
2420         if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2421             (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2422                 if (connected) {
2423                         DRM_DEBUG("DFP2 connected\n");
2424                         bios_4_scratch |= RADEON_DFP2_ATTACHED;
2425                         bios_5_scratch |= RADEON_DFP2_ON;
2426                         bios_5_scratch |= RADEON_ACC_REQ_DFP2;
2427                 } else {
2428                         DRM_DEBUG("DFP2 disconnected\n");
2429                         bios_4_scratch &= ~RADEON_DFP2_ATTACHED;
2430                         bios_5_scratch &= ~RADEON_DFP2_ON;
2431                         bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;
2432                 }
2433         }
2434         WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);
2435         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2436 }
2437
2438 void
2439 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2440 {
2441         struct drm_device *dev = encoder->dev;
2442         struct radeon_device *rdev = dev->dev_private;
2443         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2444         uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);
2445
2446         if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2447                 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
2448                 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);
2449         }
2450         if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2451                 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
2452                 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);
2453         }
2454         if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2455                 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
2456                 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);
2457         }
2458         if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2459                 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
2460                 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);
2461         }
2462         if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2463                 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
2464                 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);
2465         }
2466         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2467                 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
2468                 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);
2469         }
2470         WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
2471 }
2472
2473 void
2474 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2475 {
2476         struct drm_device *dev = encoder->dev;
2477         struct radeon_device *rdev = dev->dev_private;
2478         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2479         uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2480
2481         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
2482                 if (on)
2483                         bios_6_scratch |= RADEON_TV_DPMS_ON;
2484                 else
2485                         bios_6_scratch &= ~RADEON_TV_DPMS_ON;
2486         }
2487         if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2488                 if (on)
2489                         bios_6_scratch |= RADEON_CRT_DPMS_ON;
2490                 else
2491                         bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
2492         }
2493         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2494                 if (on)
2495                         bios_6_scratch |= RADEON_LCD_DPMS_ON;
2496                 else
2497                         bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
2498         }
2499         if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
2500                 if (on)
2501                         bios_6_scratch |= RADEON_DFP_DPMS_ON;
2502                 else
2503                         bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
2504         }
2505         WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2506 }