drivers/gpu/drm/radeon/radeon_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include "drmP.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31
  32 void r100_cs_dump_packet(struct radeon_cs_parser *p,
  33                          struct radeon_cs_packet *pkt);
  34
  35 int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  36 {
  37         struct drm_device *ddev = p->rdev->ddev;
  38         struct radeon_cs_chunk *chunk;
  39         unsigned i, j;
  40         bool duplicate;
  41
  42         if (p->chunk_relocs_idx == -1) {
  43                 return 0;
  44         }
  45         chunk = &p->chunks[p->chunk_relocs_idx];
  46         /* FIXME: we assume that each relocs use 4 dwords */
  47         p->nrelocs = chunk->length_dw / 4;
  48         p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  49         if (p->relocs_ptr == NULL) {
  50                 return -ENOMEM;
  51         }
  52         p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  53         if (p->relocs == NULL) {
  54                 return -ENOMEM;
  55         }
  56         for (i = 0; i < p->nrelocs; i++) {
  57                 struct drm_radeon_cs_reloc *r;
  58
  59                 duplicate = false;
  60                 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  61                 for (j = 0; j < i; j++) {
  62                         if (r->handle == p->relocs[j].handle) {
  63                                 p->relocs_ptr[i] = &p->relocs[j];
  64                                 duplicate = true;
  65                                 break;
  66                         }
  67                 }
  68                 if (!duplicate) {
  69                         p->relocs[i].gobj = drm_gem_object_lookup(ddev,
  70                                                                   p->filp,
  71                                                                   r->handle);
  72                         if (p->relocs[i].gobj == NULL) {
  73                                 DRM_ERROR("gem object lookup failed 0x%x\n",
  74                                           r->handle);
  75                                 return -ENOENT;
  76                         }
  77                         p->relocs_ptr[i] = &p->relocs[i];
  78                         p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  79                         p->relocs[i].lobj.bo = p->relocs[i].robj;
  80                         p->relocs[i].lobj.wdomain = r->write_domain;
  81                         p->relocs[i].lobj.rdomain = r->read_domains;
  82                         p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
  83                         p->relocs[i].handle = r->handle;
  84                         p->relocs[i].flags = r->flags;
  85                         radeon_bo_list_add_object(&p->relocs[i].lobj,
  86                                                   &p->validated);
  87
  88                 } else
  89                         p->relocs[i].handle = 0;
  90         }
  91         return radeon_bo_list_validate(&p->validated);
  92 }
  93
  94 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
  95 {
  96         p->priority = priority;
  97
  98         switch (ring) {
  99         default:
 100                 DRM_ERROR("unknown ring id: %d\n", ring);
 101                 return -EINVAL;
 102         case RADEON_CS_RING_GFX:
 103                 p->ring = RADEON_RING_TYPE_GFX_INDEX;
 104                 break;
 105         case RADEON_CS_RING_COMPUTE:
 106                 if (p->rdev->family >= CHIP_TAHITI) {
 107                         if (p->priority > 0)
 108                                 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
 109                         else
 110                                 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
 111                 } else
 112                         p->ring = RADEON_RING_TYPE_GFX_INDEX;
 113                 break;
 114         }
 115         return 0;
 116 }
 117
 118 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
 119 {
 120         int i;
 121
 122         for (i = 0; i < p->nrelocs; i++) {
 123                 struct radeon_fence *a, *b;
 124
 125                 if (!p->relocs[i].robj || !p->relocs[i].robj->tbo.sync_obj)
 126                         continue;
 127
 128                 a = p->relocs[i].robj->tbo.sync_obj;
 129                 b = p->ib.sync_to[a->ring];
 130                 p->ib.sync_to[a->ring] = radeon_fence_later(a, b);
 131         }
 132 }
 133
 134 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
 135 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 136 {
 137         struct drm_radeon_cs *cs = data;
 138         uint64_t *chunk_array_ptr;
 139         unsigned size, i;
 140         u32 ring = RADEON_CS_RING_GFX;
 141         s32 priority = 0;
 142
 143         if (!cs->num_chunks) {
 144                 return 0;
 145         }
 146         /* get chunks */
 147         INIT_LIST_HEAD(&p->validated);
 148         p->idx = 0;
 149         p->ib.sa_bo = NULL;
 150         p->ib.semaphore = NULL;
 151         p->const_ib.sa_bo = NULL;
 152         p->const_ib.semaphore = NULL;
 153         p->chunk_ib_idx = -1;
 154         p->chunk_relocs_idx = -1;
 155         p->chunk_flags_idx = -1;
 156         p->chunk_const_ib_idx = -1;
 157         p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
 158         if (p->chunks_array == NULL) {
 159                 return -ENOMEM;
 160         }
 161         chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
 162         if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
 163                                sizeof(uint64_t)*cs->num_chunks)) {
 164                 return -EFAULT;
 165         }
 166         p->cs_flags = 0;
 167         p->nchunks = cs->num_chunks;
 168         p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
 169         if (p->chunks == NULL) {
 170                 return -ENOMEM;
 171         }
 172         for (i = 0; i < p->nchunks; i++) {
 173                 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
 174                 struct drm_radeon_cs_chunk user_chunk;
 175                 uint32_t __user *cdata;
 176
 177                 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
 178                 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
 179                                        sizeof(struct drm_radeon_cs_chunk))) {
 180                         return -EFAULT;
 181                 }
 182                 p->chunks[i].length_dw = user_chunk.length_dw;
 183                 p->chunks[i].kdata = NULL;
 184                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 185
 186                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
 187                         p->chunk_relocs_idx = i;
 188                 }
 189                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
 190                         p->chunk_ib_idx = i;
 191                         /* zero length IB isn't useful */
 192                         if (p->chunks[i].length_dw == 0)
 193                                 return -EINVAL;
 194                 }
 195                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
 196                         p->chunk_const_ib_idx = i;
 197                         /* zero length CONST IB isn't useful */
 198                         if (p->chunks[i].length_dw == 0)
 199                                 return -EINVAL;
 200                 }
 201                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 202                         p->chunk_flags_idx = i;
 203                         /* zero length flags aren't useful */
 204                         if (p->chunks[i].length_dw == 0)
 205                                 return -EINVAL;
 206                 }
 207
 208                 p->chunks[i].length_dw = user_chunk.length_dw;
 209                 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
 210
 211                 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
 212                 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
 213                     (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
 214                         size = p->chunks[i].length_dw * sizeof(uint32_t);
 215                         p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
 216                         if (p->chunks[i].kdata == NULL) {
 217                                 return -ENOMEM;
 218                         }
 219                         if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
 220                                                p->chunks[i].user_ptr, size)) {
 221                                 return -EFAULT;
 222                         }
 223                         if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 224                                 p->cs_flags = p->chunks[i].kdata[0];
 225                                 if (p->chunks[i].length_dw > 1)
 226                                         ring = p->chunks[i].kdata[1];
 227                                 if (p->chunks[i].length_dw > 2)
 228                                         priority = (s32)p->chunks[i].kdata[2];
 229                         }
 230                 }
 231         }
 232
 233         /* these are KMS only */
 234         if (p->rdev) {
 235                 if ((p->cs_flags & RADEON_CS_USE_VM) &&
 236                     !p->rdev->vm_manager.enabled) {
 237                         DRM_ERROR("VM not active on asic!\n");
 238                         return -EINVAL;
 239                 }
 240
 241                 /* we only support VM on SI+ */
 242                 if ((p->rdev->family >= CHIP_TAHITI) &&
 243                     ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
 244                         DRM_ERROR("VM required on SI+!\n");
 245                         return -EINVAL;
 246                 }
 247
 248                 if (radeon_cs_get_ring(p, ring, priority))
 249                         return -EINVAL;
 250         }
 251
 252         /* deal with non-vm */
 253         if ((p->chunk_ib_idx != -1) &&
 254             ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
 255             (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
 256                 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
 257                         DRM_ERROR("cs IB too big: %d\n",
 258                                   p->chunks[p->chunk_ib_idx].length_dw);
 259                         return -EINVAL;
 260                 }
 261                 if ((p->rdev->flags & RADEON_IS_AGP)) {
 262                         p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
 263                         p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
 264                         if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
 265                             p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
 266                                 kfree(p->chunks[i].kpage[0]);
 267                                 kfree(p->chunks[i].kpage[1]);
 268                                 return -ENOMEM;
 269                         }
 270                 }
 271                 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
 272                 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
 273                 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
 274                 p->chunks[p->chunk_ib_idx].last_page_index =
 275                         ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
 276         }
 277
 278         return 0;
 279 }
 280
 281 /**
 282  * cs_parser_fini() - clean parser states
 283  * @parser:     parser structure holding parsing context.
 284  * @error:      error number
 285  *
 286  * If error is set than unvalidate buffer, otherwise just free memory
 287  * used by parsing context.
 288  **/
 289 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
 290 {
 291         unsigned i;
 292
 293         if (!error)
 294                 ttm_eu_fence_buffer_objects(&parser->validated,
 295                                             parser->ib.fence);
 296         else
 297                 ttm_eu_backoff_reservation(&parser->validated);
 298
 299         if (parser->relocs != NULL) {
 300                 for (i = 0; i < parser->nrelocs; i++) {
 301                         if (parser->relocs[i].gobj)
 302                                 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
 303                 }
 304         }
 305         kfree(parser->track);
 306         kfree(parser->relocs);
 307         kfree(parser->relocs_ptr);
 308         for (i = 0; i < parser->nchunks; i++) {
 309                 kfree(parser->chunks[i].kdata);
 310                 if ((parser->rdev->flags & RADEON_IS_AGP)) {
 311                         kfree(parser->chunks[i].kpage[0]);
 312                         kfree(parser->chunks[i].kpage[1]);
 313                 }
 314         }
 315         kfree(parser->chunks);
 316         kfree(parser->chunks_array);
 317         radeon_ib_free(parser->rdev, &parser->ib);
 318         radeon_ib_free(parser->rdev, &parser->const_ib);
 319 }
 320
 321 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
 322                               struct radeon_cs_parser *parser)
 323 {
 324         struct radeon_cs_chunk *ib_chunk;
 325         int r;
 326
 327         if (parser->chunk_ib_idx == -1)
 328                 return 0;
 329
 330         if (parser->cs_flags & RADEON_CS_USE_VM)
 331                 return 0;
 332
 333         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 334         /* Copy the packet into the IB, the parser will read from the
 335          * input memory (cached) and write to the IB (which can be
 336          * uncached).
 337          */
 338         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 339                            ib_chunk->length_dw * 4);
 340         if (r) {
 341                 DRM_ERROR("Failed to get ib !\n");
 342                 return r;
 343         }
 344         parser->ib.length_dw = ib_chunk->length_dw;
 345         r = radeon_cs_parse(rdev, parser->ring, parser);
 346         if (r || parser->parser_error) {
 347                 DRM_ERROR("Invalid command stream !\n");
 348                 return r;
 349         }
 350         r = radeon_cs_finish_pages(parser);
 351         if (r) {
 352                 DRM_ERROR("Invalid command stream !\n");
 353                 return r;
 354         }
 355         radeon_cs_sync_rings(parser);
 356         parser->ib.vm_id = 0;
 357         r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 358         if (r) {
 359                 DRM_ERROR("Failed to schedule IB !\n");
 360         }
 361         return r;
 362 }
 363
 364 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
 365                                    struct radeon_vm *vm)
 366 {
 367         struct radeon_bo_list *lobj;
 368         struct radeon_bo *bo;
 369         int r;
 370
 371         list_for_each_entry(lobj, &parser->validated, tv.head) {
 372                 bo = lobj->bo;
 373                 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
 374                 if (r) {
 375                         return r;
 376                 }
 377         }
 378         return 0;
 379 }
 380
 381 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
 382                                  struct radeon_cs_parser *parser)
 383 {
 384         struct radeon_cs_chunk *ib_chunk;
 385         struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 386         struct radeon_vm *vm = &fpriv->vm;
 387         int r;
 388
 389         if (parser->chunk_ib_idx == -1)
 390                 return 0;
 391
 392         if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
 393                 return 0;
 394
 395         if ((rdev->family >= CHIP_TAHITI) &&
 396             (parser->chunk_const_ib_idx != -1)) {
 397                 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
 398                 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 399                         DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
 400                         return -EINVAL;
 401                 }
 402                 r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
 403                                    ib_chunk->length_dw * 4);
 404                 if (r) {
 405                         DRM_ERROR("Failed to get const ib !\n");
 406                         return r;
 407                 }
 408                 parser->const_ib.is_const_ib = true;
 409                 parser->const_ib.length_dw = ib_chunk->length_dw;
 410                 /* Copy the packet into the IB */
 411                 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
 412                                        ib_chunk->length_dw * 4)) {
 413                         return -EFAULT;
 414                 }
 415                 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
 416                 if (r) {
 417                         return r;
 418                 }
 419         }
 420
 421         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 422         if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 423                 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
 424                 return -EINVAL;
 425         }
 426         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 427                            ib_chunk->length_dw * 4);
 428         if (r) {
 429                 DRM_ERROR("Failed to get ib !\n");
 430                 return r;
 431         }
 432         parser->ib.length_dw = ib_chunk->length_dw;
 433         /* Copy the packet into the IB */
 434         if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
 435                                ib_chunk->length_dw * 4)) {
 436                 return -EFAULT;
 437         }
 438         r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
 439         if (r) {
 440                 return r;
 441         }
 442
 443         mutex_lock(&rdev->vm_manager.lock);
 444         mutex_lock(&vm->mutex);
 445         r = radeon_vm_bind(rdev, vm);
 446         if (r) {
 447                 goto out;
 448         }
 449         r = radeon_bo_vm_update_pte(parser, vm);
 450         if (r) {
 451                 goto out;
 452         }
 453         radeon_cs_sync_rings(parser);
 454
 455         parser->ib.vm_id = vm->id;
 456         /* ib pool is bind at 0 in virtual address space,
 457          * so gpu_addr is the offset inside the pool bo
 458          */
 459         parser->ib.gpu_addr = parser->ib.sa_bo->soffset;
 460
 461         if ((rdev->family >= CHIP_TAHITI) &&
 462             (parser->chunk_const_ib_idx != -1)) {
 463                 parser->const_ib.vm_id = vm->id;
 464                 /* ib pool is bind at 0 in virtual address space,
 465                  * so gpu_addr is the offset inside the pool bo
 466                  */
 467                 parser->const_ib.gpu_addr = parser->const_ib.sa_bo->soffset;
 468                 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
 469         } else {
 470                 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 471         }
 472
 473 out:
 474         if (!r) {
 475                 if (vm->fence) {
 476                         radeon_fence_unref(&vm->fence);
 477                 }
 478                 vm->fence = radeon_fence_ref(parser->ib.fence);
 479         }
 480         mutex_unlock(&vm->mutex);
 481         mutex_unlock(&rdev->vm_manager.lock);
 482         return r;
 483 }
 484
 485 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
 486 {
 487         if (r == -EDEADLK) {
 488                 r = radeon_gpu_reset(rdev);
 489                 if (!r)
 490                         r = -EAGAIN;
 491         }
 492         return r;
 493 }
 494
 495 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 496 {
 497         struct radeon_device *rdev = dev->dev_private;
 498         struct radeon_cs_parser parser;
 499         int r;
 500
 501         down_read(&rdev->exclusive_lock);
 502         if (!rdev->accel_working) {
 503                 up_read(&rdev->exclusive_lock);
 504                 return -EBUSY;
 505         }
 506         /* initialize parser */
 507         memset(&parser, 0, sizeof(struct radeon_cs_parser));
 508         parser.filp = filp;
 509         parser.rdev = rdev;
 510         parser.dev = rdev->dev;
 511         parser.family = rdev->family;
 512         r = radeon_cs_parser_init(&parser, data);
 513         if (r) {
 514                 DRM_ERROR("Failed to initialize parser !\n");
 515                 radeon_cs_parser_fini(&parser, r);
 516                 up_read(&rdev->exclusive_lock);
 517                 r = radeon_cs_handle_lockup(rdev, r);
 518                 return r;
 519         }
 520         r = radeon_cs_parser_relocs(&parser);
 521         if (r) {
 522                 if (r != -ERESTARTSYS)
 523                         DRM_ERROR("Failed to parse relocation %d!\n", r);
 524                 radeon_cs_parser_fini(&parser, r);
 525                 up_read(&rdev->exclusive_lock);
 526                 r = radeon_cs_handle_lockup(rdev, r);
 527                 return r;
 528         }
 529         r = radeon_cs_ib_chunk(rdev, &parser);
 530         if (r) {
 531                 goto out;
 532         }
 533         r = radeon_cs_ib_vm_chunk(rdev, &parser);
 534         if (r) {
 535                 goto out;
 536         }
 537 out:
 538         radeon_cs_parser_fini(&parser, r);
 539         up_read(&rdev->exclusive_lock);
 540         r = radeon_cs_handle_lockup(rdev, r);
 541         return r;
 542 }
 543
 544 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
 545 {
 546         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 547         int i;
 548         int size = PAGE_SIZE;
 549
 550         for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
 551                 if (i == ibc->last_page_index) {
 552                         size = (ibc->length_dw * 4) % PAGE_SIZE;
 553                         if (size == 0)
 554                                 size = PAGE_SIZE;
 555                 }
 556
 557                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
 558                                        ibc->user_ptr + (i * PAGE_SIZE),
 559                                        size))
 560                         return -EFAULT;
 561         }
 562         return 0;
 563 }
 564
 565 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
 566 {
 567         int new_page;
 568         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 569         int i;
 570         int size = PAGE_SIZE;
 571         bool copy1 = (p->rdev->flags & RADEON_IS_AGP) ? false : true;
 572
 573         for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
 574                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
 575                                        ibc->user_ptr + (i * PAGE_SIZE),
 576                                        PAGE_SIZE)) {
 577                         p->parser_error = -EFAULT;
 578                         return 0;
 579                 }
 580         }
 581
 582         if (pg_idx == ibc->last_page_index) {
 583                 size = (ibc->length_dw * 4) % PAGE_SIZE;
 584                 if (size == 0)
 585                         size = PAGE_SIZE;
 586         }
 587
 588         new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
 589         if (copy1)
 590                 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
 591
 592         if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
 593                                ibc->user_ptr + (pg_idx * PAGE_SIZE),
 594                                size)) {
 595                 p->parser_error = -EFAULT;
 596                 return 0;
 597         }
 598
 599         /* copy to IB for non single case */
 600         if (!copy1)
 601                 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
 602
 603         ibc->last_copied_page = pg_idx;
 604         ibc->kpage_idx[new_page] = pg_idx;
 605
 606         return new_page;
 607 }
 608
 609 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 610 {
 611         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 612         u32 pg_idx, pg_offset;
 613         u32 idx_value = 0;
 614         int new_page;
 615
 616         pg_idx = (idx * 4) / PAGE_SIZE;
 617         pg_offset = (idx * 4) % PAGE_SIZE;
 618
 619         if (ibc->kpage_idx[0] == pg_idx)
 620                 return ibc->kpage[0][pg_offset/4];
 621         if (ibc->kpage_idx[1] == pg_idx)
 622                 return ibc->kpage[1][pg_offset/4];
 623
 624         new_page = radeon_cs_update_pages(p, pg_idx);
 625         if (new_page < 0) {
 626                 p->parser_error = new_page;
 627                 return 0;
 628         }
 629
 630         idx_value = ibc->kpage[new_page][pg_offset/4];
 631         return idx_value;
 632 }