2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
28 #include <drm/radeon_drm.h>
29 #include "radeon_reg.h"
31 #include "radeon_trace.h"
33 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
35 struct drm_device *ddev = p->rdev->ddev;
36 struct radeon_cs_chunk *chunk;
40 if (p->chunk_relocs_idx == -1) {
43 chunk = &p->chunks[p->chunk_relocs_idx];
45 /* FIXME: we assume that each relocs use 4 dwords */
46 p->nrelocs = chunk->length_dw / 4;
47 p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
48 if (p->relocs_ptr == NULL) {
51 p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
52 if (p->relocs == NULL) {
55 for (i = 0; i < p->nrelocs; i++) {
56 struct drm_radeon_cs_reloc *r;
59 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
60 for (j = 0; j < i; j++) {
61 if (r->handle == p->relocs[j].handle) {
62 p->relocs_ptr[i] = &p->relocs[j];
68 p->relocs[i].handle = 0;
72 p->relocs[i].gobj = drm_gem_object_lookup(ddev, p->filp,
74 if (p->relocs[i].gobj == NULL) {
75 DRM_ERROR("gem object lookup failed 0x%x\n",
79 p->relocs_ptr[i] = &p->relocs[i];
80 p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
81 p->relocs[i].lobj.bo = p->relocs[i].robj;
82 p->relocs[i].lobj.written = !!r->write_domain;
84 /* the first reloc of an UVD job is the msg and that must be in
85 VRAM, also but everything into VRAM on AGP cards to avoid
87 if (p->ring == R600_RING_TYPE_UVD_INDEX &&
88 (i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
89 /* TODO: is this still needed for NI+ ? */
90 p->relocs[i].lobj.domain =
91 RADEON_GEM_DOMAIN_VRAM;
93 p->relocs[i].lobj.alt_domain =
94 RADEON_GEM_DOMAIN_VRAM;
97 uint32_t domain = r->write_domain ?
98 r->write_domain : r->read_domains;
100 p->relocs[i].lobj.domain = domain;
101 if (domain == RADEON_GEM_DOMAIN_VRAM)
102 domain |= RADEON_GEM_DOMAIN_GTT;
103 p->relocs[i].lobj.alt_domain = domain;
106 p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
107 p->relocs[i].handle = r->handle;
109 radeon_bo_list_add_object(&p->relocs[i].lobj,
112 return radeon_bo_list_validate(&p->ticket, &p->validated, p->ring);
115 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
117 p->priority = priority;
121 DRM_ERROR("unknown ring id: %d\n", ring);
123 case RADEON_CS_RING_GFX:
124 p->ring = RADEON_RING_TYPE_GFX_INDEX;
126 case RADEON_CS_RING_COMPUTE:
127 if (p->rdev->family >= CHIP_TAHITI) {
129 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
131 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
133 p->ring = RADEON_RING_TYPE_GFX_INDEX;
135 case RADEON_CS_RING_DMA:
136 if (p->rdev->family >= CHIP_CAYMAN) {
138 p->ring = R600_RING_TYPE_DMA_INDEX;
140 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
141 } else if (p->rdev->family >= CHIP_R600) {
142 p->ring = R600_RING_TYPE_DMA_INDEX;
147 case RADEON_CS_RING_UVD:
148 p->ring = R600_RING_TYPE_UVD_INDEX;
154 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
158 for (i = 0; i < p->nrelocs; i++) {
159 if (!p->relocs[i].robj)
162 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
166 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
167 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
169 struct drm_radeon_cs *cs = data;
170 uint64_t *chunk_array_ptr;
172 u32 ring = RADEON_CS_RING_GFX;
175 if (!cs->num_chunks) {
179 INIT_LIST_HEAD(&p->validated);
182 p->ib.semaphore = NULL;
183 p->const_ib.sa_bo = NULL;
184 p->const_ib.semaphore = NULL;
185 p->chunk_ib_idx = -1;
186 p->chunk_relocs_idx = -1;
187 p->chunk_flags_idx = -1;
188 p->chunk_const_ib_idx = -1;
189 p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
190 if (p->chunks_array == NULL) {
193 chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
194 if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
195 sizeof(uint64_t)*cs->num_chunks)) {
199 p->nchunks = cs->num_chunks;
200 p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
201 if (p->chunks == NULL) {
204 for (i = 0; i < p->nchunks; i++) {
205 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
206 struct drm_radeon_cs_chunk user_chunk;
207 uint32_t __user *cdata;
209 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
210 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
211 sizeof(struct drm_radeon_cs_chunk))) {
214 p->chunks[i].length_dw = user_chunk.length_dw;
215 p->chunks[i].chunk_id = user_chunk.chunk_id;
216 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
217 p->chunk_relocs_idx = i;
219 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
221 /* zero length IB isn't useful */
222 if (p->chunks[i].length_dw == 0)
225 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
226 p->chunk_const_ib_idx = i;
227 /* zero length CONST IB isn't useful */
228 if (p->chunks[i].length_dw == 0)
231 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
232 p->chunk_flags_idx = i;
233 /* zero length flags aren't useful */
234 if (p->chunks[i].length_dw == 0)
238 size = p->chunks[i].length_dw;
239 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
240 p->chunks[i].user_ptr = cdata;
241 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB)
244 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
245 if (!p->rdev || !(p->rdev->flags & RADEON_IS_AGP))
249 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
250 size *= sizeof(uint32_t);
251 if (p->chunks[i].kdata == NULL) {
254 if (DRM_COPY_FROM_USER(p->chunks[i].kdata, cdata, size)) {
257 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
258 p->cs_flags = p->chunks[i].kdata[0];
259 if (p->chunks[i].length_dw > 1)
260 ring = p->chunks[i].kdata[1];
261 if (p->chunks[i].length_dw > 2)
262 priority = (s32)p->chunks[i].kdata[2];
266 /* these are KMS only */
268 if ((p->cs_flags & RADEON_CS_USE_VM) &&
269 !p->rdev->vm_manager.enabled) {
270 DRM_ERROR("VM not active on asic!\n");
274 if (radeon_cs_get_ring(p, ring, priority))
277 /* we only support VM on some SI+ rings */
278 if ((p->rdev->asic->ring[p->ring]->cs_parse == NULL) &&
279 ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
280 DRM_ERROR("Ring %d requires VM!\n", p->ring);
289 * cs_parser_fini() - clean parser states
290 * @parser: parser structure holding parsing context.
291 * @error: error number
293 * If error is set than unvalidate buffer, otherwise just free memory
294 * used by parsing context.
296 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error, bool backoff)
301 ttm_eu_fence_buffer_objects(&parser->ticket,
304 } else if (backoff) {
305 ttm_eu_backoff_reservation(&parser->ticket,
309 if (parser->relocs != NULL) {
310 for (i = 0; i < parser->nrelocs; i++) {
311 if (parser->relocs[i].gobj)
312 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
315 kfree(parser->track);
316 kfree(parser->relocs);
317 kfree(parser->relocs_ptr);
318 for (i = 0; i < parser->nchunks; i++)
319 drm_free_large(parser->chunks[i].kdata);
320 kfree(parser->chunks);
321 kfree(parser->chunks_array);
322 radeon_ib_free(parser->rdev, &parser->ib);
323 radeon_ib_free(parser->rdev, &parser->const_ib);
326 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
327 struct radeon_cs_parser *parser)
331 if (parser->chunk_ib_idx == -1)
334 if (parser->cs_flags & RADEON_CS_USE_VM)
337 r = radeon_cs_parse(rdev, parser->ring, parser);
338 if (r || parser->parser_error) {
339 DRM_ERROR("Invalid command stream !\n");
343 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
344 radeon_uvd_note_usage(rdev);
346 radeon_cs_sync_rings(parser);
347 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
349 DRM_ERROR("Failed to schedule IB !\n");
354 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
355 struct radeon_vm *vm)
357 struct radeon_device *rdev = parser->rdev;
358 struct radeon_bo_list *lobj;
359 struct radeon_bo *bo;
362 r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
366 list_for_each_entry(lobj, &parser->validated, tv.head) {
368 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
376 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
377 struct radeon_cs_parser *parser)
379 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
380 struct radeon_vm *vm = &fpriv->vm;
383 if (parser->chunk_ib_idx == -1)
385 if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
388 if (parser->const_ib.length_dw) {
389 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
395 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
400 if (parser->ring == R600_RING_TYPE_UVD_INDEX)
401 radeon_uvd_note_usage(rdev);
403 mutex_lock(&rdev->vm_manager.lock);
404 mutex_lock(&vm->mutex);
405 r = radeon_vm_alloc_pt(rdev, vm);
409 r = radeon_bo_vm_update_pte(parser, vm);
413 radeon_cs_sync_rings(parser);
414 radeon_ib_sync_to(&parser->ib, vm->fence);
415 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
416 rdev, vm, parser->ring));
418 if ((rdev->family >= CHIP_TAHITI) &&
419 (parser->chunk_const_ib_idx != -1)) {
420 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
422 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
426 radeon_vm_fence(rdev, vm, parser->ib.fence);
430 radeon_vm_add_to_lru(rdev, vm);
431 mutex_unlock(&vm->mutex);
432 mutex_unlock(&rdev->vm_manager.lock);
436 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
439 r = radeon_gpu_reset(rdev);
446 static int radeon_cs_ib_fill(struct radeon_device *rdev, struct radeon_cs_parser *parser)
448 struct radeon_cs_chunk *ib_chunk;
449 struct radeon_vm *vm = NULL;
452 if (parser->chunk_ib_idx == -1)
455 if (parser->cs_flags & RADEON_CS_USE_VM) {
456 struct radeon_fpriv *fpriv = parser->filp->driver_priv;
459 if ((rdev->family >= CHIP_TAHITI) &&
460 (parser->chunk_const_ib_idx != -1)) {
461 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
462 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
463 DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
466 r = radeon_ib_get(rdev, parser->ring, &parser->const_ib,
467 vm, ib_chunk->length_dw * 4);
469 DRM_ERROR("Failed to get const ib !\n");
472 parser->const_ib.is_const_ib = true;
473 parser->const_ib.length_dw = ib_chunk->length_dw;
474 if (DRM_COPY_FROM_USER(parser->const_ib.ptr,
476 ib_chunk->length_dw * 4))
480 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
481 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
482 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
486 ib_chunk = &parser->chunks[parser->chunk_ib_idx];
488 r = radeon_ib_get(rdev, parser->ring, &parser->ib,
489 vm, ib_chunk->length_dw * 4);
491 DRM_ERROR("Failed to get ib !\n");
494 parser->ib.length_dw = ib_chunk->length_dw;
496 memcpy(parser->ib.ptr, ib_chunk->kdata, ib_chunk->length_dw * 4);
497 else if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr, ib_chunk->length_dw * 4))
502 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
504 struct radeon_device *rdev = dev->dev_private;
505 struct radeon_cs_parser parser;
508 down_read(&rdev->exclusive_lock);
509 if (!rdev->accel_working) {
510 up_read(&rdev->exclusive_lock);
513 /* initialize parser */
514 memset(&parser, 0, sizeof(struct radeon_cs_parser));
517 parser.dev = rdev->dev;
518 parser.family = rdev->family;
519 r = radeon_cs_parser_init(&parser, data);
521 DRM_ERROR("Failed to initialize parser !\n");
522 radeon_cs_parser_fini(&parser, r, false);
523 up_read(&rdev->exclusive_lock);
524 r = radeon_cs_handle_lockup(rdev, r);
528 r = radeon_cs_ib_fill(rdev, &parser);
530 r = radeon_cs_parser_relocs(&parser);
531 if (r && r != -ERESTARTSYS)
532 DRM_ERROR("Failed to parse relocation %d!\n", r);
536 radeon_cs_parser_fini(&parser, r, false);
537 up_read(&rdev->exclusive_lock);
538 r = radeon_cs_handle_lockup(rdev, r);
542 trace_radeon_cs(&parser);
544 r = radeon_cs_ib_chunk(rdev, &parser);
548 r = radeon_cs_ib_vm_chunk(rdev, &parser);
553 radeon_cs_parser_fini(&parser, r, true);
554 up_read(&rdev->exclusive_lock);
555 r = radeon_cs_handle_lockup(rdev, r);
560 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
561 * @parser: parser structure holding parsing context.
562 * @pkt: where to store packet information
564 * Assume that chunk_ib_index is properly set. Will return -EINVAL
565 * if packet is bigger than remaining ib size. or if packets is unknown.
567 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
568 struct radeon_cs_packet *pkt,
571 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
572 struct radeon_device *rdev = p->rdev;
575 if (idx >= ib_chunk->length_dw) {
576 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
577 idx, ib_chunk->length_dw);
580 header = radeon_get_ib_value(p, idx);
582 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
583 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
586 case RADEON_PACKET_TYPE0:
587 if (rdev->family < CHIP_R600) {
588 pkt->reg = R100_CP_PACKET0_GET_REG(header);
590 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
592 pkt->reg = R600_CP_PACKET0_GET_REG(header);
594 case RADEON_PACKET_TYPE3:
595 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
597 case RADEON_PACKET_TYPE2:
601 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
604 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
605 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
606 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
613 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
614 * @p: structure holding the parser context.
616 * Check if the next packet is NOP relocation packet3.
618 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
620 struct radeon_cs_packet p3reloc;
623 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
626 if (p3reloc.type != RADEON_PACKET_TYPE3)
628 if (p3reloc.opcode != RADEON_PACKET3_NOP)
634 * radeon_cs_dump_packet() - dump raw packet context
635 * @p: structure holding the parser context.
636 * @pkt: structure holding the packet.
638 * Used mostly for debugging and error reporting.
640 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
641 struct radeon_cs_packet *pkt)
643 volatile uint32_t *ib;
649 for (i = 0; i <= (pkt->count + 1); i++, idx++)
650 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
654 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
655 * @parser: parser structure holding parsing context.
656 * @data: pointer to relocation data
657 * @offset_start: starting offset
658 * @offset_mask: offset mask (to align start offset on)
659 * @reloc: reloc informations
661 * Check if next packet is relocation packet3, do bo validation and compute
662 * GPU offset using the provided start.
664 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
665 struct radeon_cs_reloc **cs_reloc,
668 struct radeon_cs_chunk *relocs_chunk;
669 struct radeon_cs_packet p3reloc;
673 if (p->chunk_relocs_idx == -1) {
674 DRM_ERROR("No relocation chunk !\n");
678 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
679 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
682 p->idx += p3reloc.count + 2;
683 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
684 p3reloc.opcode != RADEON_PACKET3_NOP) {
685 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
687 radeon_cs_dump_packet(p, &p3reloc);
690 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
691 if (idx >= relocs_chunk->length_dw) {
692 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
693 idx, relocs_chunk->length_dw);
694 radeon_cs_dump_packet(p, &p3reloc);
697 /* FIXME: we assume reloc size is 4 dwords */
699 *cs_reloc = p->relocs;
700 (*cs_reloc)->lobj.gpu_offset =
701 (u64)relocs_chunk->kdata[idx + 3] << 32;
702 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
704 *cs_reloc = p->relocs_ptr[(idx / 4)];