drivers/gpu/drm/radeon/radeon_display.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/radeon_drm.h>
  28 #include "radeon.h"
  29
  30 #include "atom.h"
  31 #include <asm/div64.h>
  32
  33 #include <linux/pm_runtime.h>
  34 #include <drm/drm_crtc_helper.h>
  35 #include <drm/drm_edid.h>
  36
  37 #include <linux/gcd.h>
  38
  39 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
  40 {
  41         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  42         struct drm_device *dev = crtc->dev;
  43         struct radeon_device *rdev = dev->dev_private;
  44         int i;
  45
  46         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  47         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
  48
  49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  51         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  52
  53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  55         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  56
  57         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
  58         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
  59         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
  60
  61         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
  62         for (i = 0; i < 256; i++) {
  63                 WREG32(AVIVO_DC_LUT_30_COLOR,
  64                              (radeon_crtc->lut_r[i] << 20) |
  65                              (radeon_crtc->lut_g[i] << 10) |
  66                              (radeon_crtc->lut_b[i] << 0));
  67         }
  68
  69         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
  70 }
  71
  72 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
  73 {
  74         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  75         struct drm_device *dev = crtc->dev;
  76         struct radeon_device *rdev = dev->dev_private;
  77         int i;
  78
  79         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
  80         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
  81
  82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
  83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
  84         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
  85
  86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
  87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
  88         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
  89
  90         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
  91         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
  92
  93         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
  94         for (i = 0; i < 256; i++) {
  95                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
  96                        (radeon_crtc->lut_r[i] << 20) |
  97                        (radeon_crtc->lut_g[i] << 10) |
  98                        (radeon_crtc->lut_b[i] << 0));
  99         }
 100 }
 101
 102 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
 103 {
 104         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 105         struct drm_device *dev = crtc->dev;
 106         struct radeon_device *rdev = dev->dev_private;
 107         int i;
 108
 109         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
 110
 111         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 112                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
 113                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
 114         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
 115                NI_GRPH_PRESCALE_BYPASS);
 116         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
 117                NI_OVL_PRESCALE_BYPASS);
 118         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
 119                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
 120                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
 121
 122         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
 123
 124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
 125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
 126         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
 127
 128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
 129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
 130         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
 131
 132         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
 133         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
 134
 135         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
 136         for (i = 0; i < 256; i++) {
 137                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
 138                        (radeon_crtc->lut_r[i] << 20) |
 139                        (radeon_crtc->lut_g[i] << 10) |
 140                        (radeon_crtc->lut_b[i] << 0));
 141         }
 142
 143         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
 144                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 145                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 146                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
 147                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
 148         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
 149                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
 150                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
 151         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
 152                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
 153                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
 154         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
 155                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
 156                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
 157         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
 158         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
 159         if (ASIC_IS_DCE8(rdev)) {
 160                 /* XXX this only needs to be programmed once per crtc at startup,
 161                  * not sure where the best place for it is
 162                  */
 163                 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset,
 164                        CIK_CURSOR_ALPHA_BLND_ENA);
 165         }
 166 }
 167
 168 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
 169 {
 170         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 171         struct drm_device *dev = crtc->dev;
 172         struct radeon_device *rdev = dev->dev_private;
 173         int i;
 174         uint32_t dac2_cntl;
 175
 176         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
 177         if (radeon_crtc->crtc_id == 0)
 178                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
 179         else
 180                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
 181         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 182
 183         WREG8(RADEON_PALETTE_INDEX, 0);
 184         for (i = 0; i < 256; i++) {
 185                 WREG32(RADEON_PALETTE_30_DATA,
 186                              (radeon_crtc->lut_r[i] << 20) |
 187                              (radeon_crtc->lut_g[i] << 10) |
 188                              (radeon_crtc->lut_b[i] << 0));
 189         }
 190 }
 191
 192 void radeon_crtc_load_lut(struct drm_crtc *crtc)
 193 {
 194         struct drm_device *dev = crtc->dev;
 195         struct radeon_device *rdev = dev->dev_private;
 196
 197         if (!crtc->enabled)
 198                 return;
 199
 200         if (ASIC_IS_DCE5(rdev))
 201                 dce5_crtc_load_lut(crtc);
 202         else if (ASIC_IS_DCE4(rdev))
 203                 dce4_crtc_load_lut(crtc);
 204         else if (ASIC_IS_AVIVO(rdev))
 205                 avivo_crtc_load_lut(crtc);
 206         else
 207                 legacy_crtc_load_lut(crtc);
 208 }
 209
 210 /** Sets the color ramps on behalf of fbcon */
 211 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
 212                               u16 blue, int regno)
 213 {
 214         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 215
 216         radeon_crtc->lut_r[regno] = red >> 6;
 217         radeon_crtc->lut_g[regno] = green >> 6;
 218         radeon_crtc->lut_b[regno] = blue >> 6;
 219 }
 220
 221 /** Gets the color ramps on behalf of fbcon */
 222 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
 223                               u16 *blue, int regno)
 224 {
 225         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 226
 227         *red = radeon_crtc->lut_r[regno] << 6;
 228         *green = radeon_crtc->lut_g[regno] << 6;
 229         *blue = radeon_crtc->lut_b[regno] << 6;
 230 }
 231
 232 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
 233                                   u16 *blue, uint32_t start, uint32_t size)
 234 {
 235         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 236         int end = (start + size > 256) ? 256 : start + size, i;
 237
 238         /* userspace palettes are always correct as is */
 239         for (i = start; i < end; i++) {
 240                 radeon_crtc->lut_r[i] = red[i] >> 6;
 241                 radeon_crtc->lut_g[i] = green[i] >> 6;
 242                 radeon_crtc->lut_b[i] = blue[i] >> 6;
 243         }
 244         radeon_crtc_load_lut(crtc);
 245 }
 246
 247 static void radeon_crtc_destroy(struct drm_crtc *crtc)
 248 {
 249         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 250
 251         drm_crtc_cleanup(crtc);
 252         kfree(radeon_crtc);
 253 }
 254
 255 /*
 256  * Handle unpin events outside the interrupt handler proper.
 257  */
 258 static void radeon_unpin_work_func(struct work_struct *__work)
 259 {
 260         struct radeon_unpin_work *work =
 261                 container_of(__work, struct radeon_unpin_work, work);
 262         int r;
 263
 264         /* unpin of the old buffer */
 265         r = radeon_bo_reserve(work->old_rbo, false);
 266         if (likely(r == 0)) {
 267                 r = radeon_bo_unpin(work->old_rbo);
 268                 if (unlikely(r != 0)) {
 269                         DRM_ERROR("failed to unpin buffer after flip\n");
 270                 }
 271                 radeon_bo_unreserve(work->old_rbo);
 272         } else
 273                 DRM_ERROR("failed to reserve buffer after flip\n");
 274
 275         drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
 276         kfree(work);
 277 }
 278
 279 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 280 {
 281         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 282         struct radeon_unpin_work *work;
 283         unsigned long flags;
 284         u32 update_pending;
 285         int vpos, hpos;
 286
 287         /* can happen during initialization */
 288         if (radeon_crtc == NULL)
 289                 return;
 290
 291         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
 292         work = radeon_crtc->unpin_work;
 293         if (work == NULL ||
 294             (work->fence && !radeon_fence_signaled(work->fence))) {
 295                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 296                 return;
 297         }
 298         /* New pageflip, or just completion of a previous one? */
 299         if (!radeon_crtc->deferred_flip_completion) {
 300                 /* do the flip (mmio) */
 301                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
 302         } else {
 303                 /* This is just a completion of a flip queued in crtc
 304                  * at last invocation. Make sure we go directly to
 305                  * completion routine.
 306                  */
 307                 update_pending = 0;
 308                 radeon_crtc->deferred_flip_completion = 0;
 309         }
 310
 311         /* Has the pageflip already completed in crtc, or is it certain
 312          * to complete in this vblank?
 313          */
 314         if (update_pending &&
 315             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, 0,
 316                                                                &vpos, &hpos, NULL, NULL)) &&
 317             ((vpos >= (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100) ||
 318              (vpos < 0 && !ASIC_IS_AVIVO(rdev)))) {
 319                 /* crtc didn't flip in this target vblank interval,
 320                  * but flip is pending in crtc. Based on the current
 321                  * scanout position we know that the current frame is
 322                  * (nearly) complete and the flip will (likely)
 323                  * complete before the start of the next frame.
 324                  */
 325                 update_pending = 0;
 326         }
 327         if (update_pending) {
 328                 /* crtc didn't flip in this target vblank interval,
 329                  * but flip is pending in crtc. It will complete it
 330                  * in next vblank interval, so complete the flip at
 331                  * next vblank irq.
 332                  */
 333                 radeon_crtc->deferred_flip_completion = 1;
 334                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 335                 return;
 336         }
 337
 338         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
 339         radeon_crtc->unpin_work = NULL;
 340
 341         /* wakeup userspace */
 342         if (work->event)
 343                 drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
 344
 345         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 346
 347         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
 348         radeon_fence_unref(&work->fence);
 349         radeon_post_page_flip(work->rdev, work->crtc_id);
 350         schedule_work(&work->work);
 351 }
 352
 353 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
 354                                  struct drm_framebuffer *fb,
 355                                  struct drm_pending_vblank_event *event,
 356                                  uint32_t page_flip_flags)
 357 {
 358         struct drm_device *dev = crtc->dev;
 359         struct radeon_device *rdev = dev->dev_private;
 360         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 361         struct radeon_framebuffer *old_radeon_fb;
 362         struct radeon_framebuffer *new_radeon_fb;
 363         struct drm_gem_object *obj;
 364         struct radeon_bo *rbo;
 365         struct radeon_unpin_work *work;
 366         unsigned long flags;
 367         u32 tiling_flags, pitch_pixels;
 368         u64 base;
 369         int r;
 370
 371         work = kzalloc(sizeof *work, GFP_KERNEL);
 372         if (work == NULL)
 373                 return -ENOMEM;
 374
 375         work->event = event;
 376         work->rdev = rdev;
 377         work->crtc_id = radeon_crtc->crtc_id;
 378         old_radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
 379         new_radeon_fb = to_radeon_framebuffer(fb);
 380         /* schedule unpin of the old buffer */
 381         obj = old_radeon_fb->obj;
 382         /* take a reference to the old object */
 383         drm_gem_object_reference(obj);
 384         rbo = gem_to_radeon_bo(obj);
 385         work->old_rbo = rbo;
 386         obj = new_radeon_fb->obj;
 387         rbo = gem_to_radeon_bo(obj);
 388
 389         spin_lock(&rbo->tbo.bdev->fence_lock);
 390         if (rbo->tbo.sync_obj)
 391                 work->fence = radeon_fence_ref(rbo->tbo.sync_obj);
 392         spin_unlock(&rbo->tbo.bdev->fence_lock);
 393
 394         INIT_WORK(&work->work, radeon_unpin_work_func);
 395
 396         /* We borrow the event spin lock for protecting unpin_work */
 397         spin_lock_irqsave(&dev->event_lock, flags);
 398         if (radeon_crtc->unpin_work) {
 399                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
 400                 r = -EBUSY;
 401                 goto unlock_free;
 402         }
 403         radeon_crtc->unpin_work = work;
 404         radeon_crtc->deferred_flip_completion = 0;
 405         spin_unlock_irqrestore(&dev->event_lock, flags);
 406
 407         /* pin the new buffer */
 408         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
 409                          work->old_rbo, rbo);
 410
 411         r = radeon_bo_reserve(rbo, false);
 412         if (unlikely(r != 0)) {
 413                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
 414                 goto pflip_cleanup;
 415         }
 416         /* Only 27 bit offset for legacy CRTC */
 417         r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM,
 418                                      ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27, &base);
 419         if (unlikely(r != 0)) {
 420                 radeon_bo_unreserve(rbo);
 421                 r = -EINVAL;
 422                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
 423                 goto pflip_cleanup;
 424         }
 425         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
 426         radeon_bo_unreserve(rbo);
 427
 428         if (!ASIC_IS_AVIVO(rdev)) {
 429                 /* crtc offset is from display base addr not FB location */
 430                 base -= radeon_crtc->legacy_display_base_addr;
 431                 pitch_pixels = fb->pitches[0] / (fb->bits_per_pixel / 8);
 432
 433                 if (tiling_flags & RADEON_TILING_MACRO) {
 434                         if (ASIC_IS_R300(rdev)) {
 435                                 base &= ~0x7ff;
 436                         } else {
 437                                 int byteshift = fb->bits_per_pixel >> 4;
 438                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
 439                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
 440                         }
 441                 } else {
 442                         int offset = crtc->y * pitch_pixels + crtc->x;
 443                         switch (fb->bits_per_pixel) {
 444                         case 8:
 445                         default:
 446                                 offset *= 1;
 447                                 break;
 448                         case 15:
 449                         case 16:
 450                                 offset *= 2;
 451                                 break;
 452                         case 24:
 453                                 offset *= 3;
 454                                 break;
 455                         case 32:
 456                                 offset *= 4;
 457                                 break;
 458                         }
 459                         base += offset;
 460                 }
 461                 base &= ~7;
 462         }
 463
 464         spin_lock_irqsave(&dev->event_lock, flags);
 465         work->new_crtc_base = base;
 466         spin_unlock_irqrestore(&dev->event_lock, flags);
 467
 468         /* update crtc fb */
 469         crtc->primary->fb = fb;
 470
 471         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
 472         if (r) {
 473                 DRM_ERROR("failed to get vblank before flip\n");
 474                 goto pflip_cleanup1;
 475         }
 476
 477         /* set the proper interrupt */
 478         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
 479
 480         return 0;
 481
 482 pflip_cleanup1:
 483         if (unlikely(radeon_bo_reserve(rbo, false) != 0)) {
 484                 DRM_ERROR("failed to reserve new rbo in error path\n");
 485                 goto pflip_cleanup;
 486         }
 487         if (unlikely(radeon_bo_unpin(rbo) != 0)) {
 488                 DRM_ERROR("failed to unpin new rbo in error path\n");
 489         }
 490         radeon_bo_unreserve(rbo);
 491
 492 pflip_cleanup:
 493         spin_lock_irqsave(&dev->event_lock, flags);
 494         radeon_crtc->unpin_work = NULL;
 495 unlock_free:
 496         spin_unlock_irqrestore(&dev->event_lock, flags);
 497         drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
 498         radeon_fence_unref(&work->fence);
 499         kfree(work);
 500
 501         return r;
 502 }
 503
 504 static int
 505 radeon_crtc_set_config(struct drm_mode_set *set)
 506 {
 507         struct drm_device *dev;
 508         struct radeon_device *rdev;
 509         struct drm_crtc *crtc;
 510         bool active = false;
 511         int ret;
 512
 513         if (!set || !set->crtc)
 514                 return -EINVAL;
 515
 516         dev = set->crtc->dev;
 517
 518         ret = pm_runtime_get_sync(dev->dev);
 519         if (ret < 0)
 520                 return ret;
 521
 522         ret = drm_crtc_helper_set_config(set);
 523
 524         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 525                 if (crtc->enabled)
 526                         active = true;
 527
 528         pm_runtime_mark_last_busy(dev->dev);
 529
 530         rdev = dev->dev_private;
 531         /* if we have active crtcs and we don't have a power ref,
 532            take the current one */
 533         if (active && !rdev->have_disp_power_ref) {
 534                 rdev->have_disp_power_ref = true;
 535                 return ret;
 536         }
 537         /* if we have no active crtcs, then drop the power ref
 538            we got before */
 539         if (!active && rdev->have_disp_power_ref) {
 540                 pm_runtime_put_autosuspend(dev->dev);
 541                 rdev->have_disp_power_ref = false;
 542         }
 543
 544         /* drop the power reference we got coming in here */
 545         pm_runtime_put_autosuspend(dev->dev);
 546         return ret;
 547 }
 548 static const struct drm_crtc_funcs radeon_crtc_funcs = {
 549         .cursor_set = radeon_crtc_cursor_set,
 550         .cursor_move = radeon_crtc_cursor_move,
 551         .gamma_set = radeon_crtc_gamma_set,
 552         .set_config = radeon_crtc_set_config,
 553         .destroy = radeon_crtc_destroy,
 554         .page_flip = radeon_crtc_page_flip,
 555 };
 556
 557 static void radeon_crtc_init(struct drm_device *dev, int index)
 558 {
 559         struct radeon_device *rdev = dev->dev_private;
 560         struct radeon_crtc *radeon_crtc;
 561         int i;
 562
 563         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
 564         if (radeon_crtc == NULL)
 565                 return;
 566
 567         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
 568
 569         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
 570         radeon_crtc->crtc_id = index;
 571         rdev->mode_info.crtcs[index] = radeon_crtc;
 572
 573         if (rdev->family >= CHIP_BONAIRE) {
 574                 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH;
 575                 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT;
 576         } else {
 577                 radeon_crtc->max_cursor_width = CURSOR_WIDTH;
 578                 radeon_crtc->max_cursor_height = CURSOR_HEIGHT;
 579         }
 580         dev->mode_config.cursor_width = radeon_crtc->max_cursor_width;
 581         dev->mode_config.cursor_height = radeon_crtc->max_cursor_height;
 582
 583 #if 0
 584         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
 585         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
 586         radeon_crtc->mode_set.num_connectors = 0;
 587 #endif
 588
 589         for (i = 0; i < 256; i++) {
 590                 radeon_crtc->lut_r[i] = i << 2;
 591                 radeon_crtc->lut_g[i] = i << 2;
 592                 radeon_crtc->lut_b[i] = i << 2;
 593         }
 594
 595         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
 596                 radeon_atombios_init_crtc(dev, radeon_crtc);
 597         else
 598                 radeon_legacy_init_crtc(dev, radeon_crtc);
 599 }
 600
 601 static const char *encoder_names[38] = {
 602         "NONE",
 603         "INTERNAL_LVDS",
 604         "INTERNAL_TMDS1",
 605         "INTERNAL_TMDS2",
 606         "INTERNAL_DAC1",
 607         "INTERNAL_DAC2",
 608         "INTERNAL_SDVOA",
 609         "INTERNAL_SDVOB",
 610         "SI170B",
 611         "CH7303",
 612         "CH7301",
 613         "INTERNAL_DVO1",
 614         "EXTERNAL_SDVOA",
 615         "EXTERNAL_SDVOB",
 616         "TITFP513",
 617         "INTERNAL_LVTM1",
 618         "VT1623",
 619         "HDMI_SI1930",
 620         "HDMI_INTERNAL",
 621         "INTERNAL_KLDSCP_TMDS1",
 622         "INTERNAL_KLDSCP_DVO1",
 623         "INTERNAL_KLDSCP_DAC1",
 624         "INTERNAL_KLDSCP_DAC2",
 625         "SI178",
 626         "MVPU_FPGA",
 627         "INTERNAL_DDI",
 628         "VT1625",
 629         "HDMI_SI1932",
 630         "DP_AN9801",
 631         "DP_DP501",
 632         "INTERNAL_UNIPHY",
 633         "INTERNAL_KLDSCP_LVTMA",
 634         "INTERNAL_UNIPHY1",
 635         "INTERNAL_UNIPHY2",
 636         "NUTMEG",
 637         "TRAVIS",
 638         "INTERNAL_VCE",
 639         "INTERNAL_UNIPHY3",
 640 };
 641
 642 static const char *hpd_names[6] = {
 643         "HPD1",
 644         "HPD2",
 645         "HPD3",
 646         "HPD4",
 647         "HPD5",
 648         "HPD6",
 649 };
 650
 651 static void radeon_print_display_setup(struct drm_device *dev)
 652 {
 653         struct drm_connector *connector;
 654         struct radeon_connector *radeon_connector;
 655         struct drm_encoder *encoder;
 656         struct radeon_encoder *radeon_encoder;
 657         uint32_t devices;
 658         int i = 0;
 659
 660         DRM_INFO("Radeon Display Connectors\n");
 661         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 662                 radeon_connector = to_radeon_connector(connector);
 663                 DRM_INFO("Connector %d:\n", i);
 664                 DRM_INFO("  %s\n", drm_get_connector_name(connector));
 665                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
 666                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
 667                 if (radeon_connector->ddc_bus) {
 668                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
 669                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
 670                                  radeon_connector->ddc_bus->rec.mask_data_reg,
 671                                  radeon_connector->ddc_bus->rec.a_clk_reg,
 672                                  radeon_connector->ddc_bus->rec.a_data_reg,
 673                                  radeon_connector->ddc_bus->rec.en_clk_reg,
 674                                  radeon_connector->ddc_bus->rec.en_data_reg,
 675                                  radeon_connector->ddc_bus->rec.y_clk_reg,
 676                                  radeon_connector->ddc_bus->rec.y_data_reg);
 677                         if (radeon_connector->router.ddc_valid)
 678                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
 679                                          radeon_connector->router.ddc_mux_control_pin,
 680                                          radeon_connector->router.ddc_mux_state);
 681                         if (radeon_connector->router.cd_valid)
 682                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
 683                                          radeon_connector->router.cd_mux_control_pin,
 684                                          radeon_connector->router.cd_mux_state);
 685                 } else {
 686                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
 687                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
 688                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
 689                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
 690                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
 691                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
 692                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
 693                 }
 694                 DRM_INFO("  Encoders:\n");
 695                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 696                         radeon_encoder = to_radeon_encoder(encoder);
 697                         devices = radeon_encoder->devices & radeon_connector->devices;
 698                         if (devices) {
 699                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
 700                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 701                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
 702                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 703                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
 704                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 705                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
 706                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 707                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
 708                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
 709                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
 710                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
 711                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
 712                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
 713                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
 714                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
 715                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
 716                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
 717                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
 718                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
 719                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
 720                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
 721                         }
 722                 }
 723                 i++;
 724         }
 725 }
 726
 727 static bool radeon_setup_enc_conn(struct drm_device *dev)
 728 {
 729         struct radeon_device *rdev = dev->dev_private;
 730         bool ret = false;
 731
 732         if (rdev->bios) {
 733                 if (rdev->is_atom_bios) {
 734                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
 735                         if (ret == false)
 736                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
 737                 } else {
 738                         ret = radeon_get_legacy_connector_info_from_bios(dev);
 739                         if (ret == false)
 740                                 ret = radeon_get_legacy_connector_info_from_table(dev);
 741                 }
 742         } else {
 743                 if (!ASIC_IS_AVIVO(rdev))
 744                         ret = radeon_get_legacy_connector_info_from_table(dev);
 745         }
 746         if (ret) {
 747                 radeon_setup_encoder_clones(dev);
 748                 radeon_print_display_setup(dev);
 749         }
 750
 751         return ret;
 752 }
 753
 754 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
 755 {
 756         struct drm_device *dev = radeon_connector->base.dev;
 757         struct radeon_device *rdev = dev->dev_private;
 758         int ret = 0;
 759
 760         /* on hw with routers, select right port */
 761         if (radeon_connector->router.ddc_valid)
 762                 radeon_router_select_ddc_port(radeon_connector);
 763
 764         if (radeon_connector_encoder_get_dp_bridge_encoder_id(&radeon_connector->base) !=
 765             ENCODER_OBJECT_ID_NONE) {
 766                 if (radeon_connector->ddc_bus->has_aux)
 767                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 768                                                               &radeon_connector->ddc_bus->aux.ddc);
 769         } else if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
 770                    (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
 771                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
 772
 773                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
 774                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) &&
 775                     radeon_connector->ddc_bus->has_aux)
 776                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 777                                                               &radeon_connector->ddc_bus->aux.ddc);
 778                 else if (radeon_connector->ddc_bus && !radeon_connector->edid)
 779                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 780                                                               &radeon_connector->ddc_bus->adapter);
 781         } else {
 782                 if (radeon_connector->ddc_bus && !radeon_connector->edid)
 783                         radeon_connector->edid = drm_get_edid(&radeon_connector->base,
 784                                                               &radeon_connector->ddc_bus->adapter);
 785         }
 786
 787         if (!radeon_connector->edid) {
 788                 if (rdev->is_atom_bios) {
 789                         /* some laptops provide a hardcoded edid in rom for LCDs */
 790                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
 791                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
 792                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 793                 } else
 794                         /* some servers provide a hardcoded edid in rom for KVMs */
 795                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
 796         }
 797         if (radeon_connector->edid) {
 798                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 799                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 800                 drm_edid_to_eld(&radeon_connector->base, radeon_connector->edid);
 801                 return ret;
 802         }
 803         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
 804         return 0;
 805 }
 806
 807 /* avivo */
 808
 809 /**
 810  * avivo_reduce_ratio - fractional number reduction
 811  *
 812  * @nom: nominator
 813  * @den: denominator
 814  * @nom_min: minimum value for nominator
 815  * @den_min: minimum value for denominator
 816  *
 817  * Find the greatest common divisor and apply it on both nominator and
 818  * denominator, but make nominator and denominator are at least as large
 819  * as their minimum values.
 820  */
 821 static void avivo_reduce_ratio(unsigned *nom, unsigned *den,
 822                                unsigned nom_min, unsigned den_min)
 823 {
 824         unsigned tmp;
 825
 826         /* reduce the numbers to a simpler ratio */
 827         tmp = gcd(*nom, *den);
 828         *nom /= tmp;
 829         *den /= tmp;
 830
 831         /* make sure nominator is large enough */
 832         if (*nom < nom_min) {
 833                 tmp = DIV_ROUND_UP(nom_min, *nom);
 834                 *nom *= tmp;
 835                 *den *= tmp;
 836         }
 837
 838         /* make sure the denominator is large enough */
 839         if (*den < den_min) {
 840                 tmp = DIV_ROUND_UP(den_min, *den);
 841                 *nom *= tmp;
 842                 *den *= tmp;
 843         }
 844 }
 845
 846 /**
 847  * avivo_get_fb_ref_div - feedback and ref divider calculation
 848  *
 849  * @nom: nominator
 850  * @den: denominator
 851  * @post_div: post divider
 852  * @fb_div_max: feedback divider maximum
 853  * @ref_div_max: reference divider maximum
 854  * @fb_div: resulting feedback divider
 855  * @ref_div: resulting reference divider
 856  *
 857  * Calculate feedback and reference divider for a given post divider. Makes
 858  * sure we stay within the limits.
 859  */
 860 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
 861                                  unsigned fb_div_max, unsigned ref_div_max,
 862                                  unsigned *fb_div, unsigned *ref_div)
 863 {
 864         /* limit reference * post divider to a maximum */
 865         ref_div_max = max(min(100 / post_div, ref_div_max), 1u);
 866
 867         /* get matching reference and feedback divider */
 868         *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
 869         *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den);
 870
 871         /* limit fb divider to its maximum */
 872         if (*fb_div > fb_div_max) {
 873                 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div);
 874                 *fb_div = fb_div_max;
 875         }
 876 }
 877
 878 /**
 879  * radeon_compute_pll_avivo - compute PLL paramaters
 880  *
 881  * @pll: information about the PLL
 882  * @dot_clock_p: resulting pixel clock
 883  * fb_div_p: resulting feedback divider
 884  * frac_fb_div_p: fractional part of the feedback divider
 885  * ref_div_p: resulting reference divider
 886  * post_div_p: resulting reference divider
 887  *
 888  * Try to calculate the PLL parameters to generate the given frequency:
 889  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
 890  */
 891 void radeon_compute_pll_avivo(struct radeon_pll *pll,
 892                               u32 freq,
 893                               u32 *dot_clock_p,
 894                               u32 *fb_div_p,
 895                               u32 *frac_fb_div_p,
 896                               u32 *ref_div_p,
 897                               u32 *post_div_p)
 898 {
 899         unsigned target_clock = pll->flags & RADEON_PLL_USE_FRAC_FB_DIV ?
 900                 freq : freq / 10;
 901
 902         unsigned fb_div_min, fb_div_max, fb_div;
 903         unsigned post_div_min, post_div_max, post_div;
 904         unsigned ref_div_min, ref_div_max, ref_div;
 905         unsigned post_div_best, diff_best;
 906         unsigned nom, den;
 907
 908         /* determine allowed feedback divider range */
 909         fb_div_min = pll->min_feedback_div;
 910         fb_div_max = pll->max_feedback_div;
 911
 912         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 913                 fb_div_min *= 10;
 914                 fb_div_max *= 10;
 915         }
 916
 917         /* determine allowed ref divider range */
 918         if (pll->flags & RADEON_PLL_USE_REF_DIV)
 919                 ref_div_min = pll->reference_div;
 920         else
 921                 ref_div_min = pll->min_ref_div;
 922
 923         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV &&
 924             pll->flags & RADEON_PLL_USE_REF_DIV)
 925                 ref_div_max = pll->reference_div;
 926         else
 927                 ref_div_max = pll->max_ref_div;
 928
 929         /* determine allowed post divider range */
 930         if (pll->flags & RADEON_PLL_USE_POST_DIV) {
 931                 post_div_min = pll->post_div;
 932                 post_div_max = pll->post_div;
 933         } else {
 934                 unsigned vco_min, vco_max;
 935
 936                 if (pll->flags & RADEON_PLL_IS_LCD) {
 937                         vco_min = pll->lcd_pll_out_min;
 938                         vco_max = pll->lcd_pll_out_max;
 939                 } else {
 940                         vco_min = pll->pll_out_min;
 941                         vco_max = pll->pll_out_max;
 942                 }
 943
 944                 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
 945                         vco_min *= 10;
 946                         vco_max *= 10;
 947                 }
 948
 949                 post_div_min = vco_min / target_clock;
 950                 if ((target_clock * post_div_min) < vco_min)
 951                         ++post_div_min;
 952                 if (post_div_min < pll->min_post_div)
 953                         post_div_min = pll->min_post_div;
 954
 955                 post_div_max = vco_max / target_clock;
 956                 if ((target_clock * post_div_max) > vco_max)
 957                         --post_div_max;
 958                 if (post_div_max > pll->max_post_div)
 959                         post_div_max = pll->max_post_div;
 960         }
 961
 962         /* represent the searched ratio as fractional number */
 963         nom = target_clock;
 964         den = pll->reference_freq;
 965
 966         /* reduce the numbers to a simpler ratio */
 967         avivo_reduce_ratio(&nom, &den, fb_div_min, post_div_min);
 968
 969         /* now search for a post divider */
 970         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
 971                 post_div_best = post_div_min;
 972         else
 973                 post_div_best = post_div_max;
 974         diff_best = ~0;
 975
 976         for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
 977                 unsigned diff;
 978                 avivo_get_fb_ref_div(nom, den, post_div, fb_div_max,
 979                                      ref_div_max, &fb_div, &ref_div);
 980                 diff = abs(target_clock - (pll->reference_freq * fb_div) /
 981                         (ref_div * post_div));
 982
 983                 if (diff < diff_best || (diff == diff_best &&
 984                     !(pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP))) {
 985
 986                         post_div_best = post_div;
 987                         diff_best = diff;
 988                 }
 989         }
 990         post_div = post_div_best;
 991
 992         /* get the feedback and reference divider for the optimal value */
 993         avivo_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
 994                              &fb_div, &ref_div);
 995
 996         /* reduce the numbers to a simpler ratio once more */
 997         /* this also makes sure that the reference divider is large enough */
 998         avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min);
 999
1000         /* avoid high jitter with small fractional dividers */
1001         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) {
1002                 fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 50);
1003                 if (fb_div < fb_div_min) {
1004                         unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div);
1005                         fb_div *= tmp;
1006                         ref_div *= tmp;
1007                 }
1008         }
1009
1010         /* and finally save the result */
1011         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1012                 *fb_div_p = fb_div / 10;
1013                 *frac_fb_div_p = fb_div % 10;
1014         } else {
1015                 *fb_div_p = fb_div;
1016                 *frac_fb_div_p = 0;
1017         }
1018
1019         *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) +
1020                         (pll->reference_freq * *frac_fb_div_p)) /
1021                        (ref_div * post_div * 10);
1022         *ref_div_p = ref_div;
1023         *post_div_p = post_div;
1024
1025         DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1026                       freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p,
1027                       ref_div, post_div);
1028 }
1029
1030 /* pre-avivo */
1031 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
1032 {
1033         uint64_t mod;
1034
1035         n += d / 2;
1036
1037         mod = do_div(n, d);
1038         return n;
1039 }
1040
1041 void radeon_compute_pll_legacy(struct radeon_pll *pll,
1042                                uint64_t freq,
1043                                uint32_t *dot_clock_p,
1044                                uint32_t *fb_div_p,
1045                                uint32_t *frac_fb_div_p,
1046                                uint32_t *ref_div_p,
1047                                uint32_t *post_div_p)
1048 {
1049         uint32_t min_ref_div = pll->min_ref_div;
1050         uint32_t max_ref_div = pll->max_ref_div;
1051         uint32_t min_post_div = pll->min_post_div;
1052         uint32_t max_post_div = pll->max_post_div;
1053         uint32_t min_fractional_feed_div = 0;
1054         uint32_t max_fractional_feed_div = 0;
1055         uint32_t best_vco = pll->best_vco;
1056         uint32_t best_post_div = 1;
1057         uint32_t best_ref_div = 1;
1058         uint32_t best_feedback_div = 1;
1059         uint32_t best_frac_feedback_div = 0;
1060         uint32_t best_freq = -1;
1061         uint32_t best_error = 0xffffffff;
1062         uint32_t best_vco_diff = 1;
1063         uint32_t post_div;
1064         u32 pll_out_min, pll_out_max;
1065
1066         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
1067         freq = freq * 1000;
1068
1069         if (pll->flags & RADEON_PLL_IS_LCD) {
1070                 pll_out_min = pll->lcd_pll_out_min;
1071                 pll_out_max = pll->lcd_pll_out_max;
1072         } else {
1073                 pll_out_min = pll->pll_out_min;
1074                 pll_out_max = pll->pll_out_max;
1075         }
1076
1077         if (pll_out_min > 64800)
1078                 pll_out_min = 64800;
1079
1080         if (pll->flags & RADEON_PLL_USE_REF_DIV)
1081                 min_ref_div = max_ref_div = pll->reference_div;
1082         else {
1083                 while (min_ref_div < max_ref_div-1) {
1084                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
1085                         uint32_t pll_in = pll->reference_freq / mid;
1086                         if (pll_in < pll->pll_in_min)
1087                                 max_ref_div = mid;
1088                         else if (pll_in > pll->pll_in_max)
1089                                 min_ref_div = mid;
1090                         else
1091                                 break;
1092                 }
1093         }
1094
1095         if (pll->flags & RADEON_PLL_USE_POST_DIV)
1096                 min_post_div = max_post_div = pll->post_div;
1097
1098         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
1099                 min_fractional_feed_div = pll->min_frac_feedback_div;
1100                 max_fractional_feed_div = pll->max_frac_feedback_div;
1101         }
1102
1103         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
1104                 uint32_t ref_div;
1105
1106                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
1107                         continue;
1108
1109                 /* legacy radeons only have a few post_divs */
1110                 if (pll->flags & RADEON_PLL_LEGACY) {
1111                         if ((post_div == 5) ||
1112                             (post_div == 7) ||
1113                             (post_div == 9) ||
1114                             (post_div == 10) ||
1115                             (post_div == 11) ||
1116                             (post_div == 13) ||
1117                             (post_div == 14) ||
1118                             (post_div == 15))
1119                                 continue;
1120                 }
1121
1122                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
1123                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
1124                         uint32_t pll_in = pll->reference_freq / ref_div;
1125                         uint32_t min_feed_div = pll->min_feedback_div;
1126                         uint32_t max_feed_div = pll->max_feedback_div + 1;
1127
1128                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1129                                 continue;
1130
1131                         while (min_feed_div < max_feed_div) {
1132                                 uint32_t vco;
1133                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1134                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1135                                 uint32_t frac_feedback_div;
1136                                 uint64_t tmp;
1137
1138                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1139
1140                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1141                                 vco = radeon_div(tmp, ref_div);
1142
1143                                 if (vco < pll_out_min) {
1144                                         min_feed_div = feedback_div + 1;
1145                                         continue;
1146                                 } else if (vco > pll_out_max) {
1147                                         max_feed_div = feedback_div;
1148                                         continue;
1149                                 }
1150
1151                                 while (min_frac_feed_div < max_frac_feed_div) {
1152                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1153                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1154                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1155                                         current_freq = radeon_div(tmp, ref_div * post_div);
1156
1157                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1158                                                 if (freq < current_freq)
1159                                                         error = 0xffffffff;
1160                                                 else
1161                                                         error = freq - current_freq;
1162                                         } else
1163                                                 error = abs(current_freq - freq);
1164                                         vco_diff = abs(vco - best_vco);
1165
1166                                         if ((best_vco == 0 && error < best_error) ||
1167                                             (best_vco != 0 &&
1168                                              ((best_error > 100 && error < best_error - 100) ||
1169                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1170                                                 best_post_div = post_div;
1171                                                 best_ref_div = ref_div;
1172                                                 best_feedback_div = feedback_div;
1173                                                 best_frac_feedback_div = frac_feedback_div;
1174                                                 best_freq = current_freq;
1175                                                 best_error = error;
1176                                                 best_vco_diff = vco_diff;
1177                                         } else if (current_freq == freq) {
1178                                                 if (best_freq == -1) {
1179                                                         best_post_div = post_div;
1180                                                         best_ref_div = ref_div;
1181                                                         best_feedback_div = feedback_div;
1182                                                         best_frac_feedback_div = frac_feedback_div;
1183                                                         best_freq = current_freq;
1184                                                         best_error = error;
1185                                                         best_vco_diff = vco_diff;
1186                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1187                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1188                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1189                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1190                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1191                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1192                                                         best_post_div = post_div;
1193                                                         best_ref_div = ref_div;
1194                                                         best_feedback_div = feedback_div;
1195                                                         best_frac_feedback_div = frac_feedback_div;
1196                                                         best_freq = current_freq;
1197                                                         best_error = error;
1198                                                         best_vco_diff = vco_diff;
1199                                                 }
1200                                         }
1201                                         if (current_freq < freq)
1202                                                 min_frac_feed_div = frac_feedback_div + 1;
1203                                         else
1204                                                 max_frac_feed_div = frac_feedback_div;
1205                                 }
1206                                 if (current_freq < freq)
1207                                         min_feed_div = feedback_div + 1;
1208                                 else
1209                                         max_feed_div = feedback_div;
1210                         }
1211                 }
1212         }
1213
1214         *dot_clock_p = best_freq / 10000;
1215         *fb_div_p = best_feedback_div;
1216         *frac_fb_div_p = best_frac_feedback_div;
1217         *ref_div_p = best_ref_div;
1218         *post_div_p = best_post_div;
1219         DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1220                       (long long)freq,
1221                       best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1222                       best_ref_div, best_post_div);
1223
1224 }
1225
1226 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1227 {
1228         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1229
1230         if (radeon_fb->obj) {
1231                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1232         }
1233         drm_framebuffer_cleanup(fb);
1234         kfree(radeon_fb);
1235 }
1236
1237 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1238                                                   struct drm_file *file_priv,
1239                                                   unsigned int *handle)
1240 {
1241         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1242
1243         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1244 }
1245
1246 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1247         .destroy = radeon_user_framebuffer_destroy,
1248         .create_handle = radeon_user_framebuffer_create_handle,
1249 };
1250
1251 int
1252 radeon_framebuffer_init(struct drm_device *dev,
1253                         struct radeon_framebuffer *rfb,
1254                         struct drm_mode_fb_cmd2 *mode_cmd,
1255                         struct drm_gem_object *obj)
1256 {
1257         int ret;
1258         rfb->obj = obj;
1259         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1260         ret = drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1261         if (ret) {
1262                 rfb->obj = NULL;
1263                 return ret;
1264         }
1265         return 0;
1266 }
1267
1268 static struct drm_framebuffer *
1269 radeon_user_framebuffer_create(struct drm_device *dev,
1270                                struct drm_file *file_priv,
1271                                struct drm_mode_fb_cmd2 *mode_cmd)
1272 {
1273         struct drm_gem_object *obj;
1274         struct radeon_framebuffer *radeon_fb;
1275         int ret;
1276
1277         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]);
1278         if (obj ==  NULL) {
1279                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1280                         "can't create framebuffer\n", mode_cmd->handles[0]);
1281                 return ERR_PTR(-ENOENT);
1282         }
1283
1284         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1285         if (radeon_fb == NULL) {
1286                 drm_gem_object_unreference_unlocked(obj);
1287                 return ERR_PTR(-ENOMEM);
1288         }
1289
1290         ret = radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1291         if (ret) {
1292                 kfree(radeon_fb);
1293                 drm_gem_object_unreference_unlocked(obj);
1294                 return ERR_PTR(ret);
1295         }
1296
1297         return &radeon_fb->base;
1298 }
1299
1300 static void radeon_output_poll_changed(struct drm_device *dev)
1301 {
1302         struct radeon_device *rdev = dev->dev_private;
1303         radeon_fb_output_poll_changed(rdev);
1304 }
1305
1306 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1307         .fb_create = radeon_user_framebuffer_create,
1308         .output_poll_changed = radeon_output_poll_changed
1309 };
1310
1311 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1312 {       { 0, "driver" },
1313         { 1, "bios" },
1314 };
1315
1316 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1317 {       { TV_STD_NTSC, "ntsc" },
1318         { TV_STD_PAL, "pal" },
1319         { TV_STD_PAL_M, "pal-m" },
1320         { TV_STD_PAL_60, "pal-60" },
1321         { TV_STD_NTSC_J, "ntsc-j" },
1322         { TV_STD_SCART_PAL, "scart-pal" },
1323         { TV_STD_PAL_CN, "pal-cn" },
1324         { TV_STD_SECAM, "secam" },
1325 };
1326
1327 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1328 {       { UNDERSCAN_OFF, "off" },
1329         { UNDERSCAN_ON, "on" },
1330         { UNDERSCAN_AUTO, "auto" },
1331 };
1332
1333 static struct drm_prop_enum_list radeon_audio_enum_list[] =
1334 {       { RADEON_AUDIO_DISABLE, "off" },
1335         { RADEON_AUDIO_ENABLE, "on" },
1336         { RADEON_AUDIO_AUTO, "auto" },
1337 };
1338
1339 /* XXX support different dither options? spatial, temporal, both, etc. */
1340 static struct drm_prop_enum_list radeon_dither_enum_list[] =
1341 {       { RADEON_FMT_DITHER_DISABLE, "off" },
1342         { RADEON_FMT_DITHER_ENABLE, "on" },
1343 };
1344
1345 static int radeon_modeset_create_props(struct radeon_device *rdev)
1346 {
1347         int sz;
1348
1349         if (rdev->is_atom_bios) {
1350                 rdev->mode_info.coherent_mode_property =
1351                         drm_property_create_range(rdev->ddev, 0 , "coherent", 0, 1);
1352                 if (!rdev->mode_info.coherent_mode_property)
1353                         return -ENOMEM;
1354         }
1355
1356         if (!ASIC_IS_AVIVO(rdev)) {
1357                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1358                 rdev->mode_info.tmds_pll_property =
1359                         drm_property_create_enum(rdev->ddev, 0,
1360                                             "tmds_pll",
1361                                             radeon_tmds_pll_enum_list, sz);
1362         }
1363
1364         rdev->mode_info.load_detect_property =
1365                 drm_property_create_range(rdev->ddev, 0, "load detection", 0, 1);
1366         if (!rdev->mode_info.load_detect_property)
1367                 return -ENOMEM;
1368
1369         drm_mode_create_scaling_mode_property(rdev->ddev);
1370
1371         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1372         rdev->mode_info.tv_std_property =
1373                 drm_property_create_enum(rdev->ddev, 0,
1374                                     "tv standard",
1375                                     radeon_tv_std_enum_list, sz);
1376
1377         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1378         rdev->mode_info.underscan_property =
1379                 drm_property_create_enum(rdev->ddev, 0,
1380                                     "underscan",
1381                                     radeon_underscan_enum_list, sz);
1382
1383         rdev->mode_info.underscan_hborder_property =
1384                 drm_property_create_range(rdev->ddev, 0,
1385                                         "underscan hborder", 0, 128);
1386         if (!rdev->mode_info.underscan_hborder_property)
1387                 return -ENOMEM;
1388
1389         rdev->mode_info.underscan_vborder_property =
1390                 drm_property_create_range(rdev->ddev, 0,
1391                                         "underscan vborder", 0, 128);
1392         if (!rdev->mode_info.underscan_vborder_property)
1393                 return -ENOMEM;
1394
1395         sz = ARRAY_SIZE(radeon_audio_enum_list);
1396         rdev->mode_info.audio_property =
1397                 drm_property_create_enum(rdev->ddev, 0,
1398                                          "audio",
1399                                          radeon_audio_enum_list, sz);
1400
1401         sz = ARRAY_SIZE(radeon_dither_enum_list);
1402         rdev->mode_info.dither_property =
1403                 drm_property_create_enum(rdev->ddev, 0,
1404                                          "dither",
1405                                          radeon_dither_enum_list, sz);
1406
1407         return 0;
1408 }
1409
1410 void radeon_update_display_priority(struct radeon_device *rdev)
1411 {
1412         /* adjustment options for the display watermarks */
1413         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1414                 /* set display priority to high for r3xx, rv515 chips
1415                  * this avoids flickering due to underflow to the
1416                  * display controllers during heavy acceleration.
1417                  * Don't force high on rs4xx igp chips as it seems to
1418                  * affect the sound card.  See kernel bug 15982.
1419                  */
1420                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1421                     !(rdev->flags & RADEON_IS_IGP))
1422                         rdev->disp_priority = 2;
1423                 else
1424                         rdev->disp_priority = 0;
1425         } else
1426                 rdev->disp_priority = radeon_disp_priority;
1427
1428 }
1429
1430 /*
1431  * Allocate hdmi structs and determine register offsets
1432  */
1433 static void radeon_afmt_init(struct radeon_device *rdev)
1434 {
1435         int i;
1436
1437         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++)
1438                 rdev->mode_info.afmt[i] = NULL;
1439
1440         if (ASIC_IS_NODCE(rdev)) {
1441                 /* nothing to do */
1442         } else if (ASIC_IS_DCE4(rdev)) {
1443                 static uint32_t eg_offsets[] = {
1444                         EVERGREEN_CRTC0_REGISTER_OFFSET,
1445                         EVERGREEN_CRTC1_REGISTER_OFFSET,
1446                         EVERGREEN_CRTC2_REGISTER_OFFSET,
1447                         EVERGREEN_CRTC3_REGISTER_OFFSET,
1448                         EVERGREEN_CRTC4_REGISTER_OFFSET,
1449                         EVERGREEN_CRTC5_REGISTER_OFFSET,
1450                         0x13830 - 0x7030,
1451                 };
1452                 int num_afmt;
1453
1454                 /* DCE8 has 7 audio blocks tied to DIG encoders */
1455                 /* DCE6 has 6 audio blocks tied to DIG encoders */
1456                 /* DCE4/5 has 6 audio blocks tied to DIG encoders */
1457                 /* DCE4.1 has 2 audio blocks tied to DIG encoders */
1458                 if (ASIC_IS_DCE8(rdev))
1459                         num_afmt = 7;
1460                 else if (ASIC_IS_DCE6(rdev))
1461                         num_afmt = 6;
1462                 else if (ASIC_IS_DCE5(rdev))
1463                         num_afmt = 6;
1464                 else if (ASIC_IS_DCE41(rdev))
1465                         num_afmt = 2;
1466                 else /* DCE4 */
1467                         num_afmt = 6;
1468
1469                 BUG_ON(num_afmt > ARRAY_SIZE(eg_offsets));
1470                 for (i = 0; i < num_afmt; i++) {
1471                         rdev->mode_info.afmt[i] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1472                         if (rdev->mode_info.afmt[i]) {
1473                                 rdev->mode_info.afmt[i]->offset = eg_offsets[i];
1474                                 rdev->mode_info.afmt[i]->id = i;
1475                         }
1476                 }
1477         } else if (ASIC_IS_DCE3(rdev)) {
1478                 /* DCE3.x has 2 audio blocks tied to DIG encoders */
1479                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1480                 if (rdev->mode_info.afmt[0]) {
1481                         rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
1482                         rdev->mode_info.afmt[0]->id = 0;
1483                 }
1484                 rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1485                 if (rdev->mode_info.afmt[1]) {
1486                         rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
1487                         rdev->mode_info.afmt[1]->id = 1;
1488                 }
1489         } else if (ASIC_IS_DCE2(rdev)) {
1490                 /* DCE2 has at least 1 routable audio block */
1491                 rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1492                 if (rdev->mode_info.afmt[0]) {
1493                         rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
1494                         rdev->mode_info.afmt[0]->id = 0;
1495                 }
1496                 /* r6xx has 2 routable audio blocks */
1497                 if (rdev->family >= CHIP_R600) {
1498                         rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
1499                         if (rdev->mode_info.afmt[1]) {
1500                                 rdev->mode_info.afmt[1]->offset = DCE2_HDMI_OFFSET1;
1501                                 rdev->mode_info.afmt[1]->id = 1;
1502                         }
1503                 }
1504         }
1505 }
1506
1507 static void radeon_afmt_fini(struct radeon_device *rdev)
1508 {
1509         int i;
1510
1511         for (i = 0; i < RADEON_MAX_AFMT_BLOCKS; i++) {
1512                 kfree(rdev->mode_info.afmt[i]);
1513                 rdev->mode_info.afmt[i] = NULL;
1514         }
1515 }
1516
1517 int radeon_modeset_init(struct radeon_device *rdev)
1518 {
1519         int i;
1520         int ret;
1521
1522         drm_mode_config_init(rdev->ddev);
1523         rdev->mode_info.mode_config_initialized = true;
1524
1525         rdev->ddev->mode_config.funcs = &radeon_mode_funcs;
1526
1527         if (ASIC_IS_DCE5(rdev)) {
1528                 rdev->ddev->mode_config.max_width = 16384;
1529                 rdev->ddev->mode_config.max_height = 16384;
1530         } else if (ASIC_IS_AVIVO(rdev)) {
1531                 rdev->ddev->mode_config.max_width = 8192;
1532                 rdev->ddev->mode_config.max_height = 8192;
1533         } else {
1534                 rdev->ddev->mode_config.max_width = 4096;
1535                 rdev->ddev->mode_config.max_height = 4096;
1536         }
1537
1538         rdev->ddev->mode_config.preferred_depth = 24;
1539         rdev->ddev->mode_config.prefer_shadow = 1;
1540
1541         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1542
1543         ret = radeon_modeset_create_props(rdev);
1544         if (ret) {
1545                 return ret;
1546         }
1547
1548         /* init i2c buses */
1549         radeon_i2c_init(rdev);
1550
1551         /* check combios for a valid hardcoded EDID - Sun servers */
1552         if (!rdev->is_atom_bios) {
1553                 /* check for hardcoded EDID in BIOS */
1554                 radeon_combios_check_hardcoded_edid(rdev);
1555         }
1556
1557         /* allocate crtcs */
1558         for (i = 0; i < rdev->num_crtc; i++) {
1559                 radeon_crtc_init(rdev->ddev, i);
1560         }
1561
1562         /* okay we should have all the bios connectors */
1563         ret = radeon_setup_enc_conn(rdev->ddev);
1564         if (!ret) {
1565                 return ret;
1566         }
1567
1568         /* init dig PHYs, disp eng pll */
1569         if (rdev->is_atom_bios) {
1570                 radeon_atom_encoder_init(rdev);
1571                 radeon_atom_disp_eng_pll_init(rdev);
1572         }
1573
1574         /* initialize hpd */
1575         radeon_hpd_init(rdev);
1576
1577         /* setup afmt */
1578         radeon_afmt_init(rdev);
1579
1580         radeon_fbdev_init(rdev);
1581         drm_kms_helper_poll_init(rdev->ddev);
1582
1583         if (rdev->pm.dpm_enabled) {
1584                 /* do dpm late init */
1585                 ret = radeon_pm_late_init(rdev);
1586                 if (ret) {
1587                         rdev->pm.dpm_enabled = false;
1588                         DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1589                 }
1590                 /* set the dpm state for PX since there won't be
1591                  * a modeset to call this.
1592                  */
1593                 radeon_pm_compute_clocks(rdev);
1594         }
1595
1596         return 0;
1597 }
1598
1599 void radeon_modeset_fini(struct radeon_device *rdev)
1600 {
1601         radeon_fbdev_fini(rdev);
1602         kfree(rdev->mode_info.bios_hardcoded_edid);
1603
1604         if (rdev->mode_info.mode_config_initialized) {
1605                 radeon_afmt_fini(rdev);
1606                 drm_kms_helper_poll_fini(rdev->ddev);
1607                 radeon_hpd_fini(rdev);
1608                 drm_mode_config_cleanup(rdev->ddev);
1609                 rdev->mode_info.mode_config_initialized = false;
1610         }
1611         /* free i2c buses */
1612         radeon_i2c_fini(rdev);
1613 }
1614
1615 static bool is_hdtv_mode(const struct drm_display_mode *mode)
1616 {
1617         /* try and guess if this is a tv or a monitor */
1618         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1619             (mode->vdisplay == 576) || /* 576p */
1620             (mode->vdisplay == 720) || /* 720p */
1621             (mode->vdisplay == 1080)) /* 1080p */
1622                 return true;
1623         else
1624                 return false;
1625 }
1626
1627 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1628                                 const struct drm_display_mode *mode,
1629                                 struct drm_display_mode *adjusted_mode)
1630 {
1631         struct drm_device *dev = crtc->dev;
1632         struct radeon_device *rdev = dev->dev_private;
1633         struct drm_encoder *encoder;
1634         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1635         struct radeon_encoder *radeon_encoder;
1636         struct drm_connector *connector;
1637         struct radeon_connector *radeon_connector;
1638         bool first = true;
1639         u32 src_v = 1, dst_v = 1;
1640         u32 src_h = 1, dst_h = 1;
1641
1642         radeon_crtc->h_border = 0;
1643         radeon_crtc->v_border = 0;
1644
1645         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1646                 if (encoder->crtc != crtc)
1647                         continue;
1648                 radeon_encoder = to_radeon_encoder(encoder);
1649                 connector = radeon_get_connector_for_encoder(encoder);
1650                 radeon_connector = to_radeon_connector(connector);
1651
1652                 if (first) {
1653                         /* set scaling */
1654                         if (radeon_encoder->rmx_type == RMX_OFF)
1655                                 radeon_crtc->rmx_type = RMX_OFF;
1656                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1657                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1658                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1659                         else
1660                                 radeon_crtc->rmx_type = RMX_OFF;
1661                         /* copy native mode */
1662                         memcpy(&radeon_crtc->native_mode,
1663                                &radeon_encoder->native_mode,
1664                                 sizeof(struct drm_display_mode));
1665                         src_v = crtc->mode.vdisplay;
1666                         dst_v = radeon_crtc->native_mode.vdisplay;
1667                         src_h = crtc->mode.hdisplay;
1668                         dst_h = radeon_crtc->native_mode.hdisplay;
1669
1670                         /* fix up for overscan on hdmi */
1671                         if (ASIC_IS_AVIVO(rdev) &&
1672                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1673                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1674                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1675                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1676                               is_hdtv_mode(mode)))) {
1677                                 if (radeon_encoder->underscan_hborder != 0)
1678                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1679                                 else
1680                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1681                                 if (radeon_encoder->underscan_vborder != 0)
1682                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1683                                 else
1684                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1685                                 radeon_crtc->rmx_type = RMX_FULL;
1686                                 src_v = crtc->mode.vdisplay;
1687                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1688                                 src_h = crtc->mode.hdisplay;
1689                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1690                         }
1691                         first = false;
1692                 } else {
1693                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1694                                 /* WARNING: Right now this can't happen but
1695                                  * in the future we need to check that scaling
1696                                  * are consistent across different encoder
1697                                  * (ie all encoder can work with the same
1698                                  *  scaling).
1699                                  */
1700                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1701                                 return false;
1702                         }
1703                 }
1704         }
1705         if (radeon_crtc->rmx_type != RMX_OFF) {
1706                 fixed20_12 a, b;
1707                 a.full = dfixed_const(src_v);
1708                 b.full = dfixed_const(dst_v);
1709                 radeon_crtc->vsc.full = dfixed_div(a, b);
1710                 a.full = dfixed_const(src_h);
1711                 b.full = dfixed_const(dst_h);
1712                 radeon_crtc->hsc.full = dfixed_div(a, b);
1713         } else {
1714                 radeon_crtc->vsc.full = dfixed_const(1);
1715                 radeon_crtc->hsc.full = dfixed_const(1);
1716         }
1717         return true;
1718 }
1719
1720 /*
1721  * Retrieve current video scanout position of crtc on a given gpu, and
1722  * an optional accurate timestamp of when query happened.
1723  *
1724  * \param dev Device to query.
1725  * \param crtc Crtc to query.
1726  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
1727  * \param *vpos Location where vertical scanout position should be stored.
1728  * \param *hpos Location where horizontal scanout position should go.
1729  * \param *stime Target location for timestamp taken immediately before
1730  *               scanout position query. Can be NULL to skip timestamp.
1731  * \param *etime Target location for timestamp taken immediately after
1732  *               scanout position query. Can be NULL to skip timestamp.
1733  *
1734  * Returns vpos as a positive number while in active scanout area.
1735  * Returns vpos as a negative number inside vblank, counting the number
1736  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1737  * until start of active scanout / end of vblank."
1738  *
1739  * \return Flags, or'ed together as follows:
1740  *
1741  * DRM_SCANOUTPOS_VALID = Query successful.
1742  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1743  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1744  * this flag means that returned position may be offset by a constant but
1745  * unknown small number of scanlines wrt. real scanout position.
1746  *
1747  */
1748 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
1749                                int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
1750 {
1751         u32 stat_crtc = 0, vbl = 0, position = 0;
1752         int vbl_start, vbl_end, vtotal, ret = 0;
1753         bool in_vbl = true;
1754
1755         struct radeon_device *rdev = dev->dev_private;
1756
1757         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
1758
1759         /* Get optional system timestamp before query. */
1760         if (stime)
1761                 *stime = ktime_get();
1762
1763         if (ASIC_IS_DCE4(rdev)) {
1764                 if (crtc == 0) {
1765                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1766                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1767                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1768                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1769                         ret |= DRM_SCANOUTPOS_VALID;
1770                 }
1771                 if (crtc == 1) {
1772                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1773                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1774                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1775                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1776                         ret |= DRM_SCANOUTPOS_VALID;
1777                 }
1778                 if (crtc == 2) {
1779                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1780                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1781                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1782                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1783                         ret |= DRM_SCANOUTPOS_VALID;
1784                 }
1785                 if (crtc == 3) {
1786                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1787                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1788                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1789                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1790                         ret |= DRM_SCANOUTPOS_VALID;
1791                 }
1792                 if (crtc == 4) {
1793                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1794                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1795                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1796                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1797                         ret |= DRM_SCANOUTPOS_VALID;
1798                 }
1799                 if (crtc == 5) {
1800                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1801                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1802                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1803                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1804                         ret |= DRM_SCANOUTPOS_VALID;
1805                 }
1806         } else if (ASIC_IS_AVIVO(rdev)) {
1807                 if (crtc == 0) {
1808                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1809                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1810                         ret |= DRM_SCANOUTPOS_VALID;
1811                 }
1812                 if (crtc == 1) {
1813                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1814                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1815                         ret |= DRM_SCANOUTPOS_VALID;
1816                 }
1817         } else {
1818                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1819                 if (crtc == 0) {
1820                         /* Assume vbl_end == 0, get vbl_start from
1821                          * upper 16 bits.
1822                          */
1823                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1824                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1825                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1826                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1827                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1828                         if (!(stat_crtc & 1))
1829                                 in_vbl = false;
1830
1831                         ret |= DRM_SCANOUTPOS_VALID;
1832                 }
1833                 if (crtc == 1) {
1834                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1835                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1836                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1837                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1838                         if (!(stat_crtc & 1))
1839                                 in_vbl = false;
1840
1841                         ret |= DRM_SCANOUTPOS_VALID;
1842                 }
1843         }
1844
1845         /* Get optional system timestamp after query. */
1846         if (etime)
1847                 *etime = ktime_get();
1848
1849         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1850
1851         /* Decode into vertical and horizontal scanout position. */
1852         *vpos = position & 0x1fff;
1853         *hpos = (position >> 16) & 0x1fff;
1854
1855         /* Valid vblank area boundaries from gpu retrieved? */
1856         if (vbl > 0) {
1857                 /* Yes: Decode. */
1858                 ret |= DRM_SCANOUTPOS_ACCURATE;
1859                 vbl_start = vbl & 0x1fff;
1860                 vbl_end = (vbl >> 16) & 0x1fff;
1861         }
1862         else {
1863                 /* No: Fake something reasonable which gives at least ok results. */
1864                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1865                 vbl_end = 0;
1866         }
1867
1868         /* Test scanout position against vblank region. */
1869         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1870                 in_vbl = false;
1871
1872         /* Check if inside vblank area and apply corrective offsets:
1873          * vpos will then be >=0 in video scanout area, but negative
1874          * within vblank area, counting down the number of lines until
1875          * start of scanout.
1876          */
1877
1878         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1879         if (in_vbl && (*vpos >= vbl_start)) {
1880                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1881                 *vpos = *vpos - vtotal;
1882         }
1883
1884         /* Correct for shifted end of vbl at vbl_end. */
1885         *vpos = *vpos - vbl_end;
1886
1887         /* In vblank? */
1888         if (in_vbl)
1889                 ret |= DRM_SCANOUTPOS_INVBL;
1890
1891         /* Is vpos outside nominal vblank area, but less than
1892          * 1/100 of a frame height away from start of vblank?
1893          * If so, assume this isn't a massively delayed vblank
1894          * interrupt, but a vblank interrupt that fired a few
1895          * microseconds before true start of vblank. Compensate
1896          * by adding a full frame duration to the final timestamp.
1897          * Happens, e.g., on ATI R500, R600.
1898          *
1899          * We only do this if DRM_CALLED_FROM_VBLIRQ.
1900          */
1901         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
1902                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1903                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1904
1905                 if (vbl_start - *vpos < vtotal / 100) {
1906                         *vpos -= vtotal;
1907
1908                         /* Signal this correction as "applied". */
1909                         ret |= 0x8;
1910                 }
1911         }
1912
1913         return ret;
1914 }