2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
32 #include <linux/list.h>
33 #include <linux/slab.h>
35 #include "radeon_drm.h"
37 #include "radeon_trace.h"
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
53 bo = container_of(tbo, struct radeon_bo, tbo);
54 mutex_lock(&bo->rdev->gem.mutex);
55 list_del_init(&bo->list);
56 mutex_unlock(&bo->rdev->gem.mutex);
57 radeon_bo_clear_surface_reg(bo);
58 drm_gem_object_release(&bo->gem_base);
62 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
64 if (bo->destroy == &radeon_ttm_bo_destroy)
69 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
73 rbo->placement.fpfn = 0;
74 rbo->placement.lpfn = 0;
75 rbo->placement.placement = rbo->placements;
76 rbo->placement.busy_placement = rbo->placements;
77 if (domain & RADEON_GEM_DOMAIN_VRAM)
78 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
80 if (domain & RADEON_GEM_DOMAIN_GTT)
81 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
82 if (domain & RADEON_GEM_DOMAIN_CPU)
83 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
85 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
86 rbo->placement.num_placement = c;
87 rbo->placement.num_busy_placement = c;
90 int radeon_bo_create(struct radeon_device *rdev,
91 unsigned long size, int byte_align, bool kernel, u32 domain,
92 struct radeon_bo **bo_ptr)
95 enum ttm_bo_type type;
96 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
97 unsigned long max_size = 0;
100 size = ALIGN(size, PAGE_SIZE);
102 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
103 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
106 type = ttm_bo_type_kernel;
108 type = ttm_bo_type_device;
112 /* maximun bo size is the minimun btw visible vram and gtt size */
113 max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
114 if ((page_align << PAGE_SHIFT) >= max_size) {
115 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
116 __func__, __LINE__, page_align >> (20 - PAGE_SHIFT), max_size >> 20);
121 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
124 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
130 bo->gobj = &bo->gem_base;
131 bo->gem_base.driver_private = NULL;
132 bo->surface_reg = -1;
133 INIT_LIST_HEAD(&bo->list);
134 radeon_ttm_placement_from_domain(bo, domain);
135 /* Kernel allocation are uninterruptible */
136 mutex_lock(&rdev->vram_mutex);
137 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
138 &bo->placement, page_align, 0, !kernel, NULL, size,
139 &radeon_ttm_bo_destroy);
140 mutex_unlock(&rdev->vram_mutex);
141 if (unlikely(r != 0)) {
142 if (r != -ERESTARTSYS) {
143 if (domain == RADEON_GEM_DOMAIN_VRAM) {
144 domain |= RADEON_GEM_DOMAIN_GTT;
148 "object_init failed for (%lu, 0x%08X)\n",
155 trace_radeon_bo_create(bo);
160 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
171 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
175 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
179 radeon_bo_check_tiling(bo, 0, 0);
183 void radeon_bo_kunmap(struct radeon_bo *bo)
185 if (bo->kptr == NULL)
188 radeon_bo_check_tiling(bo, 0, 0);
189 ttm_bo_kunmap(&bo->kmap);
192 void radeon_bo_unref(struct radeon_bo **bo)
194 struct ttm_buffer_object *tbo;
195 struct radeon_device *rdev;
201 mutex_lock(&rdev->vram_mutex);
203 mutex_unlock(&rdev->vram_mutex);
208 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
215 *gpu_addr = radeon_bo_gpu_offset(bo);
218 radeon_ttm_placement_from_domain(bo, domain);
219 if (domain == RADEON_GEM_DOMAIN_VRAM) {
220 /* force to pin into visible video ram */
221 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
223 for (i = 0; i < bo->placement.num_placement; i++)
224 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
225 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
226 if (likely(r == 0)) {
228 if (gpu_addr != NULL)
229 *gpu_addr = radeon_bo_gpu_offset(bo);
231 if (unlikely(r != 0))
232 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
236 int radeon_bo_unpin(struct radeon_bo *bo)
240 if (!bo->pin_count) {
241 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
247 for (i = 0; i < bo->placement.num_placement; i++)
248 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
249 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
250 if (unlikely(r != 0))
251 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
255 int radeon_bo_evict_vram(struct radeon_device *rdev)
257 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
258 if (0 && (rdev->flags & RADEON_IS_IGP)) {
259 if (rdev->mc.igp_sideport_enabled == false)
260 /* Useless to evict on IGP chips */
263 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
266 void radeon_bo_force_delete(struct radeon_device *rdev)
268 struct radeon_bo *bo, *n;
269 struct drm_gem_object *gobj;
271 if (list_empty(&rdev->gem.objects)) {
274 dev_err(rdev->dev, "Userspace still has active objects !\n");
275 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
276 mutex_lock(&rdev->ddev->struct_mutex);
278 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
279 gobj, bo, (unsigned long)gobj->size,
280 *((unsigned long *)&gobj->refcount));
281 mutex_lock(&bo->rdev->gem.mutex);
282 list_del_init(&bo->list);
283 mutex_unlock(&bo->rdev->gem.mutex);
284 radeon_bo_unref(&bo);
285 drm_gem_object_unreference(gobj);
286 mutex_unlock(&rdev->ddev->struct_mutex);
290 int radeon_bo_init(struct radeon_device *rdev)
292 /* Add an MTRR for the VRAM */
293 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
294 MTRR_TYPE_WRCOMB, 1);
295 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
296 rdev->mc.mc_vram_size >> 20,
297 (unsigned long long)rdev->mc.aper_size >> 20);
298 DRM_INFO("RAM width %dbits %cDR\n",
299 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
300 return radeon_ttm_init(rdev);
303 void radeon_bo_fini(struct radeon_device *rdev)
305 radeon_ttm_fini(rdev);
308 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
309 struct list_head *head)
312 list_add(&lobj->tv.head, head);
314 list_add_tail(&lobj->tv.head, head);
318 int radeon_bo_list_validate(struct list_head *head)
320 struct radeon_bo_list *lobj;
321 struct radeon_bo *bo;
325 r = ttm_eu_reserve_buffers(head);
326 if (unlikely(r != 0)) {
329 list_for_each_entry(lobj, head, tv.head) {
331 if (!bo->pin_count) {
332 domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
335 radeon_ttm_placement_from_domain(bo, domain);
336 r = ttm_bo_validate(&bo->tbo, &bo->placement,
339 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
340 domain |= RADEON_GEM_DOMAIN_GTT;
346 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
347 lobj->tiling_flags = bo->tiling_flags;
352 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
353 struct vm_area_struct *vma)
355 return ttm_fbdev_mmap(vma, &bo->tbo);
358 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
360 struct radeon_device *rdev = bo->rdev;
361 struct radeon_surface_reg *reg;
362 struct radeon_bo *old_object;
366 BUG_ON(!atomic_read(&bo->tbo.reserved));
368 if (!bo->tiling_flags)
371 if (bo->surface_reg >= 0) {
372 reg = &rdev->surface_regs[bo->surface_reg];
378 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
380 reg = &rdev->surface_regs[i];
384 old_object = reg->bo;
385 if (old_object->pin_count == 0)
389 /* if we are all out */
390 if (i == RADEON_GEM_MAX_SURFACES) {
393 /* find someone with a surface reg and nuke their BO */
394 reg = &rdev->surface_regs[steal];
395 old_object = reg->bo;
396 /* blow away the mapping */
397 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
398 ttm_bo_unmap_virtual(&old_object->tbo);
399 old_object->surface_reg = -1;
407 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
408 bo->tbo.mem.start << PAGE_SHIFT,
409 bo->tbo.num_pages << PAGE_SHIFT);
413 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
415 struct radeon_device *rdev = bo->rdev;
416 struct radeon_surface_reg *reg;
418 if (bo->surface_reg == -1)
421 reg = &rdev->surface_regs[bo->surface_reg];
422 radeon_clear_surface_reg(rdev, bo->surface_reg);
425 bo->surface_reg = -1;
428 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
429 uint32_t tiling_flags, uint32_t pitch)
433 r = radeon_bo_reserve(bo, false);
434 if (unlikely(r != 0))
436 bo->tiling_flags = tiling_flags;
438 radeon_bo_unreserve(bo);
442 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
443 uint32_t *tiling_flags,
446 BUG_ON(!atomic_read(&bo->tbo.reserved));
448 *tiling_flags = bo->tiling_flags;
453 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
456 BUG_ON(!atomic_read(&bo->tbo.reserved));
458 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
462 radeon_bo_clear_surface_reg(bo);
466 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
470 if (bo->surface_reg >= 0)
471 radeon_bo_clear_surface_reg(bo);
475 if ((bo->surface_reg >= 0) && !has_moved)
478 return radeon_bo_get_surface_reg(bo);
481 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
482 struct ttm_mem_reg *mem)
484 struct radeon_bo *rbo;
485 if (!radeon_ttm_bo_is_radeon_bo(bo))
487 rbo = container_of(bo, struct radeon_bo, tbo);
488 radeon_bo_check_tiling(rbo, 0, 1);
491 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
493 struct radeon_device *rdev;
494 struct radeon_bo *rbo;
495 unsigned long offset, size;
498 if (!radeon_ttm_bo_is_radeon_bo(bo))
500 rbo = container_of(bo, struct radeon_bo, tbo);
501 radeon_bo_check_tiling(rbo, 0, 0);
503 if (bo->mem.mem_type == TTM_PL_VRAM) {
504 size = bo->mem.num_pages << PAGE_SHIFT;
505 offset = bo->mem.start << PAGE_SHIFT;
506 if ((offset + size) > rdev->mc.visible_vram_size) {
507 /* hurrah the memory is not visible ! */
508 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
509 rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
510 r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
511 if (unlikely(r != 0))
513 offset = bo->mem.start << PAGE_SHIFT;
514 /* this should not happen */
515 if ((offset + size) > rdev->mc.visible_vram_size)