drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include "r600_dpm.h"
  28 #include <linux/power_supply.h>
  29 #include <linux/hwmon.h>
  30 #include <linux/hwmon-sysfs.h>
  31
  32 #define RADEON_IDLE_LOOP_MS 100
  33 #define RADEON_RECLOCK_DELAY_MS 200
  34 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  35
  36 static const char *radeon_pm_state_type_name[5] = {
  37         "",
  38         "Powersave",
  39         "Battery",
  40         "Balanced",
  41         "Performance",
  42 };
  43
  44 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  45 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  46 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  48 static void radeon_pm_update_profile(struct radeon_device *rdev);
  49 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  50
  51 int radeon_pm_get_type_index(struct radeon_device *rdev,
  52                              enum radeon_pm_state_type ps_type,
  53                              int instance)
  54 {
  55         int i;
  56         int found_instance = -1;
  57
  58         for (i = 0; i < rdev->pm.num_power_states; i++) {
  59                 if (rdev->pm.power_state[i].type == ps_type) {
  60                         found_instance++;
  61                         if (found_instance == instance)
  62                                 return i;
  63                 }
  64         }
  65         /* return default if no match */
  66         return rdev->pm.default_power_state_index;
  67 }
  68
  69 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  70 {
  71         if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
  72                 mutex_lock(&rdev->pm.mutex);
  73                 if (power_supply_is_system_supplied() > 0)
  74                         rdev->pm.dpm.ac_power = true;
  75                 else
  76                         rdev->pm.dpm.ac_power = false;
  77                 if (rdev->family == CHIP_ARUBA) {
  78                         if (rdev->asic->dpm.enable_bapm)
  79                                 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
  80                 }
  81                 mutex_unlock(&rdev->pm.mutex);
  82         } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  83                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  84                         mutex_lock(&rdev->pm.mutex);
  85                         radeon_pm_update_profile(rdev);
  86                         radeon_pm_set_clocks(rdev);
  87                         mutex_unlock(&rdev->pm.mutex);
  88                 }
  89         }
  90 }
  91
  92 static void radeon_pm_update_profile(struct radeon_device *rdev)
  93 {
  94         switch (rdev->pm.profile) {
  95         case PM_PROFILE_DEFAULT:
  96                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  97                 break;
  98         case PM_PROFILE_AUTO:
  99                 if (power_supply_is_system_supplied() > 0) {
 100                         if (rdev->pm.active_crtc_count > 1)
 101                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 102                         else
 103                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 104                 } else {
 105                         if (rdev->pm.active_crtc_count > 1)
 106                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 107                         else
 108                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 109                 }
 110                 break;
 111         case PM_PROFILE_LOW:
 112                 if (rdev->pm.active_crtc_count > 1)
 113                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 114                 else
 115                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 116                 break;
 117         case PM_PROFILE_MID:
 118                 if (rdev->pm.active_crtc_count > 1)
 119                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 120                 else
 121                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 122                 break;
 123         case PM_PROFILE_HIGH:
 124                 if (rdev->pm.active_crtc_count > 1)
 125                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 126                 else
 127                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 128                 break;
 129         }
 130
 131         if (rdev->pm.active_crtc_count == 0) {
 132                 rdev->pm.requested_power_state_index =
 133                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 134                 rdev->pm.requested_clock_mode_index =
 135                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 136         } else {
 137                 rdev->pm.requested_power_state_index =
 138                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 139                 rdev->pm.requested_clock_mode_index =
 140                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 141         }
 142 }
 143
 144 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 145 {
 146         struct radeon_bo *bo, *n;
 147
 148         if (list_empty(&rdev->gem.objects))
 149                 return;
 150
 151         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 152                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 153                         ttm_bo_unmap_virtual(&bo->tbo);
 154         }
 155 }
 156
 157 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 158 {
 159         if (rdev->pm.active_crtcs) {
 160                 rdev->pm.vblank_sync = false;
 161                 wait_event_timeout(
 162                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 163                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 164         }
 165 }
 166
 167 static void radeon_set_power_state(struct radeon_device *rdev)
 168 {
 169         u32 sclk, mclk;
 170         bool misc_after = false;
 171
 172         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 173             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 174                 return;
 175
 176         if (radeon_gui_idle(rdev)) {
 177                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 178                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 179                 if (sclk > rdev->pm.default_sclk)
 180                         sclk = rdev->pm.default_sclk;
 181
 182                 /* starting with BTC, there is one state that is used for both
 183                  * MH and SH.  Difference is that we always use the high clock index for
 184                  * mclk and vddci.
 185                  */
 186                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 187                     (rdev->family >= CHIP_BARTS) &&
 188                     rdev->pm.active_crtc_count &&
 189                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 190                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 191                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 192                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 193                 else
 194                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 195                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 196
 197                 if (mclk > rdev->pm.default_mclk)
 198                         mclk = rdev->pm.default_mclk;
 199
 200                 /* upvolt before raising clocks, downvolt after lowering clocks */
 201                 if (sclk < rdev->pm.current_sclk)
 202                         misc_after = true;
 203
 204                 radeon_sync_with_vblank(rdev);
 205
 206                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 207                         if (!radeon_pm_in_vbl(rdev))
 208                                 return;
 209                 }
 210
 211                 radeon_pm_prepare(rdev);
 212
 213                 if (!misc_after)
 214                         /* voltage, pcie lanes, etc.*/
 215                         radeon_pm_misc(rdev);
 216
 217                 /* set engine clock */
 218                 if (sclk != rdev->pm.current_sclk) {
 219                         radeon_pm_debug_check_in_vbl(rdev, false);
 220                         radeon_set_engine_clock(rdev, sclk);
 221                         radeon_pm_debug_check_in_vbl(rdev, true);
 222                         rdev->pm.current_sclk = sclk;
 223                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 224                 }
 225
 226                 /* set memory clock */
 227                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 228                         radeon_pm_debug_check_in_vbl(rdev, false);
 229                         radeon_set_memory_clock(rdev, mclk);
 230                         radeon_pm_debug_check_in_vbl(rdev, true);
 231                         rdev->pm.current_mclk = mclk;
 232                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 233                 }
 234
 235                 if (misc_after)
 236                         /* voltage, pcie lanes, etc.*/
 237                         radeon_pm_misc(rdev);
 238
 239                 radeon_pm_finish(rdev);
 240
 241                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 242                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 243         } else
 244                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 245 }
 246
 247 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 248 {
 249         int i, r;
 250
 251         /* no need to take locks, etc. if nothing's going to change */
 252         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 253             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 254                 return;
 255
 256         mutex_lock(&rdev->ddev->struct_mutex);
 257         down_write(&rdev->pm.mclk_lock);
 258         mutex_lock(&rdev->ring_lock);
 259
 260         /* wait for the rings to drain */
 261         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 262                 struct radeon_ring *ring = &rdev->ring[i];
 263                 if (!ring->ready) {
 264                         continue;
 265                 }
 266                 r = radeon_fence_wait_empty(rdev, i);
 267                 if (r) {
 268                         /* needs a GPU reset dont reset here */
 269                         mutex_unlock(&rdev->ring_lock);
 270                         up_write(&rdev->pm.mclk_lock);
 271                         mutex_unlock(&rdev->ddev->struct_mutex);
 272                         return;
 273                 }
 274         }
 275
 276         radeon_unmap_vram_bos(rdev);
 277
 278         if (rdev->irq.installed) {
 279                 for (i = 0; i < rdev->num_crtc; i++) {
 280                         if (rdev->pm.active_crtcs & (1 << i)) {
 281                                 rdev->pm.req_vblank |= (1 << i);
 282                                 drm_vblank_get(rdev->ddev, i);
 283                         }
 284                 }
 285         }
 286
 287         radeon_set_power_state(rdev);
 288
 289         if (rdev->irq.installed) {
 290                 for (i = 0; i < rdev->num_crtc; i++) {
 291                         if (rdev->pm.req_vblank & (1 << i)) {
 292                                 rdev->pm.req_vblank &= ~(1 << i);
 293                                 drm_vblank_put(rdev->ddev, i);
 294                         }
 295                 }
 296         }
 297
 298         /* update display watermarks based on new power state */
 299         radeon_update_bandwidth_info(rdev);
 300         if (rdev->pm.active_crtc_count)
 301                 radeon_bandwidth_update(rdev);
 302
 303         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 304
 305         mutex_unlock(&rdev->ring_lock);
 306         up_write(&rdev->pm.mclk_lock);
 307         mutex_unlock(&rdev->ddev->struct_mutex);
 308 }
 309
 310 static void radeon_pm_print_states(struct radeon_device *rdev)
 311 {
 312         int i, j;
 313         struct radeon_power_state *power_state;
 314         struct radeon_pm_clock_info *clock_info;
 315
 316         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 317         for (i = 0; i < rdev->pm.num_power_states; i++) {
 318                 power_state = &rdev->pm.power_state[i];
 319                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 320                         radeon_pm_state_type_name[power_state->type]);
 321                 if (i == rdev->pm.default_power_state_index)
 322                         DRM_DEBUG_DRIVER("\tDefault");
 323                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 324                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 325                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 326                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 327                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 328                 for (j = 0; j < power_state->num_clock_modes; j++) {
 329                         clock_info = &(power_state->clock_info[j]);
 330                         if (rdev->flags & RADEON_IS_IGP)
 331                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 332                                                  j,
 333                                                  clock_info->sclk * 10);
 334                         else
 335                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 336                                                  j,
 337                                                  clock_info->sclk * 10,
 338                                                  clock_info->mclk * 10,
 339                                                  clock_info->voltage.voltage);
 340                 }
 341         }
 342 }
 343
 344 static ssize_t radeon_get_pm_profile(struct device *dev,
 345                                      struct device_attribute *attr,
 346                                      char *buf)
 347 {
 348         struct drm_device *ddev = dev_get_drvdata(dev);
 349         struct radeon_device *rdev = ddev->dev_private;
 350         int cp = rdev->pm.profile;
 351
 352         return snprintf(buf, PAGE_SIZE, "%s\n",
 353                         (cp == PM_PROFILE_AUTO) ? "auto" :
 354                         (cp == PM_PROFILE_LOW) ? "low" :
 355                         (cp == PM_PROFILE_MID) ? "mid" :
 356                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 357 }
 358
 359 static ssize_t radeon_set_pm_profile(struct device *dev,
 360                                      struct device_attribute *attr,
 361                                      const char *buf,
 362                                      size_t count)
 363 {
 364         struct drm_device *ddev = dev_get_drvdata(dev);
 365         struct radeon_device *rdev = ddev->dev_private;
 366
 367         /* Can't set profile when the card is off */
 368         if  ((rdev->flags & RADEON_IS_PX) &&
 369              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 370                 return -EINVAL;
 371
 372         mutex_lock(&rdev->pm.mutex);
 373         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 374                 if (strncmp("default", buf, strlen("default")) == 0)
 375                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 376                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 377                         rdev->pm.profile = PM_PROFILE_AUTO;
 378                 else if (strncmp("low", buf, strlen("low")) == 0)
 379                         rdev->pm.profile = PM_PROFILE_LOW;
 380                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 381                         rdev->pm.profile = PM_PROFILE_MID;
 382                 else if (strncmp("high", buf, strlen("high")) == 0)
 383                         rdev->pm.profile = PM_PROFILE_HIGH;
 384                 else {
 385                         count = -EINVAL;
 386                         goto fail;
 387                 }
 388                 radeon_pm_update_profile(rdev);
 389                 radeon_pm_set_clocks(rdev);
 390         } else
 391                 count = -EINVAL;
 392
 393 fail:
 394         mutex_unlock(&rdev->pm.mutex);
 395
 396         return count;
 397 }
 398
 399 static ssize_t radeon_get_pm_method(struct device *dev,
 400                                     struct device_attribute *attr,
 401                                     char *buf)
 402 {
 403         struct drm_device *ddev = dev_get_drvdata(dev);
 404         struct radeon_device *rdev = ddev->dev_private;
 405         int pm = rdev->pm.pm_method;
 406
 407         return snprintf(buf, PAGE_SIZE, "%s\n",
 408                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 409                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 410 }
 411
 412 static ssize_t radeon_set_pm_method(struct device *dev,
 413                                     struct device_attribute *attr,
 414                                     const char *buf,
 415                                     size_t count)
 416 {
 417         struct drm_device *ddev = dev_get_drvdata(dev);
 418         struct radeon_device *rdev = ddev->dev_private;
 419
 420         /* Can't set method when the card is off */
 421         if  ((rdev->flags & RADEON_IS_PX) &&
 422              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
 423                 count = -EINVAL;
 424                 goto fail;
 425         }
 426
 427         /* we don't support the legacy modes with dpm */
 428         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 429                 count = -EINVAL;
 430                 goto fail;
 431         }
 432
 433         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 434                 mutex_lock(&rdev->pm.mutex);
 435                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 436                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 437                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 438                 mutex_unlock(&rdev->pm.mutex);
 439         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 440                 mutex_lock(&rdev->pm.mutex);
 441                 /* disable dynpm */
 442                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 443                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 444                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 445                 mutex_unlock(&rdev->pm.mutex);
 446                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 447         } else {
 448                 count = -EINVAL;
 449                 goto fail;
 450         }
 451         radeon_pm_compute_clocks(rdev);
 452 fail:
 453         return count;
 454 }
 455
 456 static ssize_t radeon_get_dpm_state(struct device *dev,
 457                                     struct device_attribute *attr,
 458                                     char *buf)
 459 {
 460         struct drm_device *ddev = dev_get_drvdata(dev);
 461         struct radeon_device *rdev = ddev->dev_private;
 462         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 463
 464         return snprintf(buf, PAGE_SIZE, "%s\n",
 465                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 466                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 467 }
 468
 469 static ssize_t radeon_set_dpm_state(struct device *dev,
 470                                     struct device_attribute *attr,
 471                                     const char *buf,
 472                                     size_t count)
 473 {
 474         struct drm_device *ddev = dev_get_drvdata(dev);
 475         struct radeon_device *rdev = ddev->dev_private;
 476
 477         mutex_lock(&rdev->pm.mutex);
 478         if (strncmp("battery", buf, strlen("battery")) == 0)
 479                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 480         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 481                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 482         else if (strncmp("performance", buf, strlen("performance")) == 0)
 483                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 484         else {
 485                 mutex_unlock(&rdev->pm.mutex);
 486                 count = -EINVAL;
 487                 goto fail;
 488         }
 489         mutex_unlock(&rdev->pm.mutex);
 490
 491         /* Can't set dpm state when the card is off */
 492         if (!(rdev->flags & RADEON_IS_PX) ||
 493             (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 494                 radeon_pm_compute_clocks(rdev);
 495
 496 fail:
 497         return count;
 498 }
 499
 500 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
 501                                                        struct device_attribute *attr,
 502                                                        char *buf)
 503 {
 504         struct drm_device *ddev = dev_get_drvdata(dev);
 505         struct radeon_device *rdev = ddev->dev_private;
 506         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
 507
 508         if  ((rdev->flags & RADEON_IS_PX) &&
 509              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 510                 return snprintf(buf, PAGE_SIZE, "off\n");
 511
 512         return snprintf(buf, PAGE_SIZE, "%s\n",
 513                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 514                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
 515 }
 516
 517 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
 518                                                        struct device_attribute *attr,
 519                                                        const char *buf,
 520                                                        size_t count)
 521 {
 522         struct drm_device *ddev = dev_get_drvdata(dev);
 523         struct radeon_device *rdev = ddev->dev_private;
 524         enum radeon_dpm_forced_level level;
 525         int ret = 0;
 526
 527         /* Can't force performance level when the card is off */
 528         if  ((rdev->flags & RADEON_IS_PX) &&
 529              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 530                 return -EINVAL;
 531
 532         mutex_lock(&rdev->pm.mutex);
 533         if (strncmp("low", buf, strlen("low")) == 0) {
 534                 level = RADEON_DPM_FORCED_LEVEL_LOW;
 535         } else if (strncmp("high", buf, strlen("high")) == 0) {
 536                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
 537         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 538                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
 539         } else {
 540                 count = -EINVAL;
 541                 goto fail;
 542         }
 543         if (rdev->asic->dpm.force_performance_level) {
 544                 if (rdev->pm.dpm.thermal_active) {
 545                         count = -EINVAL;
 546                         goto fail;
 547                 }
 548                 ret = radeon_dpm_force_performance_level(rdev, level);
 549                 if (ret)
 550                         count = -EINVAL;
 551         }
 552 fail:
 553         mutex_unlock(&rdev->pm.mutex);
 554
 555         return count;
 556 }
 557
 558 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
 559                                             struct device_attribute *attr,
 560                                             char *buf)
 561 {
 562         struct radeon_device *rdev = dev_get_drvdata(dev);
 563         u32 pwm_mode = 0;
 564
 565         if (rdev->asic->dpm.fan_ctrl_get_mode)
 566                 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
 567
 568         /* never 0 (full-speed), fuse or smc-controlled always */
 569         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 570 }
 571
 572 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
 573                                             struct device_attribute *attr,
 574                                             const char *buf,
 575                                             size_t count)
 576 {
 577         struct radeon_device *rdev = dev_get_drvdata(dev);
 578         int err;
 579         int value;
 580
 581         if(!rdev->asic->dpm.fan_ctrl_set_mode)
 582                 return -EINVAL;
 583
 584         err = kstrtoint(buf, 10, &value);
 585         if (err)
 586                 return err;
 587
 588         switch (value) {
 589         case 1: /* manual, percent-based */
 590                 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
 591                 break;
 592         default: /* disable */
 593                 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
 594                 break;
 595         }
 596
 597         return count;
 598 }
 599
 600 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
 601                                          struct device_attribute *attr,
 602                                          char *buf)
 603 {
 604         return sprintf(buf, "%i\n", 0);
 605 }
 606
 607 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
 608                                          struct device_attribute *attr,
 609                                          char *buf)
 610 {
 611         return sprintf(buf, "%i\n", 255);
 612 }
 613
 614 static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
 615                                      struct device_attribute *attr,
 616                                      const char *buf, size_t count)
 617 {
 618         struct radeon_device *rdev = dev_get_drvdata(dev);
 619         int err;
 620         u32 value;
 621
 622         err = kstrtou32(buf, 10, &value);
 623         if (err)
 624                 return err;
 625
 626         value = (value * 100) / 255;
 627
 628         err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
 629         if (err)
 630                 return err;
 631
 632         return count;
 633 }
 634
 635 static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
 636                                      struct device_attribute *attr,
 637                                      char *buf)
 638 {
 639         struct radeon_device *rdev = dev_get_drvdata(dev);
 640         int err;
 641         u32 speed;
 642
 643         err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
 644         if (err)
 645                 return err;
 646
 647         speed = (speed * 255) / 100;
 648
 649         return sprintf(buf, "%i\n", speed);
 650 }
 651
 652 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 653 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 654 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 655 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 656                    radeon_get_dpm_forced_performance_level,
 657                    radeon_set_dpm_forced_performance_level);
 658
 659 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 660                                       struct device_attribute *attr,
 661                                       char *buf)
 662 {
 663         struct radeon_device *rdev = dev_get_drvdata(dev);
 664         struct drm_device *ddev = rdev->ddev;
 665         int temp;
 666
 667         /* Can't get temperature when the card is off */
 668         if  ((rdev->flags & RADEON_IS_PX) &&
 669              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 670                 return -EINVAL;
 671
 672         if (rdev->asic->pm.get_temperature)
 673                 temp = radeon_get_temperature(rdev);
 674         else
 675                 temp = 0;
 676
 677         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 678 }
 679
 680 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
 681                                              struct device_attribute *attr,
 682                                              char *buf)
 683 {
 684         struct radeon_device *rdev = dev_get_drvdata(dev);
 685         int hyst = to_sensor_dev_attr(attr)->index;
 686         int temp;
 687
 688         if (hyst)
 689                 temp = rdev->pm.dpm.thermal.min_temp;
 690         else
 691                 temp = rdev->pm.dpm.thermal.max_temp;
 692
 693         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 694 }
 695
 696 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 697 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
 698 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
 699 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
 700 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
 701 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
 702 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
 703
 704
 705 static struct attribute *hwmon_attributes[] = {
 706         &sensor_dev_attr_temp1_input.dev_attr.attr,
 707         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 708         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 709         &sensor_dev_attr_pwm1.dev_attr.attr,
 710         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 711         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 712         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 713         NULL
 714 };
 715
 716 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 717                                         struct attribute *attr, int index)
 718 {
 719         struct device *dev = container_of(kobj, struct device, kobj);
 720         struct radeon_device *rdev = dev_get_drvdata(dev);
 721         umode_t effective_mode = attr->mode;
 722
 723         /* Skip limit attributes if DPM is not enabled */
 724         if (rdev->pm.pm_method != PM_METHOD_DPM &&
 725             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 726              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
 727                 return 0;
 728
 729         /* Skip fan attributes if fan is not present */
 730         if (rdev->pm.no_fan &&
 731             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 732              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 733              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 734              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 735                 return 0;
 736
 737         /* mask fan attributes if we have no bindings for this asic to expose */
 738         if ((!rdev->asic->dpm.get_fan_speed_percent &&
 739              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
 740             (!rdev->asic->dpm.fan_ctrl_get_mode &&
 741              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
 742                 effective_mode &= ~S_IRUGO;
 743
 744         if ((!rdev->asic->dpm.set_fan_speed_percent &&
 745              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
 746             (!rdev->asic->dpm.fan_ctrl_set_mode &&
 747              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
 748                 effective_mode &= ~S_IWUSR;
 749
 750         /* hide max/min values if we can't both query and manage the fan */
 751         if ((!rdev->asic->dpm.set_fan_speed_percent &&
 752              !rdev->asic->dpm.get_fan_speed_percent) &&
 753             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 754              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 755                 return 0;
 756
 757         return effective_mode;
 758 }
 759
 760 static const struct attribute_group hwmon_attrgroup = {
 761         .attrs = hwmon_attributes,
 762         .is_visible = hwmon_attributes_visible,
 763 };
 764
 765 static const struct attribute_group *hwmon_groups[] = {
 766         &hwmon_attrgroup,
 767         NULL
 768 };
 769
 770 static int radeon_hwmon_init(struct radeon_device *rdev)
 771 {
 772         int err = 0;
 773
 774         switch (rdev->pm.int_thermal_type) {
 775         case THERMAL_TYPE_RV6XX:
 776         case THERMAL_TYPE_RV770:
 777         case THERMAL_TYPE_EVERGREEN:
 778         case THERMAL_TYPE_NI:
 779         case THERMAL_TYPE_SUMO:
 780         case THERMAL_TYPE_SI:
 781         case THERMAL_TYPE_CI:
 782         case THERMAL_TYPE_KV:
 783                 if (rdev->asic->pm.get_temperature == NULL)
 784                         return err;
 785                 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
 786                                                                            "radeon", rdev,
 787                                                                            hwmon_groups);
 788                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 789                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 790                         dev_err(rdev->dev,
 791                                 "Unable to register hwmon device: %d\n", err);
 792                 }
 793                 break;
 794         default:
 795                 break;
 796         }
 797
 798         return err;
 799 }
 800
 801 static void radeon_hwmon_fini(struct radeon_device *rdev)
 802 {
 803         if (rdev->pm.int_hwmon_dev)
 804                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 805 }
 806
 807 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 808 {
 809         struct radeon_device *rdev =
 810                 container_of(work, struct radeon_device,
 811                              pm.dpm.thermal.work);
 812         /* switch to the thermal state */
 813         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 814
 815         if (!rdev->pm.dpm_enabled)
 816                 return;
 817
 818         if (rdev->asic->pm.get_temperature) {
 819                 int temp = radeon_get_temperature(rdev);
 820
 821                 if (temp < rdev->pm.dpm.thermal.min_temp)
 822                         /* switch back the user state */
 823                         dpm_state = rdev->pm.dpm.user_state;
 824         } else {
 825                 if (rdev->pm.dpm.thermal.high_to_low)
 826                         /* switch back the user state */
 827                         dpm_state = rdev->pm.dpm.user_state;
 828         }
 829         mutex_lock(&rdev->pm.mutex);
 830         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
 831                 rdev->pm.dpm.thermal_active = true;
 832         else
 833                 rdev->pm.dpm.thermal_active = false;
 834         rdev->pm.dpm.state = dpm_state;
 835         mutex_unlock(&rdev->pm.mutex);
 836
 837         radeon_pm_compute_clocks(rdev);
 838 }
 839
 840 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 841                                                      enum radeon_pm_state_type dpm_state)
 842 {
 843         int i;
 844         struct radeon_ps *ps;
 845         u32 ui_class;
 846         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
 847                 true : false;
 848
 849         /* check if the vblank period is too short to adjust the mclk */
 850         if (single_display && rdev->asic->dpm.vblank_too_short) {
 851                 if (radeon_dpm_vblank_too_short(rdev))
 852                         single_display = false;
 853         }
 854
 855         /* 120hz tends to be problematic even if they are under the
 856          * vblank limit.
 857          */
 858         if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
 859                 single_display = false;
 860
 861         /* certain older asics have a separare 3D performance state,
 862          * so try that first if the user selected performance
 863          */
 864         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
 865                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
 866         /* balanced states don't exist at the moment */
 867         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 868                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 869
 870 restart_search:
 871         /* Pick the best power state based on current conditions */
 872         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 873                 ps = &rdev->pm.dpm.ps[i];
 874                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 875                 switch (dpm_state) {
 876                 /* user states */
 877                 case POWER_STATE_TYPE_BATTERY:
 878                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 879                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 880                                         if (single_display)
 881                                                 return ps;
 882                                 } else
 883                                         return ps;
 884                         }
 885                         break;
 886                 case POWER_STATE_TYPE_BALANCED:
 887                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 888                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 889                                         if (single_display)
 890                                                 return ps;
 891                                 } else
 892                                         return ps;
 893                         }
 894                         break;
 895                 case POWER_STATE_TYPE_PERFORMANCE:
 896                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 897                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 898                                         if (single_display)
 899                                                 return ps;
 900                                 } else
 901                                         return ps;
 902                         }
 903                         break;
 904                 /* internal states */
 905                 case POWER_STATE_TYPE_INTERNAL_UVD:
 906                         if (rdev->pm.dpm.uvd_ps)
 907                                 return rdev->pm.dpm.uvd_ps;
 908                         else
 909                                 break;
 910                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 911                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 912                                 return ps;
 913                         break;
 914                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 915                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 916                                 return ps;
 917                         break;
 918                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 919                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 920                                 return ps;
 921                         break;
 922                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 923                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 924                                 return ps;
 925                         break;
 926                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 927                         return rdev->pm.dpm.boot_ps;
 928                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 929                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 930                                 return ps;
 931                         break;
 932                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 933                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 934                                 return ps;
 935                         break;
 936                 case POWER_STATE_TYPE_INTERNAL_ULV:
 937                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 938                                 return ps;
 939                         break;
 940                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
 941                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
 942                                 return ps;
 943                         break;
 944                 default:
 945                         break;
 946                 }
 947         }
 948         /* use a fallback state if we didn't match */
 949         switch (dpm_state) {
 950         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 951                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
 952                 goto restart_search;
 953         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 954         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 955         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 956                 if (rdev->pm.dpm.uvd_ps) {
 957                         return rdev->pm.dpm.uvd_ps;
 958                 } else {
 959                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 960                         goto restart_search;
 961                 }
 962         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 963                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 964                 goto restart_search;
 965         case POWER_STATE_TYPE_INTERNAL_ACPI:
 966                 dpm_state = POWER_STATE_TYPE_BATTERY;
 967                 goto restart_search;
 968         case POWER_STATE_TYPE_BATTERY:
 969         case POWER_STATE_TYPE_BALANCED:
 970         case POWER_STATE_TYPE_INTERNAL_3DPERF:
 971                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 972                 goto restart_search;
 973         default:
 974                 break;
 975         }
 976
 977         return NULL;
 978 }
 979
 980 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 981 {
 982         int i;
 983         struct radeon_ps *ps;
 984         enum radeon_pm_state_type dpm_state;
 985         int ret;
 986
 987         /* if dpm init failed */
 988         if (!rdev->pm.dpm_enabled)
 989                 return;
 990
 991         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 992                 /* add other state override checks here */
 993                 if ((!rdev->pm.dpm.thermal_active) &&
 994                     (!rdev->pm.dpm.uvd_active))
 995                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 996         }
 997         dpm_state = rdev->pm.dpm.state;
 998
 999         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1000         if (ps)
1001                 rdev->pm.dpm.requested_ps = ps;
1002         else
1003                 return;
1004
1005         /* no need to reprogram if nothing changed unless we are on BTC+ */
1006         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1007                 /* vce just modifies an existing state so force a change */
1008                 if (ps->vce_active != rdev->pm.dpm.vce_active)
1009                         goto force;
1010                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1011                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1012                          * all we need to do is update the display configuration.
1013                          */
1014                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1015                                 /* update display watermarks based on new power state */
1016                                 radeon_bandwidth_update(rdev);
1017                                 /* update displays */
1018                                 radeon_dpm_display_configuration_changed(rdev);
1019                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1020                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1021                         }
1022                         return;
1023                 } else {
1024                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
1025                          * nothing to do, if the num crtcs is > 1 and state is the same,
1026                          * update display configuration.
1027                          */
1028                         if (rdev->pm.dpm.new_active_crtcs ==
1029                             rdev->pm.dpm.current_active_crtcs) {
1030                                 return;
1031                         } else {
1032                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1033                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
1034                                         /* update display watermarks based on new power state */
1035                                         radeon_bandwidth_update(rdev);
1036                                         /* update displays */
1037                                         radeon_dpm_display_configuration_changed(rdev);
1038                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1039                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1040                                         return;
1041                                 }
1042                         }
1043                 }
1044         }
1045
1046 force:
1047         if (radeon_dpm == 1) {
1048                 printk("switching from power state:\n");
1049                 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1050                 printk("switching to power state:\n");
1051                 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1052         }
1053
1054         mutex_lock(&rdev->ddev->struct_mutex);
1055         down_write(&rdev->pm.mclk_lock);
1056         mutex_lock(&rdev->ring_lock);
1057
1058         /* update whether vce is active */
1059         ps->vce_active = rdev->pm.dpm.vce_active;
1060
1061         ret = radeon_dpm_pre_set_power_state(rdev);
1062         if (ret)
1063                 goto done;
1064
1065         /* update display watermarks based on new power state */
1066         radeon_bandwidth_update(rdev);
1067         /* update displays */
1068         radeon_dpm_display_configuration_changed(rdev);
1069
1070         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1071         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1072
1073         /* wait for the rings to drain */
1074         for (i = 0; i < RADEON_NUM_RINGS; i++) {
1075                 struct radeon_ring *ring = &rdev->ring[i];
1076                 if (ring->ready)
1077                         radeon_fence_wait_empty(rdev, i);
1078         }
1079
1080         /* program the new power state */
1081         radeon_dpm_set_power_state(rdev);
1082
1083         /* update current power state */
1084         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1085
1086         radeon_dpm_post_set_power_state(rdev);
1087
1088         if (rdev->asic->dpm.force_performance_level) {
1089                 if (rdev->pm.dpm.thermal_active) {
1090                         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1091                         /* force low perf level for thermal */
1092                         radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1093                         /* save the user's level */
1094                         rdev->pm.dpm.forced_level = level;
1095                 } else {
1096                         /* otherwise, user selected level */
1097                         radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1098                 }
1099         }
1100
1101 done:
1102         mutex_unlock(&rdev->ring_lock);
1103         up_write(&rdev->pm.mclk_lock);
1104         mutex_unlock(&rdev->ddev->struct_mutex);
1105 }
1106
1107 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1108 {
1109         enum radeon_pm_state_type dpm_state;
1110
1111         if (rdev->asic->dpm.powergate_uvd) {
1112                 mutex_lock(&rdev->pm.mutex);
1113                 /* don't powergate anything if we
1114                    have active but pause streams */
1115                 enable |= rdev->pm.dpm.sd > 0;
1116                 enable |= rdev->pm.dpm.hd > 0;
1117                 /* enable/disable UVD */
1118                 radeon_dpm_powergate_uvd(rdev, !enable);
1119                 mutex_unlock(&rdev->pm.mutex);
1120         } else {
1121                 if (enable) {
1122                         mutex_lock(&rdev->pm.mutex);
1123                         rdev->pm.dpm.uvd_active = true;
1124                         /* disable this for now */
1125 #if 0
1126                         if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1127                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1128                         else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1129                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1130                         else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1131                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1132                         else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1133                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1134                         else
1135 #endif
1136                                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1137                         rdev->pm.dpm.state = dpm_state;
1138                         mutex_unlock(&rdev->pm.mutex);
1139                 } else {
1140                         mutex_lock(&rdev->pm.mutex);
1141                         rdev->pm.dpm.uvd_active = false;
1142                         mutex_unlock(&rdev->pm.mutex);
1143                 }
1144
1145                 radeon_pm_compute_clocks(rdev);
1146         }
1147 }
1148
1149 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1150 {
1151         if (enable) {
1152                 mutex_lock(&rdev->pm.mutex);
1153                 rdev->pm.dpm.vce_active = true;
1154                 /* XXX select vce level based on ring/task */
1155                 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1156                 mutex_unlock(&rdev->pm.mutex);
1157         } else {
1158                 mutex_lock(&rdev->pm.mutex);
1159                 rdev->pm.dpm.vce_active = false;
1160                 mutex_unlock(&rdev->pm.mutex);
1161         }
1162
1163         radeon_pm_compute_clocks(rdev);
1164 }
1165
1166 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1167 {
1168         mutex_lock(&rdev->pm.mutex);
1169         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1170                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1171                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1172         }
1173         mutex_unlock(&rdev->pm.mutex);
1174
1175         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1176 }
1177
1178 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1179 {
1180         mutex_lock(&rdev->pm.mutex);
1181         /* disable dpm */
1182         radeon_dpm_disable(rdev);
1183         /* reset the power state */
1184         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1185         rdev->pm.dpm_enabled = false;
1186         mutex_unlock(&rdev->pm.mutex);
1187 }
1188
1189 void radeon_pm_suspend(struct radeon_device *rdev)
1190 {
1191         if (rdev->pm.pm_method == PM_METHOD_DPM)
1192                 radeon_pm_suspend_dpm(rdev);
1193         else
1194                 radeon_pm_suspend_old(rdev);
1195 }
1196
1197 static void radeon_pm_resume_old(struct radeon_device *rdev)
1198 {
1199         /* set up the default clocks if the MC ucode is loaded */
1200         if ((rdev->family >= CHIP_BARTS) &&
1201             (rdev->family <= CHIP_CAYMAN) &&
1202             rdev->mc_fw) {
1203                 if (rdev->pm.default_vddc)
1204                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1205                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
1206                 if (rdev->pm.default_vddci)
1207                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1208                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1209                 if (rdev->pm.default_sclk)
1210                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1211                 if (rdev->pm.default_mclk)
1212                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1213         }
1214         /* asic init will reset the default power state */
1215         mutex_lock(&rdev->pm.mutex);
1216         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1217         rdev->pm.current_clock_mode_index = 0;
1218         rdev->pm.current_sclk = rdev->pm.default_sclk;
1219         rdev->pm.current_mclk = rdev->pm.default_mclk;
1220         if (rdev->pm.power_state) {
1221                 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1222                 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1223         }
1224         if (rdev->pm.pm_method == PM_METHOD_DYNPM
1225             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1226                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1227                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1228                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1229         }
1230         mutex_unlock(&rdev->pm.mutex);
1231         radeon_pm_compute_clocks(rdev);
1232 }
1233
1234 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1235 {
1236         int ret;
1237
1238         /* asic init will reset to the boot state */
1239         mutex_lock(&rdev->pm.mutex);
1240         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1241         radeon_dpm_setup_asic(rdev);
1242         ret = radeon_dpm_enable(rdev);
1243         mutex_unlock(&rdev->pm.mutex);
1244         if (ret)
1245                 goto dpm_resume_fail;
1246         rdev->pm.dpm_enabled = true;
1247         return;
1248
1249 dpm_resume_fail:
1250         DRM_ERROR("radeon: dpm resume failed\n");
1251         if ((rdev->family >= CHIP_BARTS) &&
1252             (rdev->family <= CHIP_CAYMAN) &&
1253             rdev->mc_fw) {
1254                 if (rdev->pm.default_vddc)
1255                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1256                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
1257                 if (rdev->pm.default_vddci)
1258                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1259                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1260                 if (rdev->pm.default_sclk)
1261                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1262                 if (rdev->pm.default_mclk)
1263                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1264         }
1265 }
1266
1267 void radeon_pm_resume(struct radeon_device *rdev)
1268 {
1269         if (rdev->pm.pm_method == PM_METHOD_DPM)
1270                 radeon_pm_resume_dpm(rdev);
1271         else
1272                 radeon_pm_resume_old(rdev);
1273 }
1274
1275 static int radeon_pm_init_old(struct radeon_device *rdev)
1276 {
1277         int ret;
1278
1279         rdev->pm.profile = PM_PROFILE_DEFAULT;
1280         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1281         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1282         rdev->pm.dynpm_can_upclock = true;
1283         rdev->pm.dynpm_can_downclock = true;
1284         rdev->pm.default_sclk = rdev->clock.default_sclk;
1285         rdev->pm.default_mclk = rdev->clock.default_mclk;
1286         rdev->pm.current_sclk = rdev->clock.default_sclk;
1287         rdev->pm.current_mclk = rdev->clock.default_mclk;
1288         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1289
1290         if (rdev->bios) {
1291                 if (rdev->is_atom_bios)
1292                         radeon_atombios_get_power_modes(rdev);
1293                 else
1294                         radeon_combios_get_power_modes(rdev);
1295                 radeon_pm_print_states(rdev);
1296                 radeon_pm_init_profile(rdev);
1297                 /* set up the default clocks if the MC ucode is loaded */
1298                 if ((rdev->family >= CHIP_BARTS) &&
1299                     (rdev->family <= CHIP_CAYMAN) &&
1300                     rdev->mc_fw) {
1301                         if (rdev->pm.default_vddc)
1302                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1303                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1304                         if (rdev->pm.default_vddci)
1305                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1306                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1307                         if (rdev->pm.default_sclk)
1308                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1309                         if (rdev->pm.default_mclk)
1310                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1311                 }
1312         }
1313
1314         /* set up the internal thermal sensor if applicable */
1315         ret = radeon_hwmon_init(rdev);
1316         if (ret)
1317                 return ret;
1318
1319         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1320
1321         if (rdev->pm.num_power_states > 1) {
1322                 /* where's the best place to put these? */
1323                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1324                 if (ret)
1325                         DRM_ERROR("failed to create device file for power profile\n");
1326                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1327                 if (ret)
1328                         DRM_ERROR("failed to create device file for power method\n");
1329
1330                 if (radeon_debugfs_pm_init(rdev)) {
1331                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1332                 }
1333
1334                 DRM_INFO("radeon: power management initialized\n");
1335         }
1336
1337         return 0;
1338 }
1339
1340 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1341 {
1342         int i;
1343
1344         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1345                 printk("== power state %d ==\n", i);
1346                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1347         }
1348 }
1349
1350 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1351 {
1352         int ret;
1353
1354         /* default to balanced state */
1355         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1356         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1357         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1358         rdev->pm.default_sclk = rdev->clock.default_sclk;
1359         rdev->pm.default_mclk = rdev->clock.default_mclk;
1360         rdev->pm.current_sclk = rdev->clock.default_sclk;
1361         rdev->pm.current_mclk = rdev->clock.default_mclk;
1362         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1363
1364         if (rdev->bios && rdev->is_atom_bios)
1365                 radeon_atombios_get_power_modes(rdev);
1366         else
1367                 return -EINVAL;
1368
1369         /* set up the internal thermal sensor if applicable */
1370         ret = radeon_hwmon_init(rdev);
1371         if (ret)
1372                 return ret;
1373
1374         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1375         mutex_lock(&rdev->pm.mutex);
1376         radeon_dpm_init(rdev);
1377         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1378         if (radeon_dpm == 1)
1379                 radeon_dpm_print_power_states(rdev);
1380         radeon_dpm_setup_asic(rdev);
1381         ret = radeon_dpm_enable(rdev);
1382         mutex_unlock(&rdev->pm.mutex);
1383         if (ret)
1384                 goto dpm_failed;
1385         rdev->pm.dpm_enabled = true;
1386
1387         ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1388         if (ret)
1389                 DRM_ERROR("failed to create device file for dpm state\n");
1390         ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1391         if (ret)
1392                 DRM_ERROR("failed to create device file for dpm state\n");
1393         /* XXX: these are noops for dpm but are here for backwards compat */
1394         ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1395         if (ret)
1396                 DRM_ERROR("failed to create device file for power profile\n");
1397         ret = device_create_file(rdev->dev, &dev_attr_power_method);
1398         if (ret)
1399                 DRM_ERROR("failed to create device file for power method\n");
1400
1401         if (radeon_debugfs_pm_init(rdev)) {
1402                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1403         }
1404
1405         DRM_INFO("radeon: dpm initialized\n");
1406
1407         return 0;
1408
1409 dpm_failed:
1410         rdev->pm.dpm_enabled = false;
1411         if ((rdev->family >= CHIP_BARTS) &&
1412             (rdev->family <= CHIP_CAYMAN) &&
1413             rdev->mc_fw) {
1414                 if (rdev->pm.default_vddc)
1415                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1416                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
1417                 if (rdev->pm.default_vddci)
1418                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1419                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1420                 if (rdev->pm.default_sclk)
1421                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1422                 if (rdev->pm.default_mclk)
1423                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1424         }
1425         DRM_ERROR("radeon: dpm initialization failed\n");
1426         return ret;
1427 }
1428
1429 struct radeon_dpm_quirk {
1430         u32 chip_vendor;
1431         u32 chip_device;
1432         u32 subsys_vendor;
1433         u32 subsys_device;
1434 };
1435
1436 /* cards with dpm stability problems */
1437 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1438         /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1439         { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1440         /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1441         { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1442         { 0, 0, 0, 0 },
1443 };
1444
1445 int radeon_pm_init(struct radeon_device *rdev)
1446 {
1447         struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1448         bool disable_dpm = false;
1449
1450         /* Apply dpm quirks */
1451         while (p && p->chip_device != 0) {
1452                 if (rdev->pdev->vendor == p->chip_vendor &&
1453                     rdev->pdev->device == p->chip_device &&
1454                     rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1455                     rdev->pdev->subsystem_device == p->subsys_device) {
1456                         disable_dpm = true;
1457                         break;
1458                 }
1459                 ++p;
1460         }
1461
1462         /* enable dpm on rv6xx+ */
1463         switch (rdev->family) {
1464         case CHIP_RV610:
1465         case CHIP_RV630:
1466         case CHIP_RV620:
1467         case CHIP_RV635:
1468         case CHIP_RV670:
1469         case CHIP_RS780:
1470         case CHIP_RS880:
1471         case CHIP_RV770:
1472                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1473                 if (!rdev->rlc_fw)
1474                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1475                 else if ((rdev->family >= CHIP_RV770) &&
1476                          (!(rdev->flags & RADEON_IS_IGP)) &&
1477                          (!rdev->smc_fw))
1478                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1479                 else if (radeon_dpm == 1)
1480                         rdev->pm.pm_method = PM_METHOD_DPM;
1481                 else
1482                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1483                 break;
1484         case CHIP_RV730:
1485         case CHIP_RV710:
1486         case CHIP_RV740:
1487         case CHIP_CEDAR:
1488         case CHIP_REDWOOD:
1489         case CHIP_JUNIPER:
1490         case CHIP_CYPRESS:
1491         case CHIP_HEMLOCK:
1492         case CHIP_PALM:
1493         case CHIP_SUMO:
1494         case CHIP_SUMO2:
1495         case CHIP_BARTS:
1496         case CHIP_TURKS:
1497         case CHIP_CAICOS:
1498         case CHIP_CAYMAN:
1499         case CHIP_ARUBA:
1500         case CHIP_TAHITI:
1501         case CHIP_PITCAIRN:
1502         case CHIP_VERDE:
1503         case CHIP_OLAND:
1504         case CHIP_HAINAN:
1505         case CHIP_BONAIRE:
1506         case CHIP_KABINI:
1507         case CHIP_KAVERI:
1508         case CHIP_HAWAII:
1509         case CHIP_MULLINS:
1510                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1511                 if (!rdev->rlc_fw)
1512                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1513                 else if ((rdev->family >= CHIP_RV770) &&
1514                          (!(rdev->flags & RADEON_IS_IGP)) &&
1515                          (!rdev->smc_fw))
1516                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1517                 else if (disable_dpm && (radeon_dpm == -1))
1518                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1519                 else if (radeon_dpm == 0)
1520                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1521                 else
1522                         rdev->pm.pm_method = PM_METHOD_DPM;
1523                 break;
1524         default:
1525                 /* default to profile method */
1526                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1527                 break;
1528         }
1529
1530         if (rdev->pm.pm_method == PM_METHOD_DPM)
1531                 return radeon_pm_init_dpm(rdev);
1532         else
1533                 return radeon_pm_init_old(rdev);
1534 }
1535
1536 int radeon_pm_late_init(struct radeon_device *rdev)
1537 {
1538         int ret = 0;
1539
1540         if (rdev->pm.pm_method == PM_METHOD_DPM) {
1541                 mutex_lock(&rdev->pm.mutex);
1542                 ret = radeon_dpm_late_enable(rdev);
1543                 mutex_unlock(&rdev->pm.mutex);
1544         }
1545         return ret;
1546 }
1547
1548 static void radeon_pm_fini_old(struct radeon_device *rdev)
1549 {
1550         if (rdev->pm.num_power_states > 1) {
1551                 mutex_lock(&rdev->pm.mutex);
1552                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1553                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1554                         radeon_pm_update_profile(rdev);
1555                         radeon_pm_set_clocks(rdev);
1556                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1557                         /* reset default clocks */
1558                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1559                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1560                         radeon_pm_set_clocks(rdev);
1561                 }
1562                 mutex_unlock(&rdev->pm.mutex);
1563
1564                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1565
1566                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1567                 device_remove_file(rdev->dev, &dev_attr_power_method);
1568         }
1569
1570         radeon_hwmon_fini(rdev);
1571         kfree(rdev->pm.power_state);
1572 }
1573
1574 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1575 {
1576         if (rdev->pm.num_power_states > 1) {
1577                 mutex_lock(&rdev->pm.mutex);
1578                 radeon_dpm_disable(rdev);
1579                 mutex_unlock(&rdev->pm.mutex);
1580
1581                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1582                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1583                 /* XXX backwards compat */
1584                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1585                 device_remove_file(rdev->dev, &dev_attr_power_method);
1586         }
1587         radeon_dpm_fini(rdev);
1588
1589         radeon_hwmon_fini(rdev);
1590         kfree(rdev->pm.power_state);
1591 }
1592
1593 void radeon_pm_fini(struct radeon_device *rdev)
1594 {
1595         if (rdev->pm.pm_method == PM_METHOD_DPM)
1596                 radeon_pm_fini_dpm(rdev);
1597         else
1598                 radeon_pm_fini_old(rdev);
1599 }
1600
1601 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1602 {
1603         struct drm_device *ddev = rdev->ddev;
1604         struct drm_crtc *crtc;
1605         struct radeon_crtc *radeon_crtc;
1606
1607         if (rdev->pm.num_power_states < 2)
1608                 return;
1609
1610         mutex_lock(&rdev->pm.mutex);
1611
1612         rdev->pm.active_crtcs = 0;
1613         rdev->pm.active_crtc_count = 0;
1614         if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1615                 list_for_each_entry(crtc,
1616                                     &ddev->mode_config.crtc_list, head) {
1617                         radeon_crtc = to_radeon_crtc(crtc);
1618                         if (radeon_crtc->enabled) {
1619                                 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1620                                 rdev->pm.active_crtc_count++;
1621                         }
1622                 }
1623         }
1624
1625         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1626                 radeon_pm_update_profile(rdev);
1627                 radeon_pm_set_clocks(rdev);
1628         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1629                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1630                         if (rdev->pm.active_crtc_count > 1) {
1631                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1632                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1633
1634                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1635                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1636                                         radeon_pm_get_dynpm_state(rdev);
1637                                         radeon_pm_set_clocks(rdev);
1638
1639                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1640                                 }
1641                         } else if (rdev->pm.active_crtc_count == 1) {
1642                                 /* TODO: Increase clocks if needed for current mode */
1643
1644                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1645                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1646                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1647                                         radeon_pm_get_dynpm_state(rdev);
1648                                         radeon_pm_set_clocks(rdev);
1649
1650                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1651                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1652                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1653                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1654                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1655                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1656                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1657                                 }
1658                         } else { /* count == 0 */
1659                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1660                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1661
1662                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1663                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1664                                         radeon_pm_get_dynpm_state(rdev);
1665                                         radeon_pm_set_clocks(rdev);
1666                                 }
1667                         }
1668                 }
1669         }
1670
1671         mutex_unlock(&rdev->pm.mutex);
1672 }
1673
1674 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1675 {
1676         struct drm_device *ddev = rdev->ddev;
1677         struct drm_crtc *crtc;
1678         struct radeon_crtc *radeon_crtc;
1679
1680         if (!rdev->pm.dpm_enabled)
1681                 return;
1682
1683         mutex_lock(&rdev->pm.mutex);
1684
1685         /* update active crtc counts */
1686         rdev->pm.dpm.new_active_crtcs = 0;
1687         rdev->pm.dpm.new_active_crtc_count = 0;
1688         if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1689                 list_for_each_entry(crtc,
1690                                     &ddev->mode_config.crtc_list, head) {
1691                         radeon_crtc = to_radeon_crtc(crtc);
1692                         if (crtc->enabled) {
1693                                 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1694                                 rdev->pm.dpm.new_active_crtc_count++;
1695                         }
1696                 }
1697         }
1698
1699         /* update battery/ac status */
1700         if (power_supply_is_system_supplied() > 0)
1701                 rdev->pm.dpm.ac_power = true;
1702         else
1703                 rdev->pm.dpm.ac_power = false;
1704
1705         radeon_dpm_change_power_state_locked(rdev);
1706
1707         mutex_unlock(&rdev->pm.mutex);
1708
1709 }
1710
1711 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1712 {
1713         if (rdev->pm.pm_method == PM_METHOD_DPM)
1714                 radeon_pm_compute_clocks_dpm(rdev);
1715         else
1716                 radeon_pm_compute_clocks_old(rdev);
1717 }
1718
1719 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1720 {
1721         int  crtc, vpos, hpos, vbl_status;
1722         bool in_vbl = true;
1723
1724         /* Iterate over all active crtc's. All crtc's must be in vblank,
1725          * otherwise return in_vbl == false.
1726          */
1727         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1728                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1729                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1730                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1731                             !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1732                                 in_vbl = false;
1733                 }
1734         }
1735
1736         return in_vbl;
1737 }
1738
1739 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1740 {
1741         u32 stat_crtc = 0;
1742         bool in_vbl = radeon_pm_in_vbl(rdev);
1743
1744         if (in_vbl == false)
1745                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1746                          finish ? "exit" : "entry");
1747         return in_vbl;
1748 }
1749
1750 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1751 {
1752         struct radeon_device *rdev;
1753         int resched;
1754         rdev = container_of(work, struct radeon_device,
1755                                 pm.dynpm_idle_work.work);
1756
1757         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1758         mutex_lock(&rdev->pm.mutex);
1759         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1760                 int not_processed = 0;
1761                 int i;
1762
1763                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1764                         struct radeon_ring *ring = &rdev->ring[i];
1765
1766                         if (ring->ready) {
1767                                 not_processed += radeon_fence_count_emitted(rdev, i);
1768                                 if (not_processed >= 3)
1769                                         break;
1770                         }
1771                 }
1772
1773                 if (not_processed >= 3) { /* should upclock */
1774                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1775                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1776                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1777                                    rdev->pm.dynpm_can_upclock) {
1778                                 rdev->pm.dynpm_planned_action =
1779                                         DYNPM_ACTION_UPCLOCK;
1780                                 rdev->pm.dynpm_action_timeout = jiffies +
1781                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1782                         }
1783                 } else if (not_processed == 0) { /* should downclock */
1784                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1785                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1786                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1787                                    rdev->pm.dynpm_can_downclock) {
1788                                 rdev->pm.dynpm_planned_action =
1789                                         DYNPM_ACTION_DOWNCLOCK;
1790                                 rdev->pm.dynpm_action_timeout = jiffies +
1791                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1792                         }
1793                 }
1794
1795                 /* Note, radeon_pm_set_clocks is called with static_switch set
1796                  * to false since we want to wait for vbl to avoid flicker.
1797                  */
1798                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1799                     jiffies > rdev->pm.dynpm_action_timeout) {
1800                         radeon_pm_get_dynpm_state(rdev);
1801                         radeon_pm_set_clocks(rdev);
1802                 }
1803
1804                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1805                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1806         }
1807         mutex_unlock(&rdev->pm.mutex);
1808         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1809 }
1810
1811 /*
1812  * Debugfs info
1813  */
1814 #if defined(CONFIG_DEBUG_FS)
1815
1816 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1817 {
1818         struct drm_info_node *node = (struct drm_info_node *) m->private;
1819         struct drm_device *dev = node->minor->dev;
1820         struct radeon_device *rdev = dev->dev_private;
1821         struct drm_device *ddev = rdev->ddev;
1822
1823         if  ((rdev->flags & RADEON_IS_PX) &&
1824              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1825                 seq_printf(m, "PX asic powered off\n");
1826         } else if (rdev->pm.dpm_enabled) {
1827                 mutex_lock(&rdev->pm.mutex);
1828                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1829                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1830                 else
1831                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1832                 mutex_unlock(&rdev->pm.mutex);
1833         } else {
1834                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1835                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1836                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1837                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1838                 else
1839                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1840                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1841                 if (rdev->asic->pm.get_memory_clock)
1842                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1843                 if (rdev->pm.current_vddc)
1844                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1845                 if (rdev->asic->pm.get_pcie_lanes)
1846                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1847         }
1848
1849         return 0;
1850 }
1851
1852 static struct drm_info_list radeon_pm_info_list[] = {
1853         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1854 };
1855 #endif
1856
1857 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1858 {
1859 #if defined(CONFIG_DEBUG_FS)
1860         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1861 #else
1862         return 0;
1863 #endif
1864 }