2 * rcar_du_crtc.c -- R-Car Display Unit CRTCs
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/clk.h>
15 #include <linux/mutex.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_fb_cma_helper.h>
21 #include <drm/drm_gem_cma_helper.h>
22 #include <drm/drm_plane_helper.h>
24 #include "rcar_du_crtc.h"
25 #include "rcar_du_drv.h"
26 #include "rcar_du_kms.h"
27 #include "rcar_du_plane.h"
28 #include "rcar_du_regs.h"
30 static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
32 struct rcar_du_device *rcdu = rcrtc->group->dev;
34 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
37 static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
39 struct rcar_du_device *rcdu = rcrtc->group->dev;
41 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
44 static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
46 struct rcar_du_device *rcdu = rcrtc->group->dev;
48 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
49 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
52 static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
54 struct rcar_du_device *rcdu = rcrtc->group->dev;
56 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
57 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
60 static void rcar_du_crtc_clr_set(struct rcar_du_crtc *rcrtc, u32 reg,
63 struct rcar_du_device *rcdu = rcrtc->group->dev;
64 u32 value = rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
66 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, (value & ~clr) | set);
69 static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
73 ret = clk_prepare_enable(rcrtc->clock);
77 ret = rcar_du_group_get(rcrtc->group);
79 clk_disable_unprepare(rcrtc->clock);
84 static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
86 rcar_du_group_put(rcrtc->group);
87 clk_disable_unprepare(rcrtc->clock);
90 static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
92 const struct drm_display_mode *mode = &rcrtc->crtc.mode;
98 clk = clk_get_rate(rcrtc->clock);
99 div = DIV_ROUND_CLOSEST(clk, mode->clock * 1000);
100 div = clamp(div, 1U, 64U) - 1;
102 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? ESCR2 : ESCR,
103 ESCR_DCLKSEL_CLKS | div);
104 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? OTAR2 : OTAR, 0);
106 /* Signal polarities */
107 value = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? 0 : DSMR_VSL)
108 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? 0 : DSMR_HSL)
110 rcar_du_crtc_write(rcrtc, DSMR, value);
112 /* Display timings */
113 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start - 19);
114 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
115 mode->hdisplay - 19);
116 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
117 mode->hsync_start - 1);
118 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
120 rcar_du_crtc_write(rcrtc, VDSR, mode->vtotal - mode->vsync_end - 2);
121 rcar_du_crtc_write(rcrtc, VDER, mode->vtotal - mode->vsync_end +
123 rcar_du_crtc_write(rcrtc, VSPR, mode->vtotal - mode->vsync_end +
124 mode->vsync_start - 1);
125 rcar_du_crtc_write(rcrtc, VCR, mode->vtotal - 1);
127 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start);
128 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
131 void rcar_du_crtc_route_output(struct drm_crtc *crtc,
132 enum rcar_du_output output)
134 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
135 struct rcar_du_device *rcdu = rcrtc->group->dev;
137 /* Store the route from the CRTC output to the DU output. The DU will be
138 * configured when starting the CRTC.
140 rcrtc->outputs |= BIT(output);
142 /* Store RGB routing to DPAD0 for R8A7790. */
143 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_DEFR8) &&
144 output == RCAR_DU_OUTPUT_DPAD0)
145 rcdu->dpad0_source = rcrtc->index;
148 void rcar_du_crtc_update_planes(struct drm_crtc *crtc)
150 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
151 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
152 unsigned int num_planes = 0;
153 unsigned int prio = 0;
158 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
159 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
162 if (plane->crtc != &rcrtc->crtc || !plane->enabled)
165 /* Insert the plane in the sorted planes array. */
166 for (j = num_planes++; j > 0; --j) {
167 if (planes[j-1]->zpos <= plane->zpos)
169 planes[j] = planes[j-1];
173 prio += plane->format->planes * 4;
176 for (i = 0; i < num_planes; ++i) {
177 struct rcar_du_plane *plane = planes[i];
178 unsigned int index = plane->hwindex;
181 dspr |= (index + 1) << prio;
182 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
184 if (plane->format->planes == 2) {
185 index = (index + 1) % 8;
188 dspr |= (index + 1) << prio;
189 dptsr |= DPTSR_PnDK(index) | DPTSR_PnTS(index);
193 /* Select display timing and dot clock generator 2 for planes associated
194 * with superposition controller 2.
196 if (rcrtc->index % 2) {
197 u32 value = rcar_du_group_read(rcrtc->group, DPTSR);
199 /* The DPTSR register is updated when the display controller is
200 * stopped. We thus need to restart the DU. Once again, sorry
201 * for the flicker. One way to mitigate the issue would be to
202 * pre-associate planes with CRTCs (either with a fixed 4/4
203 * split, or through a module parameter). Flicker would then
204 * occur only if we need to break the pre-association.
206 if (value != dptsr) {
207 rcar_du_group_write(rcrtc->group, DPTSR, dptsr);
208 if (rcrtc->group->used_crtcs)
209 rcar_du_group_restart(rcrtc->group);
213 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
217 static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
219 struct drm_crtc *crtc = &rcrtc->crtc;
225 if (WARN_ON(rcrtc->plane->format == NULL))
228 /* Set display off and background to black */
229 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
230 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
232 /* Configure display timings and output routing */
233 rcar_du_crtc_set_display_timing(rcrtc);
234 rcar_du_group_set_routing(rcrtc->group);
236 mutex_lock(&rcrtc->group->planes.lock);
237 rcrtc->plane->enabled = true;
238 rcar_du_crtc_update_planes(crtc);
239 mutex_unlock(&rcrtc->group->planes.lock);
242 for (i = 0; i < ARRAY_SIZE(rcrtc->group->planes.planes); ++i) {
243 struct rcar_du_plane *plane = &rcrtc->group->planes.planes[i];
245 if (plane->crtc != crtc || !plane->enabled)
248 rcar_du_plane_setup(plane);
251 /* Select master sync mode. This enables display operation in master
252 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
255 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_MASTER);
257 rcar_du_group_start_stop(rcrtc->group, true);
259 rcrtc->started = true;
262 static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
264 struct drm_crtc *crtc = &rcrtc->crtc;
269 mutex_lock(&rcrtc->group->planes.lock);
270 rcrtc->plane->enabled = false;
271 rcar_du_crtc_update_planes(crtc);
272 mutex_unlock(&rcrtc->group->planes.lock);
274 /* Select switch sync mode. This stops display operation and configures
275 * the HSYNC and VSYNC signals as inputs.
277 rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
279 rcar_du_group_start_stop(rcrtc->group, false);
281 rcrtc->started = false;
284 void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
286 rcar_du_crtc_stop(rcrtc);
287 rcar_du_crtc_put(rcrtc);
290 void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
292 if (rcrtc->dpms != DRM_MODE_DPMS_ON)
295 rcar_du_crtc_get(rcrtc);
296 rcar_du_crtc_start(rcrtc);
299 static void rcar_du_crtc_update_base(struct rcar_du_crtc *rcrtc)
301 struct drm_crtc *crtc = &rcrtc->crtc;
303 rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
304 rcar_du_plane_update_base(rcrtc->plane);
307 static void rcar_du_crtc_dpms(struct drm_crtc *crtc, int mode)
309 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
311 if (rcrtc->dpms == mode)
314 if (mode == DRM_MODE_DPMS_ON) {
315 rcar_du_crtc_get(rcrtc);
316 rcar_du_crtc_start(rcrtc);
318 rcar_du_crtc_stop(rcrtc);
319 rcar_du_crtc_put(rcrtc);
325 static bool rcar_du_crtc_mode_fixup(struct drm_crtc *crtc,
326 const struct drm_display_mode *mode,
327 struct drm_display_mode *adjusted_mode)
329 /* TODO Fixup modes */
333 static void rcar_du_crtc_mode_prepare(struct drm_crtc *crtc)
335 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
337 /* We need to access the hardware during mode set, acquire a reference
340 rcar_du_crtc_get(rcrtc);
342 /* Stop the CRTC and release the plane. Force the DPMS mode to off as a
345 rcar_du_crtc_stop(rcrtc);
346 rcar_du_plane_release(rcrtc->plane);
348 rcrtc->dpms = DRM_MODE_DPMS_OFF;
351 static int rcar_du_crtc_mode_set(struct drm_crtc *crtc,
352 struct drm_display_mode *mode,
353 struct drm_display_mode *adjusted_mode,
355 struct drm_framebuffer *old_fb)
357 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
358 struct rcar_du_device *rcdu = rcrtc->group->dev;
359 const struct rcar_du_format_info *format;
362 format = rcar_du_format_info(crtc->primary->fb->pixel_format);
363 if (format == NULL) {
364 dev_dbg(rcdu->dev, "mode_set: unsupported format %08x\n",
365 crtc->primary->fb->pixel_format);
370 ret = rcar_du_plane_reserve(rcrtc->plane, format);
374 rcrtc->plane->format = format;
376 rcrtc->plane->src_x = x;
377 rcrtc->plane->src_y = y;
378 rcrtc->plane->width = mode->hdisplay;
379 rcrtc->plane->height = mode->vdisplay;
381 rcar_du_plane_compute_base(rcrtc->plane, crtc->primary->fb);
388 /* There's no rollback/abort operation to clean up in case of error. We
389 * thus need to release the reference to the CRTC acquired in prepare()
392 rcar_du_crtc_put(rcrtc);
396 static void rcar_du_crtc_mode_commit(struct drm_crtc *crtc)
398 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
400 /* We're done, restart the CRTC and set the DPMS mode to on. The
401 * reference to the DU acquired at prepare() time will thus be released
402 * by the DPMS handler (possibly called by the disable() handler).
404 rcar_du_crtc_start(rcrtc);
405 rcrtc->dpms = DRM_MODE_DPMS_ON;
408 static int rcar_du_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
409 struct drm_framebuffer *old_fb)
411 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
413 rcrtc->plane->src_x = x;
414 rcrtc->plane->src_y = y;
416 rcar_du_crtc_update_base(rcrtc);
421 static void rcar_du_crtc_disable(struct drm_crtc *crtc)
423 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
425 rcar_du_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
426 rcar_du_plane_release(rcrtc->plane);
429 static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
430 .dpms = rcar_du_crtc_dpms,
431 .mode_fixup = rcar_du_crtc_mode_fixup,
432 .prepare = rcar_du_crtc_mode_prepare,
433 .commit = rcar_du_crtc_mode_commit,
434 .mode_set = rcar_du_crtc_mode_set,
435 .mode_set_base = rcar_du_crtc_mode_set_base,
436 .disable = rcar_du_crtc_disable,
439 void rcar_du_crtc_cancel_page_flip(struct rcar_du_crtc *rcrtc,
440 struct drm_file *file)
442 struct drm_pending_vblank_event *event;
443 struct drm_device *dev = rcrtc->crtc.dev;
446 /* Destroy the pending vertical blanking event associated with the
447 * pending page flip, if any, and disable vertical blanking interrupts.
449 spin_lock_irqsave(&dev->event_lock, flags);
450 event = rcrtc->event;
451 if (event && event->base.file_priv == file) {
453 event->base.destroy(&event->base);
454 drm_vblank_put(dev, rcrtc->index);
456 spin_unlock_irqrestore(&dev->event_lock, flags);
459 static void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
461 struct drm_pending_vblank_event *event;
462 struct drm_device *dev = rcrtc->crtc.dev;
465 spin_lock_irqsave(&dev->event_lock, flags);
466 event = rcrtc->event;
468 spin_unlock_irqrestore(&dev->event_lock, flags);
473 spin_lock_irqsave(&dev->event_lock, flags);
474 drm_send_vblank_event(dev, rcrtc->index, event);
475 spin_unlock_irqrestore(&dev->event_lock, flags);
477 drm_vblank_put(dev, rcrtc->index);
480 static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
482 struct rcar_du_crtc *rcrtc = arg;
483 irqreturn_t ret = IRQ_NONE;
486 status = rcar_du_crtc_read(rcrtc, DSSR);
487 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
489 if (status & DSSR_VBK) {
490 drm_handle_vblank(rcrtc->crtc.dev, rcrtc->index);
491 rcar_du_crtc_finish_page_flip(rcrtc);
498 static int rcar_du_crtc_page_flip(struct drm_crtc *crtc,
499 struct drm_framebuffer *fb,
500 struct drm_pending_vblank_event *event,
501 uint32_t page_flip_flags)
503 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
504 struct drm_device *dev = rcrtc->crtc.dev;
507 spin_lock_irqsave(&dev->event_lock, flags);
508 if (rcrtc->event != NULL) {
509 spin_unlock_irqrestore(&dev->event_lock, flags);
512 spin_unlock_irqrestore(&dev->event_lock, flags);
514 crtc->primary->fb = fb;
515 rcar_du_crtc_update_base(rcrtc);
518 event->pipe = rcrtc->index;
519 drm_vblank_get(dev, rcrtc->index);
520 spin_lock_irqsave(&dev->event_lock, flags);
521 rcrtc->event = event;
522 spin_unlock_irqrestore(&dev->event_lock, flags);
528 static const struct drm_crtc_funcs crtc_funcs = {
529 .destroy = drm_crtc_cleanup,
530 .set_config = drm_crtc_helper_set_config,
531 .page_flip = rcar_du_crtc_page_flip,
534 int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
536 static const unsigned int mmio_offsets[] = {
537 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
540 struct rcar_du_device *rcdu = rgrp->dev;
541 struct platform_device *pdev = to_platform_device(rcdu->dev);
542 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[index];
543 struct drm_crtc *crtc = &rcrtc->crtc;
544 unsigned int irqflags;
550 /* Get the CRTC clock. */
551 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
552 sprintf(clk_name, "du.%u", index);
558 rcrtc->clock = devm_clk_get(rcdu->dev, name);
559 if (IS_ERR(rcrtc->clock)) {
560 dev_err(rcdu->dev, "no clock for CRTC %u\n", index);
561 return PTR_ERR(rcrtc->clock);
565 rcrtc->mmio_offset = mmio_offsets[index];
566 rcrtc->index = index;
567 rcrtc->dpms = DRM_MODE_DPMS_OFF;
568 rcrtc->plane = &rgrp->planes.planes[index % 2];
570 rcrtc->plane->crtc = crtc;
572 ret = drm_crtc_init(rcdu->ddev, crtc, &crtc_funcs);
576 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
578 /* Register the interrupt handler. */
579 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ_CLOCK)) {
580 irq = platform_get_irq(pdev, index);
583 irq = platform_get_irq(pdev, 0);
584 irqflags = IRQF_SHARED;
588 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", index);
592 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
593 dev_name(rcdu->dev), rcrtc);
596 "failed to register IRQ for CRTC %u\n", index);
603 void rcar_du_crtc_enable_vblank(struct rcar_du_crtc *rcrtc, bool enable)
606 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
607 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
609 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);