drivers/gpu/drm/sti/sti_hqvdp.c

   1 /*
   2  * Copyright (C) STMicroelectronics SA 2014
   3  * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
   4  * License terms:  GNU General Public License (GPL), version 2
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/component.h>
   9 #include <linux/firmware.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/reset.h>
  13
  14 #include <drm/drmP.h>
  15
  16 #include "sti_hqvdp_lut.h"
  17 #include "sti_plane.h"
  18 #include "sti_vtg.h"
  19
  20 /* Firmware name */
  21 #define HQVDP_FMW_NAME          "hqvdp-stih407.bin"
  22
  23 /* Regs address */
  24 #define HQVDP_DMEM              0x00000000               /* 0x00000000 */
  25 #define HQVDP_PMEM              0x00040000               /* 0x00040000 */
  26 #define HQVDP_RD_PLUG           0x000E0000               /* 0x000E0000 */
  27 #define HQVDP_RD_PLUG_CONTROL   (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
  28 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
  29 #define HQVDP_RD_PLUG_MIN_OPC   (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
  30 #define HQVDP_RD_PLUG_MAX_OPC   (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
  31 #define HQVDP_RD_PLUG_MAX_CHK   (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
  32 #define HQVDP_RD_PLUG_MAX_MSG   (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
  33 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
  34 #define HQVDP_WR_PLUG           0x000E2000               /* 0x000E2000 */
  35 #define HQVDP_WR_PLUG_CONTROL   (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
  36 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
  37 #define HQVDP_WR_PLUG_MIN_OPC   (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
  38 #define HQVDP_WR_PLUG_MAX_OPC   (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
  39 #define HQVDP_WR_PLUG_MAX_CHK   (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
  40 #define HQVDP_WR_PLUG_MAX_MSG   (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
  41 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
  42 #define HQVDP_MBX               0x000E4000               /* 0x000E4000 */
  43 #define HQVDP_MBX_IRQ_TO_XP70   (HQVDP_MBX + 0x0000)     /* 0x000E4000 */
  44 #define HQVDP_MBX_INFO_HOST     (HQVDP_MBX + 0x0004)     /* 0x000E4004 */
  45 #define HQVDP_MBX_IRQ_TO_HOST   (HQVDP_MBX + 0x0008)     /* 0x000E4008 */
  46 #define HQVDP_MBX_INFO_XP70     (HQVDP_MBX + 0x000C)     /* 0x000E400C */
  47 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010)     /* 0x000E4010 */
  48 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014)     /* 0x000E4014 */
  49 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018)     /* 0x000E4018 */
  50 #define HQVDP_MBX_GP_STATUS     (HQVDP_MBX + 0x001C)     /* 0x000E401C */
  51 #define HQVDP_MBX_NEXT_CMD      (HQVDP_MBX + 0x0020)     /* 0x000E4020 */
  52 #define HQVDP_MBX_CURRENT_CMD   (HQVDP_MBX + 0x0024)     /* 0x000E4024 */
  53 #define HQVDP_MBX_SOFT_VSYNC    (HQVDP_MBX + 0x0028)     /* 0x000E4028 */
  54
  55 /* Plugs config */
  56 #define PLUG_CONTROL_ENABLE     0x00000001
  57 #define PLUG_PAGE_SIZE_256      0x00000002
  58 #define PLUG_MIN_OPC_8          0x00000003
  59 #define PLUG_MAX_OPC_64         0x00000006
  60 #define PLUG_MAX_CHK_2X         0x00000001
  61 #define PLUG_MAX_MSG_1X         0x00000000
  62 #define PLUG_MIN_SPACE_1        0x00000000
  63
  64 /* SW reset CTRL */
  65 #define SW_RESET_CTRL_FULL      BIT(0)
  66 #define SW_RESET_CTRL_CORE      BIT(1)
  67
  68 /* Startup ctrl 1 */
  69 #define STARTUP_CTRL1_RST_DONE  BIT(0)
  70 #define STARTUP_CTRL1_AUTH_IDLE BIT(2)
  71
  72 /* Startup ctrl 2 */
  73 #define STARTUP_CTRL2_FETCH_EN  BIT(1)
  74
  75 /* Info xP70 */
  76 #define INFO_XP70_FW_READY      BIT(15)
  77 #define INFO_XP70_FW_PROCESSING BIT(14)
  78 #define INFO_XP70_FW_INITQUEUES BIT(13)
  79
  80 /* SOFT_VSYNC */
  81 #define SOFT_VSYNC_HW           0x00000000
  82 #define SOFT_VSYNC_SW_CMD       0x00000001
  83 #define SOFT_VSYNC_SW_CTRL_IRQ  0x00000003
  84
  85 /* Reset & boot poll config */
  86 #define POLL_MAX_ATTEMPT        50
  87 #define POLL_DELAY_MS           20
  88
  89 #define SCALE_FACTOR            8192
  90 #define SCALE_MAX_FOR_LEG_LUT_F 4096
  91 #define SCALE_MAX_FOR_LEG_LUT_E 4915
  92 #define SCALE_MAX_FOR_LEG_LUT_D 6654
  93 #define SCALE_MAX_FOR_LEG_LUT_C 8192
  94
  95 enum sti_hvsrc_orient {
  96         HVSRC_HORI,
  97         HVSRC_VERT
  98 };
  99
 100 /* Command structures */
 101 struct sti_hqvdp_top {
 102         u32 config;
 103         u32 mem_format;
 104         u32 current_luma;
 105         u32 current_enh_luma;
 106         u32 current_right_luma;
 107         u32 current_enh_right_luma;
 108         u32 current_chroma;
 109         u32 current_enh_chroma;
 110         u32 current_right_chroma;
 111         u32 current_enh_right_chroma;
 112         u32 output_luma;
 113         u32 output_chroma;
 114         u32 luma_src_pitch;
 115         u32 luma_enh_src_pitch;
 116         u32 luma_right_src_pitch;
 117         u32 luma_enh_right_src_pitch;
 118         u32 chroma_src_pitch;
 119         u32 chroma_enh_src_pitch;
 120         u32 chroma_right_src_pitch;
 121         u32 chroma_enh_right_src_pitch;
 122         u32 luma_processed_pitch;
 123         u32 chroma_processed_pitch;
 124         u32 input_frame_size;
 125         u32 input_viewport_ori;
 126         u32 input_viewport_ori_right;
 127         u32 input_viewport_size;
 128         u32 left_view_border_width;
 129         u32 right_view_border_width;
 130         u32 left_view_3d_offset_width;
 131         u32 right_view_3d_offset_width;
 132         u32 side_stripe_color;
 133         u32 crc_reset_ctrl;
 134 };
 135
 136 /* Configs for interlaced : no IT, no pass thru, 3 fields */
 137 #define TOP_CONFIG_INTER_BTM            0x00000000
 138 #define TOP_CONFIG_INTER_TOP            0x00000002
 139
 140 /* Config for progressive : no IT, no pass thru, 3 fields */
 141 #define TOP_CONFIG_PROGRESSIVE          0x00000001
 142
 143 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
 144 #define TOP_MEM_FORMAT_DFLT             0x00018060
 145
 146 /* Min/Max size */
 147 #define MAX_WIDTH                       0x1FFF
 148 #define MAX_HEIGHT                      0x0FFF
 149 #define MIN_WIDTH                       0x0030
 150 #define MIN_HEIGHT                      0x0010
 151
 152 struct sti_hqvdp_vc1re {
 153         u32 ctrl_prv_csdi;
 154         u32 ctrl_cur_csdi;
 155         u32 ctrl_nxt_csdi;
 156         u32 ctrl_cur_fmd;
 157         u32 ctrl_nxt_fmd;
 158 };
 159
 160 struct sti_hqvdp_fmd {
 161         u32 config;
 162         u32 viewport_ori;
 163         u32 viewport_size;
 164         u32 next_next_luma;
 165         u32 next_next_right_luma;
 166         u32 next_next_next_luma;
 167         u32 next_next_next_right_luma;
 168         u32 threshold_scd;
 169         u32 threshold_rfd;
 170         u32 threshold_move;
 171         u32 threshold_cfd;
 172 };
 173
 174 struct sti_hqvdp_csdi {
 175         u32 config;
 176         u32 config2;
 177         u32 dcdi_config;
 178         u32 prev_luma;
 179         u32 prev_enh_luma;
 180         u32 prev_right_luma;
 181         u32 prev_enh_right_luma;
 182         u32 next_luma;
 183         u32 next_enh_luma;
 184         u32 next_right_luma;
 185         u32 next_enh_right_luma;
 186         u32 prev_chroma;
 187         u32 prev_enh_chroma;
 188         u32 prev_right_chroma;
 189         u32 prev_enh_right_chroma;
 190         u32 next_chroma;
 191         u32 next_enh_chroma;
 192         u32 next_right_chroma;
 193         u32 next_enh_right_chroma;
 194         u32 prev_motion;
 195         u32 prev_right_motion;
 196         u32 cur_motion;
 197         u32 cur_right_motion;
 198         u32 next_motion;
 199         u32 next_right_motion;
 200 };
 201
 202 /* Config for progressive: by pass */
 203 #define CSDI_CONFIG_PROG                0x00000000
 204 /* Config for directional deinterlacing without motion */
 205 #define CSDI_CONFIG_INTER_DIR           0x00000016
 206 /* Additional configs for fader, blender, motion,... deinterlace algorithms */
 207 #define CSDI_CONFIG2_DFLT               0x000001B3
 208 #define CSDI_DCDI_CONFIG_DFLT           0x00203803
 209
 210 struct sti_hqvdp_hvsrc {
 211         u32 hor_panoramic_ctrl;
 212         u32 output_picture_size;
 213         u32 init_horizontal;
 214         u32 init_vertical;
 215         u32 param_ctrl;
 216         u32 yh_coef[NB_COEF];
 217         u32 ch_coef[NB_COEF];
 218         u32 yv_coef[NB_COEF];
 219         u32 cv_coef[NB_COEF];
 220         u32 hori_shift;
 221         u32 vert_shift;
 222 };
 223
 224 /* Default ParamCtrl: all controls enabled */
 225 #define HVSRC_PARAM_CTRL_DFLT           0xFFFFFFFF
 226
 227 struct sti_hqvdp_iqi {
 228         u32 config;
 229         u32 demo_wind_size;
 230         u32 pk_config;
 231         u32 coeff0_coeff1;
 232         u32 coeff2_coeff3;
 233         u32 coeff4;
 234         u32 pk_lut;
 235         u32 pk_gain;
 236         u32 pk_coring_level;
 237         u32 cti_config;
 238         u32 le_config;
 239         u32 le_lut[64];
 240         u32 con_bri;
 241         u32 sat_gain;
 242         u32 pxf_conf;
 243         u32 default_color;
 244 };
 245
 246 /* Default Config : IQI bypassed */
 247 #define IQI_CONFIG_DFLT                 0x00000001
 248 /* Default Contrast & Brightness gain = 256 */
 249 #define IQI_CON_BRI_DFLT                0x00000100
 250 /* Default Saturation gain = 256 */
 251 #define IQI_SAT_GAIN_DFLT               0x00000100
 252 /* Default PxfConf : P2I bypassed */
 253 #define IQI_PXF_CONF_DFLT               0x00000001
 254
 255 struct sti_hqvdp_top_status {
 256         u32 processing_time;
 257         u32 input_y_crc;
 258         u32 input_uv_crc;
 259 };
 260
 261 struct sti_hqvdp_fmd_status {
 262         u32 fmd_repeat_move_status;
 263         u32 fmd_scene_count_status;
 264         u32 cfd_sum;
 265         u32 field_sum;
 266         u32 next_y_fmd_crc;
 267         u32 next_next_y_fmd_crc;
 268         u32 next_next_next_y_fmd_crc;
 269 };
 270
 271 struct sti_hqvdp_csdi_status {
 272         u32 prev_y_csdi_crc;
 273         u32 cur_y_csdi_crc;
 274         u32 next_y_csdi_crc;
 275         u32 prev_uv_csdi_crc;
 276         u32 cur_uv_csdi_crc;
 277         u32 next_uv_csdi_crc;
 278         u32 y_csdi_crc;
 279         u32 uv_csdi_crc;
 280         u32 uv_cup_crc;
 281         u32 mot_csdi_crc;
 282         u32 mot_cur_csdi_crc;
 283         u32 mot_prev_csdi_crc;
 284 };
 285
 286 struct sti_hqvdp_hvsrc_status {
 287         u32 y_hvsrc_crc;
 288         u32 u_hvsrc_crc;
 289         u32 v_hvsrc_crc;
 290 };
 291
 292 struct sti_hqvdp_iqi_status {
 293         u32 pxf_it_status;
 294         u32 y_iqi_crc;
 295         u32 u_iqi_crc;
 296         u32 v_iqi_crc;
 297 };
 298
 299 /* Main commands. We use 2 commands one being processed by the firmware, one
 300  * ready to be fetched upon next Vsync*/
 301 #define NB_VDP_CMD      2
 302
 303 struct sti_hqvdp_cmd {
 304         struct sti_hqvdp_top top;
 305         struct sti_hqvdp_vc1re vc1re;
 306         struct sti_hqvdp_fmd fmd;
 307         struct sti_hqvdp_csdi csdi;
 308         struct sti_hqvdp_hvsrc hvsrc;
 309         struct sti_hqvdp_iqi iqi;
 310         struct sti_hqvdp_top_status top_status;
 311         struct sti_hqvdp_fmd_status fmd_status;
 312         struct sti_hqvdp_csdi_status csdi_status;
 313         struct sti_hqvdp_hvsrc_status hvsrc_status;
 314         struct sti_hqvdp_iqi_status iqi_status;
 315 };
 316
 317 /*
 318  * STI HQVDP structure
 319  *
 320  * @dev:               driver device
 321  * @drm_dev:           the drm device
 322  * @regs:              registers
 323  * @plane:             plane structure for hqvdp it self
 324  * @clk:               IP clock
 325  * @clk_pix_main:      pix main clock
 326  * @reset:             reset control
 327  * @vtg_nb:            notifier to handle VTG Vsync
 328  * @btm_field_pending: is there any bottom field (interlaced frame) to display
 329  * @curr_field_count:  number of field updates
 330  * @last_field_count:  number of field updates since last fps measure
 331  * @hqvdp_cmd:         buffer of commands
 332  * @hqvdp_cmd_paddr:   physical address of hqvdp_cmd
 333  * @vtg:               vtg for main data path
 334  * @xp70_initialized:  true if xp70 is already initialized
 335  */
 336 struct sti_hqvdp {
 337         struct device *dev;
 338         struct drm_device *drm_dev;
 339         void __iomem *regs;
 340         struct sti_plane plane;
 341         struct clk *clk;
 342         struct clk *clk_pix_main;
 343         struct reset_control *reset;
 344         struct notifier_block vtg_nb;
 345         bool btm_field_pending;
 346         unsigned int curr_field_count;
 347         unsigned int last_field_count;
 348         void *hqvdp_cmd;
 349         dma_addr_t hqvdp_cmd_paddr;
 350         struct sti_vtg *vtg;
 351         bool xp70_initialized;
 352 };
 353
 354 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
 355
 356 static const uint32_t hqvdp_supported_formats[] = {
 357         DRM_FORMAT_NV12,
 358 };
 359
 360 static const uint32_t *sti_hqvdp_get_formats(struct sti_plane *plane)
 361 {
 362         return hqvdp_supported_formats;
 363 }
 364
 365 static unsigned int sti_hqvdp_get_nb_formats(struct sti_plane *plane)
 366 {
 367         return ARRAY_SIZE(hqvdp_supported_formats);
 368 }
 369
 370 /**
 371  * sti_hqvdp_get_free_cmd
 372  * @hqvdp: hqvdp structure
 373  *
 374  * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
 375  *
 376  * RETURNS:
 377  * the offset of the command to be used.
 378  * -1 in error cases
 379  */
 380 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp)
 381 {
 382         int curr_cmd, next_cmd;
 383         dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
 384         int i;
 385
 386         curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
 387         next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 388
 389         for (i = 0; i < NB_VDP_CMD; i++) {
 390                 if ((cmd != curr_cmd) && (cmd != next_cmd))
 391                         return i * sizeof(struct sti_hqvdp_cmd);
 392                 cmd += sizeof(struct sti_hqvdp_cmd);
 393         }
 394
 395         return -1;
 396 }
 397
 398 /**
 399  * sti_hqvdp_get_curr_cmd
 400  * @hqvdp: hqvdp structure
 401  *
 402  * Look for the hqvdp_cmd that is being used by the FW.
 403  *
 404  * RETURNS:
 405  *  the offset of the command to be used.
 406  * -1 in error cases
 407  */
 408 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp)
 409 {
 410         int curr_cmd;
 411         dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
 412         unsigned int i;
 413
 414         curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
 415
 416         for (i = 0; i < NB_VDP_CMD; i++) {
 417                 if (cmd == curr_cmd)
 418                         return i * sizeof(struct sti_hqvdp_cmd);
 419
 420                 cmd += sizeof(struct sti_hqvdp_cmd);
 421         }
 422
 423         return -1;
 424 }
 425
 426 /**
 427  * sti_hqvdp_update_hvsrc
 428  * @orient: horizontal or vertical
 429  * @scale:  scaling/zoom factor
 430  * @hvsrc:  the structure containing the LUT coef
 431  *
 432  * Update the Y and C Lut coef, as well as the shift param
 433  *
 434  * RETURNS:
 435  * None.
 436  */
 437 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale,
 438                 struct sti_hqvdp_hvsrc *hvsrc)
 439 {
 440         const int *coef_c, *coef_y;
 441         int shift_c, shift_y;
 442
 443         /* Get the appropriate coef tables */
 444         if (scale < SCALE_MAX_FOR_LEG_LUT_F) {
 445                 coef_y = coef_lut_f_y_legacy;
 446                 coef_c = coef_lut_f_c_legacy;
 447                 shift_y = SHIFT_LUT_F_Y_LEGACY;
 448                 shift_c = SHIFT_LUT_F_C_LEGACY;
 449         } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) {
 450                 coef_y = coef_lut_e_y_legacy;
 451                 coef_c = coef_lut_e_c_legacy;
 452                 shift_y = SHIFT_LUT_E_Y_LEGACY;
 453                 shift_c = SHIFT_LUT_E_C_LEGACY;
 454         } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) {
 455                 coef_y = coef_lut_d_y_legacy;
 456                 coef_c = coef_lut_d_c_legacy;
 457                 shift_y = SHIFT_LUT_D_Y_LEGACY;
 458                 shift_c = SHIFT_LUT_D_C_LEGACY;
 459         } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) {
 460                 coef_y = coef_lut_c_y_legacy;
 461                 coef_c = coef_lut_c_c_legacy;
 462                 shift_y = SHIFT_LUT_C_Y_LEGACY;
 463                 shift_c = SHIFT_LUT_C_C_LEGACY;
 464         } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) {
 465                 coef_y = coef_c = coef_lut_b;
 466                 shift_y = shift_c = SHIFT_LUT_B;
 467         } else {
 468                 coef_y = coef_c = coef_lut_a_legacy;
 469                 shift_y = shift_c = SHIFT_LUT_A_LEGACY;
 470         }
 471
 472         if (orient == HVSRC_HORI) {
 473                 hvsrc->hori_shift = (shift_c << 16) | shift_y;
 474                 memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef));
 475                 memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef));
 476         } else {
 477                 hvsrc->vert_shift = (shift_c << 16) | shift_y;
 478                 memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef));
 479                 memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef));
 480         }
 481 }
 482
 483 /**
 484  * sti_hqvdp_check_hw_scaling
 485  * @plane: hqvdp plane
 486  *
 487  * Check if the HW is able to perform the scaling request
 488  * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
 489  *   Zy = OutputHeight / InputHeight
 490  *   LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
 491  *     Tx : Total video mode horizontal resolution
 492  *     IPClock : HQVDP IP clock (Mhz)
 493  *     MaxNbCycles: max(InputWidth, OutputWidth)
 494  *     Cp: Video mode pixel clock (Mhz)
 495  *
 496  * RETURNS:
 497  * True if the HW can scale.
 498  */
 499 static bool sti_hqvdp_check_hw_scaling(struct sti_plane *plane)
 500 {
 501         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
 502         unsigned long lfw;
 503         unsigned int inv_zy;
 504
 505         lfw = plane->mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000);
 506         lfw /= max(plane->src_w, plane->dst_w) * plane->mode->clock / 1000;
 507
 508         inv_zy = DIV_ROUND_UP(plane->src_h, plane->dst_h);
 509
 510         return (inv_zy <= lfw) ? true : false;
 511 }
 512
 513 /**
 514  * sti_hqvdp_prepare
 515  * @plane: hqvdp plane
 516  * @first_prepare: true if it is the first time this function is called
 517  *
 518  * Prepares a command for the firmware
 519  *
 520  * RETURNS:
 521  * 0 on success.
 522  */
 523 static int sti_hqvdp_prepare(struct sti_plane *plane, bool first_prepare)
 524 {
 525         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
 526         struct sti_hqvdp_cmd *cmd;
 527         int scale_h, scale_v;
 528         int cmd_offset;
 529
 530         dev_dbg(hqvdp->dev, "%s %s\n", __func__, sti_plane_to_str(plane));
 531
 532         cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
 533         if (cmd_offset == -1) {
 534                 DRM_ERROR("No available hqvdp_cmd now\n");
 535                 return -EBUSY;
 536         }
 537         cmd = hqvdp->hqvdp_cmd + cmd_offset;
 538
 539         if (!sti_hqvdp_check_hw_scaling(plane)) {
 540                 DRM_ERROR("Scaling beyond HW capabilities\n");
 541                 return -EINVAL;
 542         }
 543
 544         /* Static parameters, defaulting to progressive mode */
 545         cmd->top.config = TOP_CONFIG_PROGRESSIVE;
 546         cmd->top.mem_format = TOP_MEM_FORMAT_DFLT;
 547         cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT;
 548         cmd->csdi.config = CSDI_CONFIG_PROG;
 549
 550         /* VC1RE, FMD bypassed : keep everything set to 0
 551          * IQI/P2I bypassed */
 552         cmd->iqi.config = IQI_CONFIG_DFLT;
 553         cmd->iqi.con_bri = IQI_CON_BRI_DFLT;
 554         cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT;
 555         cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT;
 556
 557         /* Buffer planes address */
 558         cmd->top.current_luma = (u32)plane->paddr + plane->offsets[0];
 559         cmd->top.current_chroma = (u32)plane->paddr + plane->offsets[1];
 560
 561         /* Pitches */
 562         cmd->top.luma_processed_pitch = cmd->top.luma_src_pitch =
 563                         plane->pitches[0];
 564         cmd->top.chroma_processed_pitch = cmd->top.chroma_src_pitch =
 565                         plane->pitches[1];
 566
 567         /* Input / output size
 568          * Align to upper even value */
 569         plane->dst_w = ALIGN(plane->dst_w, 2);
 570         plane->dst_h = ALIGN(plane->dst_h, 2);
 571
 572         if ((plane->src_w > MAX_WIDTH) || (plane->src_w < MIN_WIDTH) ||
 573             (plane->src_h > MAX_HEIGHT) || (plane->src_h < MIN_HEIGHT) ||
 574             (plane->dst_w > MAX_WIDTH) || (plane->dst_w < MIN_WIDTH) ||
 575             (plane->dst_h > MAX_HEIGHT) || (plane->dst_h < MIN_HEIGHT)) {
 576                 DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
 577                                 plane->src_w, plane->src_h,
 578                                 plane->dst_w, plane->dst_h);
 579                 return -EINVAL;
 580         }
 581         cmd->top.input_viewport_size = cmd->top.input_frame_size =
 582                         plane->src_h << 16 | plane->src_w;
 583         cmd->hvsrc.output_picture_size = plane->dst_h << 16 | plane->dst_w;
 584         cmd->top.input_viewport_ori = plane->src_y << 16 | plane->src_x;
 585
 586         /* Handle interlaced */
 587         if (plane->fb->flags & DRM_MODE_FB_INTERLACED) {
 588                 /* Top field to display */
 589                 cmd->top.config = TOP_CONFIG_INTER_TOP;
 590
 591                 /* Update pitches and vert size */
 592                 cmd->top.input_frame_size = (plane->src_h / 2) << 16 |
 593                                              plane->src_w;
 594                 cmd->top.luma_processed_pitch *= 2;
 595                 cmd->top.luma_src_pitch *= 2;
 596                 cmd->top.chroma_processed_pitch *= 2;
 597                 cmd->top.chroma_src_pitch *= 2;
 598
 599                 /* Enable directional deinterlacing processing */
 600                 cmd->csdi.config = CSDI_CONFIG_INTER_DIR;
 601                 cmd->csdi.config2 = CSDI_CONFIG2_DFLT;
 602                 cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT;
 603         }
 604
 605         /* Update hvsrc lut coef */
 606         scale_h = SCALE_FACTOR * plane->dst_w / plane->src_w;
 607         sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc);
 608
 609         scale_v = SCALE_FACTOR * plane->dst_h / plane->src_h;
 610         sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc);
 611
 612         if (first_prepare) {
 613                 /* Prevent VTG shutdown */
 614                 if (clk_prepare_enable(hqvdp->clk_pix_main)) {
 615                         DRM_ERROR("Failed to prepare/enable pix main clk\n");
 616                         return -ENXIO;
 617                 }
 618
 619                 /* Register VTG Vsync callback to handle bottom fields */
 620                 if ((plane->fb->flags & DRM_MODE_FB_INTERLACED) &&
 621                     sti_vtg_register_client(hqvdp->vtg, &hqvdp->vtg_nb,
 622                                             plane->mixer_id)) {
 623                         DRM_ERROR("Cannot register VTG notifier\n");
 624                         return -ENXIO;
 625                 }
 626         }
 627
 628         return 0;
 629 }
 630
 631 /**
 632  * sti_hqvdp_commit
 633  * @plane: hqvdp plane
 634  *
 635  * Enables the HQVDP plane
 636  *
 637  * RETURNS:
 638  * 0 on success.
 639  */
 640 static int sti_hqvdp_commit(struct sti_plane *plane)
 641 {
 642         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
 643         int cmd_offset;
 644
 645         dev_dbg(hqvdp->dev, "%s %s\n", __func__, sti_plane_to_str(plane));
 646
 647         cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
 648         if (cmd_offset == -1) {
 649                 DRM_ERROR("No available hqvdp_cmd now\n");
 650                 return -EBUSY;
 651         }
 652
 653         writel(hqvdp->hqvdp_cmd_paddr + cmd_offset,
 654                         hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 655
 656         hqvdp->curr_field_count++;
 657
 658         /* Interlaced : get ready to display the bottom field at next Vsync */
 659         if (plane->fb->flags & DRM_MODE_FB_INTERLACED)
 660                 hqvdp->btm_field_pending = true;
 661
 662         dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
 663                         __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset);
 664
 665         return 0;
 666 }
 667
 668 /**
 669  * sti_hqvdp_disable
 670  * @plane: hqvdp plane
 671  *
 672  * Disables the HQVDP plane
 673  *
 674  * RETURNS:
 675  * 0 on success.
 676  */
 677 static int sti_hqvdp_disable(struct sti_plane *plane)
 678 {
 679         struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
 680         int i;
 681
 682         DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(plane));
 683
 684         /* Unregister VTG Vsync callback */
 685         if ((plane->fb->flags & DRM_MODE_FB_INTERLACED) &&
 686             sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb))
 687                 DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
 688
 689         /* Set next cmd to NULL */
 690         writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 691
 692         for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
 693                 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
 694                                 & INFO_XP70_FW_READY)
 695                         break;
 696                 msleep(POLL_DELAY_MS);
 697         }
 698
 699         /* VTG can stop now */
 700         clk_disable_unprepare(hqvdp->clk_pix_main);
 701
 702         if (i == POLL_MAX_ATTEMPT) {
 703                 DRM_ERROR("XP70 could not revert to idle\n");
 704                 return -ENXIO;
 705         }
 706
 707         return 0;
 708 }
 709
 710 /**
 711  * sti_vdp_vtg_cb
 712  * @nb: notifier block
 713  * @evt: event message
 714  * @data: private data
 715  *
 716  * Handle VTG Vsync event, display pending bottom field
 717  *
 718  * RETURNS:
 719  * 0 on success.
 720  */
 721 int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
 722 {
 723         struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb);
 724         int btm_cmd_offset, top_cmd_offest;
 725         struct sti_hqvdp_cmd *btm_cmd, *top_cmd;
 726
 727         if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) {
 728                 DRM_DEBUG_DRIVER("Unknown event\n");
 729                 return 0;
 730         }
 731
 732         if (hqvdp->btm_field_pending) {
 733                 /* Create the btm field command from the current one */
 734                 btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
 735                 top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp);
 736                 if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) {
 737                         DRM_ERROR("Cannot get cmds, skip btm field\n");
 738                         return -EBUSY;
 739                 }
 740
 741                 btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset;
 742                 top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest;
 743
 744                 memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd));
 745
 746                 btm_cmd->top.config = TOP_CONFIG_INTER_BTM;
 747                 btm_cmd->top.current_luma +=
 748                                 btm_cmd->top.luma_src_pitch / 2;
 749                 btm_cmd->top.current_chroma +=
 750                                 btm_cmd->top.chroma_src_pitch / 2;
 751
 752                 /* Post the command to mailbox */
 753                 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset,
 754                                 hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 755
 756                 hqvdp->curr_field_count++;
 757                 hqvdp->btm_field_pending = false;
 758
 759                 dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
 760                                 __func__, hqvdp->hqvdp_cmd_paddr);
 761         }
 762
 763         return 0;
 764 }
 765
 766 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp)
 767 {
 768         int size;
 769
 770         hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb;
 771
 772         /* Allocate memory for the VDP commands */
 773         size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd);
 774         hqvdp->hqvdp_cmd = dma_alloc_writecombine(hqvdp->dev, size,
 775                                          &hqvdp->hqvdp_cmd_paddr,
 776                                          GFP_KERNEL | GFP_DMA);
 777         if (!hqvdp->hqvdp_cmd) {
 778                 DRM_ERROR("Failed to allocate memory for VDP cmd\n");
 779                 return;
 780         }
 781
 782         memset(hqvdp->hqvdp_cmd, 0, size);
 783 }
 784
 785 static const struct sti_plane_funcs hqvdp_plane_ops = {
 786         .get_formats = sti_hqvdp_get_formats,
 787         .get_nb_formats = sti_hqvdp_get_nb_formats,
 788         .prepare = sti_hqvdp_prepare,
 789         .commit = sti_hqvdp_commit,
 790         .disable = sti_hqvdp_disable,
 791 };
 792
 793 struct sti_plane *sti_hqvdp_create(struct device *dev, int desc)
 794 {
 795         struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
 796
 797         hqvdp->plane.desc = desc;
 798         hqvdp->plane.ops = &hqvdp_plane_ops;
 799
 800         sti_hqvdp_init(hqvdp);
 801
 802         return &hqvdp->plane;
 803 }
 804
 805 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp)
 806 {
 807         /* Configure Plugs (same for RD & WR) */
 808         writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE);
 809         writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC);
 810         writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC);
 811         writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK);
 812         writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG);
 813         writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE);
 814         writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL);
 815
 816         writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE);
 817         writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC);
 818         writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC);
 819         writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK);
 820         writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG);
 821         writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE);
 822         writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL);
 823 }
 824
 825 /**
 826  * sti_hqvdp_start_xp70
 827  * @firmware: firmware found
 828  * @ctxt:     hqvdp structure
 829  *
 830  * Run the xP70 initialization sequence
 831  */
 832 static void sti_hqvdp_start_xp70(const struct firmware *firmware, void *ctxt)
 833 {
 834         struct sti_hqvdp *hqvdp = ctxt;
 835         u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem;
 836         u8 *data;
 837         int i;
 838         struct fw_header {
 839                 int rd_size;
 840                 int wr_size;
 841                 int pmem_size;
 842                 int dmem_size;
 843         } *header;
 844
 845         DRM_DEBUG_DRIVER("\n");
 846
 847         if (hqvdp->xp70_initialized) {
 848                 DRM_INFO("HQVDP XP70 already initialized\n");
 849                 return;
 850         }
 851
 852         /* Check firmware parts */
 853         if (!firmware) {
 854                 DRM_ERROR("Firmware not available\n");
 855                 return;
 856         }
 857
 858         header = (struct fw_header *) firmware->data;
 859         if (firmware->size < sizeof(*header)) {
 860                 DRM_ERROR("Invalid firmware size (%d)\n", firmware->size);
 861                 goto out;
 862         }
 863         if ((sizeof(*header) + header->rd_size + header->wr_size +
 864                 header->pmem_size + header->dmem_size) != firmware->size) {
 865                 DRM_ERROR("Invalid fmw structure (%d+%d+%d+%d+%d != %d)\n",
 866                            sizeof(*header), header->rd_size, header->wr_size,
 867                            header->pmem_size, header->dmem_size,
 868                            firmware->size);
 869                 goto out;
 870         }
 871
 872         data = (u8 *) firmware->data;
 873         data += sizeof(*header);
 874         fw_rd_plug = (void *) data;
 875         data += header->rd_size;
 876         fw_wr_plug = (void *) data;
 877         data += header->wr_size;
 878         fw_pmem = (void *) data;
 879         data += header->pmem_size;
 880         fw_dmem = (void *) data;
 881
 882         /* Enable clock */
 883         if (clk_prepare_enable(hqvdp->clk))
 884                 DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
 885
 886         /* Reset */
 887         writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL);
 888
 889         for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
 890                 if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
 891                                 & STARTUP_CTRL1_RST_DONE)
 892                         break;
 893                 msleep(POLL_DELAY_MS);
 894         }
 895         if (i == POLL_MAX_ATTEMPT) {
 896                 DRM_ERROR("Could not reset\n");
 897                 goto out;
 898         }
 899
 900         /* Init Read & Write plugs */
 901         for (i = 0; i < header->rd_size / 4; i++)
 902                 writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4);
 903         for (i = 0; i < header->wr_size / 4; i++)
 904                 writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4);
 905
 906         sti_hqvdp_init_plugs(hqvdp);
 907
 908         /* Authorize Idle Mode */
 909         writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1);
 910
 911         /* Prevent VTG interruption during the boot */
 912         writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
 913         writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
 914
 915         /* Download PMEM & DMEM */
 916         for (i = 0; i < header->pmem_size / 4; i++)
 917                 writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4);
 918         for (i = 0; i < header->dmem_size / 4; i++)
 919                 writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4);
 920
 921         /* Enable fetch */
 922         writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2);
 923
 924         /* Wait end of boot */
 925         for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
 926                 if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
 927                                 & INFO_XP70_FW_READY)
 928                         break;
 929                 msleep(POLL_DELAY_MS);
 930         }
 931         if (i == POLL_MAX_ATTEMPT) {
 932                 DRM_ERROR("Could not boot\n");
 933                 goto out;
 934         }
 935
 936         /* Launch Vsync */
 937         writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
 938
 939         DRM_INFO("HQVDP XP70 initialized\n");
 940
 941         hqvdp->xp70_initialized = true;
 942
 943 out:
 944         release_firmware(firmware);
 945 }
 946
 947 int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
 948 {
 949         struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
 950         struct drm_device *drm_dev = data;
 951         struct sti_plane *plane;
 952         int err;
 953
 954         DRM_DEBUG_DRIVER("\n");
 955
 956         hqvdp->drm_dev = drm_dev;
 957
 958         /* Request for firmware */
 959         err = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
 960                                 HQVDP_FMW_NAME, hqvdp->dev,
 961                                 GFP_KERNEL, hqvdp, sti_hqvdp_start_xp70);
 962         if (err) {
 963                 DRM_ERROR("Can't get HQVDP firmware\n");
 964                 return err;
 965         }
 966
 967         /* Create HQVDP plane once xp70 is initialized */
 968         plane = sti_hqvdp_create(hqvdp->dev, STI_HQVDP_0);
 969         if (plane)
 970                 sti_plane_init(hqvdp->drm_dev, plane, 1,
 971                                DRM_PLANE_TYPE_OVERLAY);
 972         else
 973                 DRM_ERROR("Can't create HQVDP plane\n");
 974
 975         return 0;
 976 }
 977
 978 static void sti_hqvdp_unbind(struct device *dev,
 979                 struct device *master, void *data)
 980 {
 981         /* do nothing */
 982 }
 983
 984 static const struct component_ops sti_hqvdp_ops = {
 985         .bind = sti_hqvdp_bind,
 986         .unbind = sti_hqvdp_unbind,
 987 };
 988
 989 static int sti_hqvdp_probe(struct platform_device *pdev)
 990 {
 991         struct device *dev = &pdev->dev;
 992         struct device_node *vtg_np;
 993         struct sti_hqvdp *hqvdp;
 994         struct resource *res;
 995
 996         DRM_DEBUG_DRIVER("\n");
 997
 998         hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL);
 999         if (!hqvdp) {
1000                 DRM_ERROR("Failed to allocate HQVDP context\n");
1001                 return -ENOMEM;
1002         }
1003
1004         hqvdp->dev = dev;
1005
1006         /* Get Memory resources */
1007         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1008         if (res == NULL) {
1009                 DRM_ERROR("Get memory resource failed\n");
1010                 return -ENXIO;
1011         }
1012         hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res));
1013         if (hqvdp->regs == NULL) {
1014                 DRM_ERROR("Register mapping failed\n");
1015                 return -ENXIO;
1016         }
1017
1018         /* Get clock resources */
1019         hqvdp->clk = devm_clk_get(dev, "hqvdp");
1020         hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main");
1021         if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) {
1022                 DRM_ERROR("Cannot get clocks\n");
1023                 return -ENXIO;
1024         }
1025
1026         /* Get reset resources */
1027         hqvdp->reset = devm_reset_control_get(dev, "hqvdp");
1028         if (!IS_ERR(hqvdp->reset))
1029                 reset_control_deassert(hqvdp->reset);
1030
1031         vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
1032         if (vtg_np)
1033                 hqvdp->vtg = of_vtg_find(vtg_np);
1034
1035         platform_set_drvdata(pdev, hqvdp);
1036
1037         return component_add(&pdev->dev, &sti_hqvdp_ops);
1038 }
1039
1040 static int sti_hqvdp_remove(struct platform_device *pdev)
1041 {
1042         component_del(&pdev->dev, &sti_hqvdp_ops);
1043         return 0;
1044 }
1045
1046 static struct of_device_id hqvdp_of_match[] = {
1047         { .compatible = "st,stih407-hqvdp", },
1048         { /* end node */ }
1049 };
1050 MODULE_DEVICE_TABLE(of, hqvdp_of_match);
1051
1052 struct platform_driver sti_hqvdp_driver = {
1053         .driver = {
1054                 .name = "sti-hqvdp",
1055                 .owner = THIS_MODULE,
1056                 .of_match_table = hqvdp_of_match,
1057         },
1058         .probe = sti_hqvdp_probe,
1059         .remove = sti_hqvdp_remove,
1060 };
1061
1062 module_platform_driver(sti_hqvdp_driver);
1063
1064 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1065 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1066 MODULE_LICENSE("GPL");