drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "drm_flip_work.h"
  19 #include <drm/drm_plane_helper.h>
  20 #include <drm/drm_atomic_helper.h>
  21
  22 #include "tilcdc_drv.h"
  23 #include "tilcdc_regs.h"
  24
  25 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US 1000
  26
  27 struct tilcdc_crtc {
  28         struct drm_crtc base;
  29
  30         struct drm_plane primary;
  31         const struct tilcdc_panel_info *info;
  32         struct drm_pending_vblank_event *event;
  33         int dpms;
  34         wait_queue_head_t frame_done_wq;
  35         bool frame_done;
  36         spinlock_t irq_lock;
  37
  38         ktime_t last_vblank;
  39
  40         struct drm_framebuffer *curr_fb;
  41         struct drm_framebuffer *next_fb;
  42
  43         /* for deferred fb unref's: */
  44         struct drm_flip_work unref_work;
  45
  46         /* Only set if an external encoder is connected */
  47         bool simulate_vesa_sync;
  48
  49         int sync_lost_count;
  50         bool frame_intact;
  51 };
  52 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  53
  54 static void unref_worker(struct drm_flip_work *work, void *val)
  55 {
  56         struct tilcdc_crtc *tilcdc_crtc =
  57                 container_of(work, struct tilcdc_crtc, unref_work);
  58         struct drm_device *dev = tilcdc_crtc->base.dev;
  59
  60         mutex_lock(&dev->mode_config.mutex);
  61         drm_framebuffer_unreference(val);
  62         mutex_unlock(&dev->mode_config.mutex);
  63 }
  64
  65 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
  66 {
  67         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  68         struct drm_device *dev = crtc->dev;
  69         struct drm_gem_cma_object *gem;
  70         unsigned int depth, bpp;
  71         dma_addr_t start, end;
  72
  73         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
  74         gem = drm_fb_cma_get_gem_obj(fb, 0);
  75
  76         start = gem->paddr + fb->offsets[0] +
  77                 crtc->y * fb->pitches[0] +
  78                 crtc->x * bpp / 8;
  79
  80         end = start + (crtc->mode.vdisplay * fb->pitches[0]);
  81
  82         tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
  83         tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end);
  84
  85         if (tilcdc_crtc->curr_fb)
  86                 drm_flip_work_queue(&tilcdc_crtc->unref_work,
  87                         tilcdc_crtc->curr_fb);
  88
  89         tilcdc_crtc->curr_fb = fb;
  90 }
  91
  92 static void reset(struct drm_crtc *crtc)
  93 {
  94         struct drm_device *dev = crtc->dev;
  95         struct tilcdc_drm_private *priv = dev->dev_private;
  96
  97         if (priv->rev != 2)
  98                 return;
  99
 100         tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 101         usleep_range(250, 1000);
 102         tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 103 }
 104
 105 static void start(struct drm_crtc *crtc)
 106 {
 107         struct drm_device *dev = crtc->dev;
 108
 109         reset(crtc);
 110
 111         tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 112         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 113         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 114
 115         drm_crtc_vblank_on(crtc);
 116 }
 117
 118 static void stop(struct drm_crtc *crtc)
 119 {
 120         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 121         struct drm_device *dev = crtc->dev;
 122         struct tilcdc_drm_private *priv = dev->dev_private;
 123
 124         tilcdc_crtc->frame_done = false;
 125         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 126
 127         /*
 128          * if necessary wait for framedone irq which will still come
 129          * before putting things to sleep..
 130          */
 131         if (priv->rev == 2) {
 132                 int ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
 133                                              tilcdc_crtc->frame_done,
 134                                              msecs_to_jiffies(500));
 135                 if (ret == 0)
 136                         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
 137                                 __func__);
 138         }
 139
 140         drm_crtc_vblank_off(crtc);
 141 }
 142
 143 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 144 {
 145         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 146
 147         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 148
 149         of_node_put(crtc->port);
 150         drm_crtc_cleanup(crtc);
 151         drm_flip_work_cleanup(&tilcdc_crtc->unref_work);
 152 }
 153
 154 static int tilcdc_verify_fb(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 155 {
 156         struct drm_device *dev = crtc->dev;
 157         unsigned int depth, bpp;
 158
 159         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 160
 161         if (fb->pitches[0] != crtc->mode.hdisplay * bpp / 8) {
 162                 dev_err(dev->dev,
 163                         "Invalid pitch: fb and crtc widths must be the same");
 164                 return -EINVAL;
 165         }
 166
 167         return 0;
 168 }
 169
 170 int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 171                 struct drm_framebuffer *fb,
 172                 struct drm_pending_vblank_event *event,
 173                 uint32_t page_flip_flags)
 174 {
 175         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 176         struct drm_device *dev = crtc->dev;
 177         int r;
 178         unsigned long flags;
 179
 180         r = tilcdc_verify_fb(crtc, fb);
 181         if (r)
 182                 return r;
 183
 184         if (tilcdc_crtc->event) {
 185                 dev_err(dev->dev, "already pending page flip!\n");
 186                 return -EBUSY;
 187         }
 188
 189         drm_framebuffer_reference(fb);
 190
 191         crtc->primary->fb = fb;
 192
 193         pm_runtime_get_sync(dev->dev);
 194
 195         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 196
 197         if (crtc->hwmode.vrefresh && ktime_to_ns(tilcdc_crtc->last_vblank)) {
 198                 ktime_t next_vblank;
 199                 s64 tdiff;
 200
 201                 next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
 202                         1000000 / crtc->hwmode.vrefresh);
 203
 204                 tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
 205
 206                 if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
 207                         tilcdc_crtc->next_fb = fb;
 208         }
 209
 210         if (tilcdc_crtc->next_fb != fb)
 211                 set_scanout(crtc, fb);
 212
 213         tilcdc_crtc->event = event;
 214
 215         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 216
 217         pm_runtime_put_sync(dev->dev);
 218
 219         return 0;
 220 }
 221
 222 void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
 223 {
 224         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 225         struct drm_device *dev = crtc->dev;
 226         struct tilcdc_drm_private *priv = dev->dev_private;
 227
 228         /* we really only care about on or off: */
 229         if (mode != DRM_MODE_DPMS_ON)
 230                 mode = DRM_MODE_DPMS_OFF;
 231
 232         if (tilcdc_crtc->dpms == mode)
 233                 return;
 234
 235         tilcdc_crtc->dpms = mode;
 236
 237         if (mode == DRM_MODE_DPMS_ON) {
 238                 pm_runtime_get_sync(dev->dev);
 239                 start(crtc);
 240         } else {
 241                 stop(crtc);
 242                 pm_runtime_put_sync(dev->dev);
 243
 244                 if (tilcdc_crtc->next_fb) {
 245                         drm_flip_work_queue(&tilcdc_crtc->unref_work,
 246                                             tilcdc_crtc->next_fb);
 247                         tilcdc_crtc->next_fb = NULL;
 248                 }
 249
 250                 if (tilcdc_crtc->curr_fb) {
 251                         drm_flip_work_queue(&tilcdc_crtc->unref_work,
 252                                             tilcdc_crtc->curr_fb);
 253                         tilcdc_crtc->curr_fb = NULL;
 254                 }
 255
 256                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 257                 tilcdc_crtc->last_vblank = ktime_set(0, 0);
 258         }
 259 }
 260
 261 int tilcdc_crtc_current_dpms_state(struct drm_crtc *crtc)
 262 {
 263         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 264
 265         return tilcdc_crtc->dpms;
 266 }
 267
 268 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 269                 const struct drm_display_mode *mode,
 270                 struct drm_display_mode *adjusted_mode)
 271 {
 272         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 273
 274         if (!tilcdc_crtc->simulate_vesa_sync)
 275                 return true;
 276
 277         /*
 278          * tilcdc does not generate VESA-compliant sync but aligns
 279          * VS on the second edge of HS instead of first edge.
 280          * We use adjusted_mode, to fixup sync by aligning both rising
 281          * edges and add HSKEW offset to fix the sync.
 282          */
 283         adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
 284         adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
 285
 286         if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
 287                 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
 288                 adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
 289         } else {
 290                 adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
 291                 adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
 292         }
 293
 294         return true;
 295 }
 296
 297 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
 298 {
 299         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 300 }
 301
 302 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
 303 {
 304         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 305 }
 306
 307 static void tilcdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 308 {
 309         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 310         struct drm_device *dev = crtc->dev;
 311         struct tilcdc_drm_private *priv = dev->dev_private;
 312         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 313         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 314         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 315         struct drm_framebuffer *fb = crtc->primary->state->fb;
 316
 317         if (WARN_ON(!info))
 318                 return;
 319
 320         if (WARN_ON(!fb))
 321                 return;
 322
 323         pm_runtime_get_sync(dev->dev);
 324
 325         /* Configure the Burst Size and fifo threshold of DMA: */
 326         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 327         switch (info->dma_burst_sz) {
 328         case 1:
 329                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 330                 break;
 331         case 2:
 332                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 333                 break;
 334         case 4:
 335                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 336                 break;
 337         case 8:
 338                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 339                 break;
 340         case 16:
 341                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 342                 break;
 343         default:
 344                 dev_err(dev->dev, "invalid burst size\n");
 345                 return;
 346         }
 347         reg |= (info->fifo_th << 8);
 348         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 349
 350         /* Configure timings: */
 351         hbp = mode->htotal - mode->hsync_end;
 352         hfp = mode->hsync_start - mode->hdisplay;
 353         hsw = mode->hsync_end - mode->hsync_start;
 354         vbp = mode->vtotal - mode->vsync_end;
 355         vfp = mode->vsync_start - mode->vdisplay;
 356         vsw = mode->vsync_end - mode->vsync_start;
 357
 358         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 359             mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 360
 361         /* Set AC Bias Period and Number of Transitions per Interrupt: */
 362         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 363         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 364                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 365
 366         /*
 367          * subtract one from hfp, hbp, hsw because the hardware uses
 368          * a value of 0 as 1
 369          */
 370         if (priv->rev == 2) {
 371                 /* clear bits we're going to set */
 372                 reg &= ~0x78000033;
 373                 reg |= ((hfp-1) & 0x300) >> 8;
 374                 reg |= ((hbp-1) & 0x300) >> 4;
 375                 reg |= ((hsw-1) & 0x3c0) << 21;
 376         }
 377         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 378
 379         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 380                 (((hbp-1) & 0xff) << 24) |
 381                 (((hfp-1) & 0xff) << 16) |
 382                 (((hsw-1) & 0x3f) << 10);
 383         if (priv->rev == 2)
 384                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 385         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 386
 387         reg = ((mode->vdisplay - 1) & 0x3ff) |
 388                 ((vbp & 0xff) << 24) |
 389                 ((vfp & 0xff) << 16) |
 390                 (((vsw-1) & 0x3f) << 10);
 391         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 392
 393         /*
 394          * be sure to set Bit 10 for the V2 LCDC controller,
 395          * otherwise limited to 1024 pixels width, stopping
 396          * 1920x1080 being supported.
 397          */
 398         if (priv->rev == 2) {
 399                 if ((mode->vdisplay - 1) & 0x400) {
 400                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 401                                 LCDC_LPP_B10);
 402                 } else {
 403                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 404                                 LCDC_LPP_B10);
 405                 }
 406         }
 407
 408         /* Configure display type: */
 409         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 410                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 411                   LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
 412                   0x000ff000 /* Palette Loading Delay bits */);
 413         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 414         if (info->tft_alt_mode)
 415                 reg |= LCDC_TFT_ALT_ENABLE;
 416         if (priv->rev == 2) {
 417                 unsigned int depth, bpp;
 418
 419                 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 420                 switch (bpp) {
 421                 case 16:
 422                         break;
 423                 case 32:
 424                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 425                         /* fallthrough */
 426                 case 24:
 427                         reg |= LCDC_V2_TFT_24BPP_MODE;
 428                         break;
 429                 default:
 430                         dev_err(dev->dev, "invalid pixel format\n");
 431                         return;
 432                 }
 433         }
 434         reg |= info->fdd < 12;
 435         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 436
 437         if (info->invert_pxl_clk)
 438                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 439         else
 440                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 441
 442         if (info->sync_ctrl)
 443                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 444         else
 445                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 446
 447         if (info->sync_edge)
 448                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 449         else
 450                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 451
 452         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 453                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 454         else
 455                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 456
 457         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 458                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 459         else
 460                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 461
 462         if (info->raster_order)
 463                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 464         else
 465                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 466
 467         drm_framebuffer_reference(fb);
 468
 469         set_scanout(crtc, fb);
 470
 471         tilcdc_crtc_update_clk(crtc);
 472
 473         pm_runtime_put_sync(dev->dev);
 474
 475         crtc->hwmode = crtc->state->adjusted_mode;
 476 }
 477
 478 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
 479                                     struct drm_crtc_state *state)
 480 {
 481         struct drm_display_mode *mode = &state->mode;
 482         int ret;
 483
 484         /* If we are not active we don't care */
 485         if (!state->active)
 486                 return 0;
 487
 488         if (state->state->planes[0].ptr != crtc->primary ||
 489             state->state->planes[0].state == NULL ||
 490             state->state->planes[0].state->crtc != crtc) {
 491                 dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
 492                 return -EINVAL;
 493         }
 494
 495         ret = tilcdc_crtc_mode_valid(crtc, mode);
 496         if (ret) {
 497                 dev_dbg(crtc->dev->dev, "Mode \"%s\" not valid", mode->name);
 498                 return -EINVAL;
 499         }
 500
 501         return 0;
 502 }
 503
 504 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 505                 struct drm_display_mode *mode,
 506                 struct drm_display_mode *adjusted_mode,
 507                 int x, int y,
 508                 struct drm_framebuffer *old_fb)
 509 {
 510         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 511         struct drm_device *dev = crtc->dev;
 512         struct tilcdc_drm_private *priv = dev->dev_private;
 513         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 514         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 515         int ret;
 516
 517         ret = tilcdc_crtc_mode_valid(crtc, mode);
 518         if (WARN_ON(ret))
 519                 return ret;
 520
 521         if (WARN_ON(!info))
 522                 return -EINVAL;
 523
 524         ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
 525         if (ret)
 526                 return ret;
 527
 528         pm_runtime_get_sync(dev->dev);
 529
 530         /* Configure the Burst Size and fifo threshold of DMA: */
 531         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 532         switch (info->dma_burst_sz) {
 533         case 1:
 534                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 535                 break;
 536         case 2:
 537                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 538                 break;
 539         case 4:
 540                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 541                 break;
 542         case 8:
 543                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 544                 break;
 545         case 16:
 546                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 547                 break;
 548         default:
 549                 return -EINVAL;
 550         }
 551         reg |= (info->fifo_th << 8);
 552         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 553
 554         /* Configure timings: */
 555         hbp = mode->htotal - mode->hsync_end;
 556         hfp = mode->hsync_start - mode->hdisplay;
 557         hsw = mode->hsync_end - mode->hsync_start;
 558         vbp = mode->vtotal - mode->vsync_end;
 559         vfp = mode->vsync_start - mode->vdisplay;
 560         vsw = mode->vsync_end - mode->vsync_start;
 561
 562         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 563                         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 564
 565         /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
 566         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 567         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 568                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 569
 570         /*
 571          * subtract one from hfp, hbp, hsw because the hardware uses
 572          * a value of 0 as 1
 573          */
 574         if (priv->rev == 2) {
 575                 /* clear bits we're going to set */
 576                 reg &= ~0x78000033;
 577                 reg |= ((hfp-1) & 0x300) >> 8;
 578                 reg |= ((hbp-1) & 0x300) >> 4;
 579                 reg |= ((hsw-1) & 0x3c0) << 21;
 580         }
 581         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 582
 583         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 584                 (((hbp-1) & 0xff) << 24) |
 585                 (((hfp-1) & 0xff) << 16) |
 586                 (((hsw-1) & 0x3f) << 10);
 587         if (priv->rev == 2)
 588                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 589         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 590
 591         reg = ((mode->vdisplay - 1) & 0x3ff) |
 592                 ((vbp & 0xff) << 24) |
 593                 ((vfp & 0xff) << 16) |
 594                 (((vsw-1) & 0x3f) << 10);
 595         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 596
 597         /*
 598          * be sure to set Bit 10 for the V2 LCDC controller,
 599          * otherwise limited to 1024 pixels width, stopping
 600          * 1920x1080 being suppoted.
 601          */
 602         if (priv->rev == 2) {
 603                 if ((mode->vdisplay - 1) & 0x400) {
 604                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 605                                 LCDC_LPP_B10);
 606                 } else {
 607                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 608                                 LCDC_LPP_B10);
 609                 }
 610         }
 611
 612         /* Configure display type: */
 613         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 614                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 615                         LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
 616         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 617         if (info->tft_alt_mode)
 618                 reg |= LCDC_TFT_ALT_ENABLE;
 619         if (priv->rev == 2) {
 620                 unsigned int depth, bpp;
 621
 622                 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp);
 623                 switch (bpp) {
 624                 case 16:
 625                         break;
 626                 case 32:
 627                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 628                         /* fallthrough */
 629                 case 24:
 630                         reg |= LCDC_V2_TFT_24BPP_MODE;
 631                         break;
 632                 default:
 633                         dev_err(dev->dev, "invalid pixel format\n");
 634                         return -EINVAL;
 635                 }
 636         }
 637         reg |= info->fdd < 12;
 638         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 639
 640         if (info->invert_pxl_clk)
 641                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 642         else
 643                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 644
 645         if (info->sync_ctrl)
 646                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 647         else
 648                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 649
 650         if (info->sync_edge)
 651                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 652         else
 653                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 654
 655         /*
 656          * use value from adjusted_mode here as this might have been
 657          * changed as part of the fixup for slave encoders to solve the
 658          * issue where tilcdc timings are not VESA compliant
 659          */
 660         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 661                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 662         else
 663                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 664
 665         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 666                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 667         else
 668                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 669
 670         if (info->raster_order)
 671                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 672         else
 673                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 674
 675         drm_framebuffer_reference(crtc->primary->fb);
 676
 677         set_scanout(crtc, crtc->primary->fb);
 678
 679         tilcdc_crtc_update_clk(crtc);
 680
 681         pm_runtime_put_sync(dev->dev);
 682
 683         return 0;
 684 }
 685
 686 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 687                 struct drm_framebuffer *old_fb)
 688 {
 689         struct drm_device *dev = crtc->dev;
 690         int r;
 691
 692         r = tilcdc_verify_fb(crtc, crtc->primary->fb);
 693         if (r)
 694                 return r;
 695
 696         drm_framebuffer_reference(crtc->primary->fb);
 697
 698         pm_runtime_get_sync(dev->dev);
 699
 700         set_scanout(crtc, crtc->primary->fb);
 701
 702         pm_runtime_put_sync(dev->dev);
 703
 704         return 0;
 705 }
 706
 707 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 708         .destroy        = tilcdc_crtc_destroy,
 709         .set_config     = drm_atomic_helper_set_config,
 710         .page_flip      = drm_atomic_helper_page_flip,
 711         .reset          = drm_atomic_helper_crtc_reset,
 712         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 713         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 714 };
 715
 716 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 717                 .dpms           = tilcdc_crtc_dpms,
 718                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 719                 .prepare        = tilcdc_crtc_disable,
 720                 .commit         = tilcdc_crtc_enable,
 721                 .mode_set       = tilcdc_crtc_mode_set,
 722                 .mode_set_base  = tilcdc_crtc_mode_set_base,
 723                 .enable         = tilcdc_crtc_enable,
 724                 .disable        = tilcdc_crtc_disable,
 725                 .atomic_check   = tilcdc_crtc_atomic_check,
 726                 .mode_set_nofb  = tilcdc_crtc_mode_set_nofb,
 727 };
 728
 729 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 730 {
 731         struct drm_device *dev = crtc->dev;
 732         struct tilcdc_drm_private *priv = dev->dev_private;
 733         int max_width = 0;
 734
 735         if (priv->rev == 1)
 736                 max_width = 1024;
 737         else if (priv->rev == 2)
 738                 max_width = 2048;
 739
 740         return max_width;
 741 }
 742
 743 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 744 {
 745         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 746         unsigned int bandwidth;
 747         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 748
 749         /*
 750          * check to see if the width is within the range that
 751          * the LCD Controller physically supports
 752          */
 753         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 754                 return MODE_VIRTUAL_X;
 755
 756         /* width must be multiple of 16 */
 757         if (mode->hdisplay & 0xf)
 758                 return MODE_VIRTUAL_X;
 759
 760         if (mode->vdisplay > 2048)
 761                 return MODE_VIRTUAL_Y;
 762
 763         DBG("Processing mode %dx%d@%d with pixel clock %d",
 764                 mode->hdisplay, mode->vdisplay,
 765                 drm_mode_vrefresh(mode), mode->clock);
 766
 767         hbp = mode->htotal - mode->hsync_end;
 768         hfp = mode->hsync_start - mode->hdisplay;
 769         hsw = mode->hsync_end - mode->hsync_start;
 770         vbp = mode->vtotal - mode->vsync_end;
 771         vfp = mode->vsync_start - mode->vdisplay;
 772         vsw = mode->vsync_end - mode->vsync_start;
 773
 774         if ((hbp-1) & ~0x3ff) {
 775                 DBG("Pruning mode: Horizontal Back Porch out of range");
 776                 return MODE_HBLANK_WIDE;
 777         }
 778
 779         if ((hfp-1) & ~0x3ff) {
 780                 DBG("Pruning mode: Horizontal Front Porch out of range");
 781                 return MODE_HBLANK_WIDE;
 782         }
 783
 784         if ((hsw-1) & ~0x3ff) {
 785                 DBG("Pruning mode: Horizontal Sync Width out of range");
 786                 return MODE_HSYNC_WIDE;
 787         }
 788
 789         if (vbp & ~0xff) {
 790                 DBG("Pruning mode: Vertical Back Porch out of range");
 791                 return MODE_VBLANK_WIDE;
 792         }
 793
 794         if (vfp & ~0xff) {
 795                 DBG("Pruning mode: Vertical Front Porch out of range");
 796                 return MODE_VBLANK_WIDE;
 797         }
 798
 799         if ((vsw-1) & ~0x3f) {
 800                 DBG("Pruning mode: Vertical Sync Width out of range");
 801                 return MODE_VSYNC_WIDE;
 802         }
 803
 804         /*
 805          * some devices have a maximum allowed pixel clock
 806          * configured from the DT
 807          */
 808         if (mode->clock > priv->max_pixelclock) {
 809                 DBG("Pruning mode: pixel clock too high");
 810                 return MODE_CLOCK_HIGH;
 811         }
 812
 813         /*
 814          * some devices further limit the max horizontal resolution
 815          * configured from the DT
 816          */
 817         if (mode->hdisplay > priv->max_width)
 818                 return MODE_BAD_WIDTH;
 819
 820         /* filter out modes that would require too much memory bandwidth: */
 821         bandwidth = mode->hdisplay * mode->vdisplay *
 822                 drm_mode_vrefresh(mode);
 823         if (bandwidth > priv->max_bandwidth) {
 824                 DBG("Pruning mode: exceeds defined bandwidth limit");
 825                 return MODE_BAD;
 826         }
 827
 828         return MODE_OK;
 829 }
 830
 831 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 832                 const struct tilcdc_panel_info *info)
 833 {
 834         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 835         tilcdc_crtc->info = info;
 836 }
 837
 838 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
 839                                         bool simulate_vesa_sync)
 840 {
 841         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 842
 843         tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
 844 }
 845
 846 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 847 {
 848         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 849         struct drm_device *dev = crtc->dev;
 850         struct tilcdc_drm_private *priv = dev->dev_private;
 851         int dpms = tilcdc_crtc->dpms;
 852         unsigned long lcd_clk;
 853         const unsigned clkdiv = 2; /* using a fixed divider of 2 */
 854         int ret;
 855
 856         pm_runtime_get_sync(dev->dev);
 857
 858         if (dpms == DRM_MODE_DPMS_ON)
 859                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 860
 861         /* mode.clock is in KHz, set_rate wants parameter in Hz */
 862         ret = clk_set_rate(priv->clk, crtc->mode.clock * 1000 * clkdiv);
 863         if (ret < 0) {
 864                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 865                                 crtc->mode.clock);
 866                 goto out;
 867         }
 868
 869         lcd_clk = clk_get_rate(priv->clk);
 870
 871         DBG("lcd_clk=%lu, mode clock=%d, div=%u",
 872                 lcd_clk, crtc->mode.clock, clkdiv);
 873
 874         /* Configure the LCD clock divisor. */
 875         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
 876                         LCDC_RASTER_MODE);
 877
 878         if (priv->rev == 2)
 879                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 880                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 881                                 LCDC_V2_CORE_CLK_EN);
 882
 883         if (dpms == DRM_MODE_DPMS_ON)
 884                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 885
 886 out:
 887         pm_runtime_put_sync(dev->dev);
 888 }
 889
 890 #define SYNC_LOST_COUNT_LIMIT 50
 891
 892 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 893 {
 894         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 895         struct drm_device *dev = crtc->dev;
 896         struct tilcdc_drm_private *priv = dev->dev_private;
 897         uint32_t stat;
 898
 899         stat = tilcdc_read_irqstatus(dev);
 900         tilcdc_clear_irqstatus(dev, stat);
 901
 902         if (stat & LCDC_END_OF_FRAME0) {
 903                 unsigned long flags;
 904                 bool skip_event = false;
 905                 ktime_t now;
 906
 907                 now = ktime_get();
 908
 909                 drm_flip_work_commit(&tilcdc_crtc->unref_work, priv->wq);
 910
 911                 spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
 912
 913                 tilcdc_crtc->last_vblank = now;
 914
 915                 if (tilcdc_crtc->next_fb) {
 916                         set_scanout(crtc, tilcdc_crtc->next_fb);
 917                         tilcdc_crtc->next_fb = NULL;
 918                         skip_event = true;
 919                 }
 920
 921                 spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
 922
 923                 drm_crtc_handle_vblank(crtc);
 924
 925                 if (!skip_event) {
 926                         struct drm_pending_vblank_event *event;
 927
 928                         spin_lock_irqsave(&dev->event_lock, flags);
 929
 930                         event = tilcdc_crtc->event;
 931                         tilcdc_crtc->event = NULL;
 932                         if (event)
 933                                 drm_crtc_send_vblank_event(crtc, event);
 934
 935                         spin_unlock_irqrestore(&dev->event_lock, flags);
 936                 }
 937
 938                 if (tilcdc_crtc->frame_intact)
 939                         tilcdc_crtc->sync_lost_count = 0;
 940                 else
 941                         tilcdc_crtc->frame_intact = true;
 942         }
 943
 944         if (stat & LCDC_FIFO_UNDERFLOW)
 945                 dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underfow",
 946                                     __func__, stat);
 947
 948         /* For revision 2 only */
 949         if (priv->rev == 2) {
 950                 if (stat & LCDC_FRAME_DONE) {
 951                         tilcdc_crtc->frame_done = true;
 952                         wake_up(&tilcdc_crtc->frame_done_wq);
 953                 }
 954
 955                 if (stat & LCDC_SYNC_LOST) {
 956                         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
 957                                             __func__, stat);
 958                         tilcdc_crtc->frame_intact = false;
 959                         if (tilcdc_crtc->sync_lost_count++ >
 960                             SYNC_LOST_COUNT_LIMIT) {
 961                                 dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
 962                                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
 963                                              LCDC_SYNC_LOST);
 964                         }
 965                 }
 966
 967                 /* Indicate to LCDC that the interrupt service routine has
 968                  * completed, see 13.3.6.1.6 in AM335x TRM.
 969                  */
 970                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 971         }
 972
 973         return IRQ_HANDLED;
 974 }
 975
 976 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 977 {
 978         struct tilcdc_drm_private *priv = dev->dev_private;
 979         struct tilcdc_crtc *tilcdc_crtc;
 980         struct drm_crtc *crtc;
 981         int ret;
 982
 983         tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
 984         if (!tilcdc_crtc) {
 985                 dev_err(dev->dev, "allocation failed\n");
 986                 return NULL;
 987         }
 988
 989         crtc = &tilcdc_crtc->base;
 990
 991         ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
 992         if (ret < 0)
 993                 goto fail;
 994
 995         tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
 996         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 997
 998         drm_flip_work_init(&tilcdc_crtc->unref_work,
 999                         "unref", unref_worker);
1000
1001         spin_lock_init(&tilcdc_crtc->irq_lock);
1002
1003         ret = drm_crtc_init_with_planes(dev, crtc,
1004                                         &tilcdc_crtc->primary,
1005                                         NULL,
1006                                         &tilcdc_crtc_funcs,
1007                                         "tilcdc crtc");
1008         if (ret < 0)
1009                 goto fail;
1010
1011         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1012
1013         if (priv->is_componentized) {
1014                 struct device_node *ports =
1015                         of_get_child_by_name(dev->dev->of_node, "ports");
1016
1017                 if (ports) {
1018                         crtc->port = of_get_child_by_name(ports, "port");
1019                         of_node_put(ports);
1020                 } else {
1021                         crtc->port =
1022                                 of_get_child_by_name(dev->dev->of_node, "port");
1023                 }
1024                 if (!crtc->port) { /* This should never happen */
1025                         dev_err(dev->dev, "Port node not found in %s\n",
1026                                 dev->dev->of_node->full_name);
1027                         goto fail;
1028                 }
1029         }
1030
1031         return crtc;
1032
1033 fail:
1034         tilcdc_crtc_destroy(crtc);
1035         return NULL;
1036 }