drivers/hwtracing/coresight/coresight-stm.c

   1 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   2  *
   3  * Description: CoreSight System Trace Macrocell driver
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * Initial implementation by Pratik Patel
  15  * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
  16  *
  17  * Serious refactoring, code cleanup and upgrading to the Coresight upstream
  18  * framework by Mathieu Poirier
  19  * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
  20  *
  21  * Guaranteed timing and support for various packet type coming from the
  22  * generic STM API by Chunyan Zhang
  23  * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
  24  */
  25 #include <asm/local.h>
  26 #include <linux/amba/bus.h>
  27 #include <linux/bitmap.h>
  28 #include <linux/clk.h>
  29 #include <linux/coresight.h>
  30 #include <linux/coresight-stm.h>
  31 #include <linux/err.h>
  32 #include <linux/kernel.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/of_address.h>
  35 #include <linux/perf_event.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/stm.h>
  38
  39 #include "coresight-priv.h"
  40
  41 #define STMDMASTARTR                    0xc04
  42 #define STMDMASTOPR                     0xc08
  43 #define STMDMASTATR                     0xc0c
  44 #define STMDMACTLR                      0xc10
  45 #define STMDMAIDR                       0xcfc
  46 #define STMHEER                         0xd00
  47 #define STMHETER                        0xd20
  48 #define STMHEBSR                        0xd60
  49 #define STMHEMCR                        0xd64
  50 #define STMHEMASTR                      0xdf4
  51 #define STMHEFEAT1R                     0xdf8
  52 #define STMHEIDR                        0xdfc
  53 #define STMSPER                         0xe00
  54 #define STMSPTER                        0xe20
  55 #define STMPRIVMASKR                    0xe40
  56 #define STMSPSCR                        0xe60
  57 #define STMSPMSCR                       0xe64
  58 #define STMSPOVERRIDER                  0xe68
  59 #define STMSPMOVERRIDER                 0xe6c
  60 #define STMSPTRIGCSR                    0xe70
  61 #define STMTCSR                         0xe80
  62 #define STMTSSTIMR                      0xe84
  63 #define STMTSFREQR                      0xe8c
  64 #define STMSYNCR                        0xe90
  65 #define STMAUXCR                        0xe94
  66 #define STMSPFEAT1R                     0xea0
  67 #define STMSPFEAT2R                     0xea4
  68 #define STMSPFEAT3R                     0xea8
  69 #define STMITTRIGGER                    0xee8
  70 #define STMITATBDATA0                   0xeec
  71 #define STMITATBCTR2                    0xef0
  72 #define STMITATBID                      0xef4
  73 #define STMITATBCTR0                    0xef8
  74
  75 #define STM_32_CHANNEL                  32
  76 #define BYTES_PER_CHANNEL               256
  77 #define STM_TRACE_BUF_SIZE              4096
  78 #define STM_SW_MASTER_END               127
  79
  80 /* Register bit definition */
  81 #define STMTCSR_BUSY_BIT                23
  82 /* Reserve the first 10 channels for kernel usage */
  83 #define STM_CHANNEL_OFFSET              0
  84
  85 enum stm_pkt_type {
  86         STM_PKT_TYPE_DATA       = 0x98,
  87         STM_PKT_TYPE_FLAG       = 0xE8,
  88         STM_PKT_TYPE_TRIG       = 0xF8,
  89 };
  90
  91 #define stm_channel_addr(drvdata, ch)   (drvdata->chs.base +    \
  92                                         (ch * BYTES_PER_CHANNEL))
  93 #define stm_channel_off(type, opts)     (type & ~opts)
  94
  95 static int boot_nr_channel;
  96
  97 /*
  98  * Not really modular but using module_param is the easiest way to
  99  * remain consistent with existing use cases for now.
 100  */
 101 module_param_named(
 102         boot_nr_channel, boot_nr_channel, int, S_IRUGO
 103 );
 104
 105 /**
 106  * struct channel_space - central management entity for extended ports
 107  * @base:               memory mapped base address where channels start.
 108  * @phys:               physical base address of channel region.
 109  * @guaraneed:          is the channel delivery guaranteed.
 110  */
 111 struct channel_space {
 112         void __iomem            *base;
 113         phys_addr_t             phys;
 114         unsigned long           *guaranteed;
 115 };
 116
 117 /**
 118  * struct stm_drvdata - specifics associated to an STM component
 119  * @base:               memory mapped base address for this component.
 120  * @dev:                the device entity associated to this component.
 121  * @atclk:              optional clock for the core parts of the STM.
 122  * @csdev:              component vitals needed by the framework.
 123  * @spinlock:           only one at a time pls.
 124  * @chs:                the channels accociated to this STM.
 125  * @stm:                structure associated to the generic STM interface.
 126  * @mode:               this tracer's mode, i.e sysFS, or disabled.
 127  * @traceid:            value of the current ID for this component.
 128  * @write_bytes:        Maximus bytes this STM can write at a time.
 129  * @stmsper:            settings for register STMSPER.
 130  * @stmspscr:           settings for register STMSPSCR.
 131  * @numsp:              the total number of stimulus port support by this STM.
 132  * @stmheer:            settings for register STMHEER.
 133  * @stmheter:           settings for register STMHETER.
 134  * @stmhebsr:           settings for register STMHEBSR.
 135  */
 136 struct stm_drvdata {
 137         void __iomem            *base;
 138         struct device           *dev;
 139         struct clk              *atclk;
 140         struct coresight_device *csdev;
 141         spinlock_t              spinlock;
 142         struct channel_space    chs;
 143         struct stm_data         stm;
 144         local_t                 mode;
 145         u8                      traceid;
 146         u32                     write_bytes;
 147         u32                     stmsper;
 148         u32                     stmspscr;
 149         u32                     numsp;
 150         u32                     stmheer;
 151         u32                     stmheter;
 152         u32                     stmhebsr;
 153 };
 154
 155 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
 156 {
 157         CS_UNLOCK(drvdata->base);
 158
 159         writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
 160         writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
 161         writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
 162         writel_relaxed(0x01 |   /* Enable HW event tracing */
 163                        0x04,    /* Error detection on event tracing */
 164                        drvdata->base + STMHEMCR);
 165
 166         CS_LOCK(drvdata->base);
 167 }
 168
 169 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
 170 {
 171         CS_UNLOCK(drvdata->base);
 172         /* ATB trigger enable on direct writes to TRIG locations */
 173         writel_relaxed(0x10,
 174                        drvdata->base + STMSPTRIGCSR);
 175         writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 176         writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 177
 178         CS_LOCK(drvdata->base);
 179 }
 180
 181 static void stm_enable_hw(struct stm_drvdata *drvdata)
 182 {
 183         if (drvdata->stmheer)
 184                 stm_hwevent_enable_hw(drvdata);
 185
 186         stm_port_enable_hw(drvdata);
 187
 188         CS_UNLOCK(drvdata->base);
 189
 190         /* 4096 byte between synchronisation packets */
 191         writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
 192         writel_relaxed((drvdata->traceid << 16 | /* trace id */
 193                         0x02 |                   /* timestamp enable */
 194                         0x01),                   /* global STM enable */
 195                         drvdata->base + STMTCSR);
 196
 197         CS_LOCK(drvdata->base);
 198 }
 199
 200 static int stm_enable(struct coresight_device *csdev,
 201                       struct perf_event_attr *attr, u32 mode)
 202 {
 203         u32 val;
 204         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 205
 206         if (mode != CS_MODE_SYSFS)
 207                 return -EINVAL;
 208
 209         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 210
 211         /* Someone is already using the tracer */
 212         if (val)
 213                 return -EBUSY;
 214
 215         pm_runtime_get_sync(drvdata->dev);
 216
 217         spin_lock(&drvdata->spinlock);
 218         stm_enable_hw(drvdata);
 219         spin_unlock(&drvdata->spinlock);
 220
 221         dev_info(drvdata->dev, "STM tracing enabled\n");
 222         return 0;
 223 }
 224
 225 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
 226 {
 227         CS_UNLOCK(drvdata->base);
 228
 229         writel_relaxed(0x0, drvdata->base + STMHEMCR);
 230         writel_relaxed(0x0, drvdata->base + STMHEER);
 231         writel_relaxed(0x0, drvdata->base + STMHETER);
 232
 233         CS_LOCK(drvdata->base);
 234 }
 235
 236 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
 237 {
 238         CS_UNLOCK(drvdata->base);
 239
 240         writel_relaxed(0x0, drvdata->base + STMSPER);
 241         writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
 242
 243         CS_LOCK(drvdata->base);
 244 }
 245
 246 static void stm_disable_hw(struct stm_drvdata *drvdata)
 247 {
 248         u32 val;
 249
 250         CS_UNLOCK(drvdata->base);
 251
 252         val = readl_relaxed(drvdata->base + STMTCSR);
 253         val &= ~0x1; /* clear global STM enable [0] */
 254         writel_relaxed(val, drvdata->base + STMTCSR);
 255
 256         CS_LOCK(drvdata->base);
 257
 258         stm_port_disable_hw(drvdata);
 259         if (drvdata->stmheer)
 260                 stm_hwevent_disable_hw(drvdata);
 261 }
 262
 263 static void stm_disable(struct coresight_device *csdev)
 264 {
 265         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 266
 267         /*
 268          * For as long as the tracer isn't disabled another entity can't
 269          * change its status.  As such we can read the status here without
 270          * fearing it will change under us.
 271          */
 272         if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
 273                 spin_lock(&drvdata->spinlock);
 274                 stm_disable_hw(drvdata);
 275                 spin_unlock(&drvdata->spinlock);
 276
 277                 /* Wait until the engine has completely stopped */
 278                 coresight_timeout(drvdata, STMTCSR, STMTCSR_BUSY_BIT, 0);
 279
 280                 pm_runtime_put(drvdata->dev);
 281
 282                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 283                 dev_info(drvdata->dev, "STM tracing disabled\n");
 284         }
 285 }
 286
 287 static int stm_trace_id(struct coresight_device *csdev)
 288 {
 289         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 290
 291         return drvdata->traceid;
 292 }
 293
 294 static const struct coresight_ops_source stm_source_ops = {
 295         .trace_id       = stm_trace_id,
 296         .enable         = stm_enable,
 297         .disable        = stm_disable,
 298 };
 299
 300 static const struct coresight_ops stm_cs_ops = {
 301         .source_ops     = &stm_source_ops,
 302 };
 303
 304 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
 305 {
 306         return ((unsigned long)addr & (write_bytes - 1));
 307 }
 308
 309 static void stm_send(void *addr, const void *data, u32 size, u8 write_bytes)
 310 {
 311         u8 paload[8];
 312
 313         if (stm_addr_unaligned(data, write_bytes)) {
 314                 memcpy(paload, data, size);
 315                 data = paload;
 316         }
 317
 318         /* now we are 64bit/32bit aligned */
 319         switch (size) {
 320 #ifdef CONFIG_64BIT
 321         case 8:
 322                 writeq_relaxed(*(u64 *)data, addr);
 323                 break;
 324 #endif
 325         case 4:
 326                 writel_relaxed(*(u32 *)data, addr);
 327                 break;
 328         case 2:
 329                 writew_relaxed(*(u16 *)data, addr);
 330                 break;
 331         case 1:
 332                 writeb_relaxed(*(u8 *)data, addr);
 333                 break;
 334         default:
 335                 break;
 336         }
 337 }
 338
 339 static int stm_generic_link(struct stm_data *stm_data,
 340                             unsigned int master,  unsigned int channel)
 341 {
 342         struct stm_drvdata *drvdata = container_of(stm_data,
 343                                                    struct stm_drvdata, stm);
 344         if (!drvdata || !drvdata->csdev)
 345                 return -EINVAL;
 346
 347         return coresight_enable(drvdata->csdev);
 348 }
 349
 350 static void stm_generic_unlink(struct stm_data *stm_data,
 351                                unsigned int master,  unsigned int channel)
 352 {
 353         struct stm_drvdata *drvdata = container_of(stm_data,
 354                                                    struct stm_drvdata, stm);
 355         if (!drvdata || !drvdata->csdev)
 356                 return;
 357
 358         stm_disable(drvdata->csdev);
 359 }
 360
 361 static phys_addr_t
 362 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
 363               unsigned int channel, unsigned int nr_chans)
 364 {
 365         struct stm_drvdata *drvdata = container_of(stm_data,
 366                                                    struct stm_drvdata, stm);
 367         phys_addr_t addr;
 368
 369         addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
 370
 371         if (offset_in_page(addr) ||
 372             offset_in_page(nr_chans * BYTES_PER_CHANNEL))
 373                 return 0;
 374
 375         return addr;
 376 }
 377
 378 static long stm_generic_set_options(struct stm_data *stm_data,
 379                                     unsigned int master,
 380                                     unsigned int channel,
 381                                     unsigned int nr_chans,
 382                                     unsigned long options)
 383 {
 384         struct stm_drvdata *drvdata = container_of(stm_data,
 385                                                    struct stm_drvdata, stm);
 386         if (!(drvdata && local_read(&drvdata->mode)))
 387                 return -EINVAL;
 388
 389         if (channel >= drvdata->numsp)
 390                 return -EINVAL;
 391
 392         switch (options) {
 393         case STM_OPTION_GUARANTEED:
 394                 set_bit(channel, drvdata->chs.guaranteed);
 395                 break;
 396
 397         case STM_OPTION_INVARIANT:
 398                 clear_bit(channel, drvdata->chs.guaranteed);
 399                 break;
 400
 401         default:
 402                 return -EINVAL;
 403         }
 404
 405         return 0;
 406 }
 407
 408 static ssize_t stm_generic_packet(struct stm_data *stm_data,
 409                                   unsigned int master,
 410                                   unsigned int channel,
 411                                   unsigned int packet,
 412                                   unsigned int flags,
 413                                   unsigned int size,
 414                                   const unsigned char *payload)
 415 {
 416         unsigned long ch_addr;
 417         struct stm_drvdata *drvdata = container_of(stm_data,
 418                                                    struct stm_drvdata, stm);
 419
 420         if (!(drvdata && local_read(&drvdata->mode)))
 421                 return 0;
 422
 423         if (channel >= drvdata->numsp)
 424                 return 0;
 425
 426         ch_addr = (unsigned long)stm_channel_addr(drvdata, channel);
 427
 428         flags = (flags == STP_PACKET_TIMESTAMPED) ? STM_FLAG_TIMESTAMPED : 0;
 429         flags |= test_bit(channel, drvdata->chs.guaranteed) ?
 430                            STM_FLAG_GUARANTEED : 0;
 431
 432         if (size > drvdata->write_bytes)
 433                 size = drvdata->write_bytes;
 434         else
 435                 size = rounddown_pow_of_two(size);
 436
 437         switch (packet) {
 438         case STP_PACKET_FLAG:
 439                 ch_addr |= stm_channel_off(STM_PKT_TYPE_FLAG, flags);
 440
 441                 /*
 442                  * The generic STM core sets a size of '0' on flag packets.
 443                  * As such send a flag packet of size '1' and tell the
 444                  * core we did so.
 445                  */
 446                 stm_send((void *)ch_addr, payload, 1, drvdata->write_bytes);
 447                 size = 1;
 448                 break;
 449
 450         case STP_PACKET_DATA:
 451                 ch_addr |= stm_channel_off(STM_PKT_TYPE_DATA, flags);
 452                 stm_send((void *)ch_addr, payload, size,
 453                                 drvdata->write_bytes);
 454                 break;
 455
 456         default:
 457                 return -ENOTSUPP;
 458         }
 459
 460         return size;
 461 }
 462
 463 static ssize_t hwevent_enable_show(struct device *dev,
 464                                    struct device_attribute *attr, char *buf)
 465 {
 466         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 467         unsigned long val = drvdata->stmheer;
 468
 469         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 470 }
 471
 472 static ssize_t hwevent_enable_store(struct device *dev,
 473                                     struct device_attribute *attr,
 474                                     const char *buf, size_t size)
 475 {
 476         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 477         unsigned long val;
 478         int ret = 0;
 479
 480         ret = kstrtoul(buf, 16, &val);
 481         if (ret)
 482                 return -EINVAL;
 483
 484         drvdata->stmheer = val;
 485         /* HW event enable and trigger go hand in hand */
 486         drvdata->stmheter = val;
 487
 488         return size;
 489 }
 490 static DEVICE_ATTR_RW(hwevent_enable);
 491
 492 static ssize_t hwevent_select_show(struct device *dev,
 493                                    struct device_attribute *attr, char *buf)
 494 {
 495         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 496         unsigned long val = drvdata->stmhebsr;
 497
 498         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 499 }
 500
 501 static ssize_t hwevent_select_store(struct device *dev,
 502                                     struct device_attribute *attr,
 503                                     const char *buf, size_t size)
 504 {
 505         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 506         unsigned long val;
 507         int ret = 0;
 508
 509         ret = kstrtoul(buf, 16, &val);
 510         if (ret)
 511                 return -EINVAL;
 512
 513         drvdata->stmhebsr = val;
 514
 515         return size;
 516 }
 517 static DEVICE_ATTR_RW(hwevent_select);
 518
 519 static ssize_t port_select_show(struct device *dev,
 520                                 struct device_attribute *attr, char *buf)
 521 {
 522         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 523         unsigned long val;
 524
 525         if (!local_read(&drvdata->mode)) {
 526                 val = drvdata->stmspscr;
 527         } else {
 528                 spin_lock(&drvdata->spinlock);
 529                 val = readl_relaxed(drvdata->base + STMSPSCR);
 530                 spin_unlock(&drvdata->spinlock);
 531         }
 532
 533         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 534 }
 535
 536 static ssize_t port_select_store(struct device *dev,
 537                                  struct device_attribute *attr,
 538                                  const char *buf, size_t size)
 539 {
 540         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 541         unsigned long val, stmsper;
 542         int ret = 0;
 543
 544         ret = kstrtoul(buf, 16, &val);
 545         if (ret)
 546                 return ret;
 547
 548         spin_lock(&drvdata->spinlock);
 549         drvdata->stmspscr = val;
 550
 551         if (local_read(&drvdata->mode)) {
 552                 CS_UNLOCK(drvdata->base);
 553                 /* Process as per ARM's TRM recommendation */
 554                 stmsper = readl_relaxed(drvdata->base + STMSPER);
 555                 writel_relaxed(0x0, drvdata->base + STMSPER);
 556                 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 557                 writel_relaxed(stmsper, drvdata->base + STMSPER);
 558                 CS_LOCK(drvdata->base);
 559         }
 560         spin_unlock(&drvdata->spinlock);
 561
 562         return size;
 563 }
 564 static DEVICE_ATTR_RW(port_select);
 565
 566 static ssize_t port_enable_show(struct device *dev,
 567                                 struct device_attribute *attr, char *buf)
 568 {
 569         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 570         unsigned long val;
 571
 572         if (!local_read(&drvdata->mode)) {
 573                 val = drvdata->stmsper;
 574         } else {
 575                 spin_lock(&drvdata->spinlock);
 576                 val = readl_relaxed(drvdata->base + STMSPER);
 577                 spin_unlock(&drvdata->spinlock);
 578         }
 579
 580         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 581 }
 582
 583 static ssize_t port_enable_store(struct device *dev,
 584                                  struct device_attribute *attr,
 585                                  const char *buf, size_t size)
 586 {
 587         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 588         unsigned long val;
 589         int ret = 0;
 590
 591         ret = kstrtoul(buf, 16, &val);
 592         if (ret)
 593                 return ret;
 594
 595         spin_lock(&drvdata->spinlock);
 596         drvdata->stmsper = val;
 597
 598         if (local_read(&drvdata->mode)) {
 599                 CS_UNLOCK(drvdata->base);
 600                 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 601                 CS_LOCK(drvdata->base);
 602         }
 603         spin_unlock(&drvdata->spinlock);
 604
 605         return size;
 606 }
 607 static DEVICE_ATTR_RW(port_enable);
 608
 609 static ssize_t traceid_show(struct device *dev,
 610                             struct device_attribute *attr, char *buf)
 611 {
 612         unsigned long val;
 613         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 614
 615         val = drvdata->traceid;
 616         return sprintf(buf, "%#lx\n", val);
 617 }
 618
 619 static ssize_t traceid_store(struct device *dev,
 620                              struct device_attribute *attr,
 621                              const char *buf, size_t size)
 622 {
 623         int ret;
 624         unsigned long val;
 625         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 626
 627         ret = kstrtoul(buf, 16, &val);
 628         if (ret)
 629                 return ret;
 630
 631         /* traceid field is 7bit wide on STM32 */
 632         drvdata->traceid = val & 0x7f;
 633         return size;
 634 }
 635 static DEVICE_ATTR_RW(traceid);
 636
 637 #define coresight_stm_simple_func(name, offset) \
 638         coresight_simple_func(struct stm_drvdata, name, offset)
 639
 640 coresight_stm_simple_func(tcsr, STMTCSR);
 641 coresight_stm_simple_func(tsfreqr, STMTSFREQR);
 642 coresight_stm_simple_func(syncr, STMSYNCR);
 643 coresight_stm_simple_func(sper, STMSPER);
 644 coresight_stm_simple_func(spter, STMSPTER);
 645 coresight_stm_simple_func(privmaskr, STMPRIVMASKR);
 646 coresight_stm_simple_func(spscr, STMSPSCR);
 647 coresight_stm_simple_func(spmscr, STMSPMSCR);
 648 coresight_stm_simple_func(spfeat1r, STMSPFEAT1R);
 649 coresight_stm_simple_func(spfeat2r, STMSPFEAT2R);
 650 coresight_stm_simple_func(spfeat3r, STMSPFEAT3R);
 651 coresight_stm_simple_func(devid, CORESIGHT_DEVID);
 652
 653 static struct attribute *coresight_stm_attrs[] = {
 654         &dev_attr_hwevent_enable.attr,
 655         &dev_attr_hwevent_select.attr,
 656         &dev_attr_port_enable.attr,
 657         &dev_attr_port_select.attr,
 658         &dev_attr_traceid.attr,
 659         NULL,
 660 };
 661
 662 static struct attribute *coresight_stm_mgmt_attrs[] = {
 663         &dev_attr_tcsr.attr,
 664         &dev_attr_tsfreqr.attr,
 665         &dev_attr_syncr.attr,
 666         &dev_attr_sper.attr,
 667         &dev_attr_spter.attr,
 668         &dev_attr_privmaskr.attr,
 669         &dev_attr_spscr.attr,
 670         &dev_attr_spmscr.attr,
 671         &dev_attr_spfeat1r.attr,
 672         &dev_attr_spfeat2r.attr,
 673         &dev_attr_spfeat3r.attr,
 674         &dev_attr_devid.attr,
 675         NULL,
 676 };
 677
 678 static const struct attribute_group coresight_stm_group = {
 679         .attrs = coresight_stm_attrs,
 680 };
 681
 682 static const struct attribute_group coresight_stm_mgmt_group = {
 683         .attrs = coresight_stm_mgmt_attrs,
 684         .name = "mgmt",
 685 };
 686
 687 static const struct attribute_group *coresight_stm_groups[] = {
 688         &coresight_stm_group,
 689         &coresight_stm_mgmt_group,
 690         NULL,
 691 };
 692
 693 static int stm_get_resource_byname(struct device_node *np,
 694                                    char *ch_base, struct resource *res)
 695 {
 696         const char *name = NULL;
 697         int index = 0, found = 0;
 698
 699         while (!of_property_read_string_index(np, "reg-names", index, &name)) {
 700                 if (strcmp(ch_base, name)) {
 701                         index++;
 702                         continue;
 703                 }
 704
 705                 /* We have a match and @index is where it's at */
 706                 found = 1;
 707                 break;
 708         }
 709
 710         if (!found)
 711                 return -EINVAL;
 712
 713         return of_address_to_resource(np, index, res);
 714 }
 715
 716 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
 717 {
 718         u32 stmspfeat2r;
 719
 720         if (!IS_ENABLED(CONFIG_64BIT))
 721                 return 4;
 722
 723         stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
 724
 725         /*
 726          * bit[15:12] represents the fundamental data size
 727          * 0 - 32-bit data
 728          * 1 - 64-bit data
 729          */
 730         return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
 731 }
 732
 733 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
 734 {
 735         u32 numsp;
 736
 737         numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 738         /*
 739          * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
 740          * 32 stimulus ports are supported.
 741          */
 742         numsp &= 0x1ffff;
 743         if (!numsp)
 744                 numsp = STM_32_CHANNEL;
 745         return numsp;
 746 }
 747
 748 static void stm_init_default_data(struct stm_drvdata *drvdata)
 749 {
 750         /* Don't use port selection */
 751         drvdata->stmspscr = 0x0;
 752         /*
 753          * Enable all channel regardless of their number.  When port
 754          * selection isn't used (see above) STMSPER applies to all
 755          * 32 channel group available, hence setting all 32 bits to 1
 756          */
 757         drvdata->stmsper = ~0x0;
 758
 759         /*
 760          * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
 761          * anything equal to or higher than 0x70 is reserved.  Since 0x00 is
 762          * also reserved the STM trace ID needs to be higher than 0x00 and
 763          * lowner than 0x10.
 764          */
 765         drvdata->traceid = 0x1;
 766
 767         /* Set invariant transaction timing on all channels */
 768         bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
 769 }
 770
 771 static void stm_init_generic_data(struct stm_drvdata *drvdata)
 772 {
 773         drvdata->stm.name = dev_name(drvdata->dev);
 774
 775         /*
 776          * MasterIDs are assigned at HW design phase. As such the core is
 777          * using a single master for interaction with this device.
 778          */
 779         drvdata->stm.sw_start = 1;
 780         drvdata->stm.sw_end = 1;
 781         drvdata->stm.hw_override = true;
 782         drvdata->stm.sw_nchannels = drvdata->numsp;
 783         drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
 784         drvdata->stm.packet = stm_generic_packet;
 785         drvdata->stm.mmio_addr = stm_mmio_addr;
 786         drvdata->stm.link = stm_generic_link;
 787         drvdata->stm.unlink = stm_generic_unlink;
 788         drvdata->stm.set_options = stm_generic_set_options;
 789 }
 790
 791 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
 792 {
 793         int ret;
 794         void __iomem *base;
 795         unsigned long *guaranteed;
 796         struct device *dev = &adev->dev;
 797         struct coresight_platform_data *pdata = NULL;
 798         struct stm_drvdata *drvdata;
 799         struct resource *res = &adev->res;
 800         struct resource ch_res;
 801         size_t res_size, bitmap_size;
 802         struct coresight_desc desc = { 0 };
 803         struct device_node *np = adev->dev.of_node;
 804
 805         if (np) {
 806                 pdata = of_get_coresight_platform_data(dev, np);
 807                 if (IS_ERR(pdata))
 808                         return PTR_ERR(pdata);
 809                 adev->dev.platform_data = pdata;
 810         }
 811         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 812         if (!drvdata)
 813                 return -ENOMEM;
 814
 815         drvdata->dev = &adev->dev;
 816         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 817         if (!IS_ERR(drvdata->atclk)) {
 818                 ret = clk_prepare_enable(drvdata->atclk);
 819                 if (ret)
 820                         return ret;
 821         }
 822         dev_set_drvdata(dev, drvdata);
 823
 824         base = devm_ioremap_resource(dev, res);
 825         if (IS_ERR(base))
 826                 return PTR_ERR(base);
 827         drvdata->base = base;
 828
 829         ret = stm_get_resource_byname(np, "stm-stimulus-base", &ch_res);
 830         if (ret)
 831                 return ret;
 832         drvdata->chs.phys = ch_res.start;
 833
 834         base = devm_ioremap_resource(dev, &ch_res);
 835         if (IS_ERR(base))
 836                 return PTR_ERR(base);
 837         drvdata->chs.base = base;
 838
 839         drvdata->write_bytes = stm_fundamental_data_size(drvdata);
 840
 841         if (boot_nr_channel) {
 842                 drvdata->numsp = boot_nr_channel;
 843                 res_size = min((resource_size_t)(boot_nr_channel *
 844                                   BYTES_PER_CHANNEL), resource_size(res));
 845         } else {
 846                 drvdata->numsp = stm_num_stimulus_port(drvdata);
 847                 res_size = min((resource_size_t)(drvdata->numsp *
 848                                  BYTES_PER_CHANNEL), resource_size(res));
 849         }
 850         bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
 851
 852         guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
 853         if (!guaranteed)
 854                 return -ENOMEM;
 855         drvdata->chs.guaranteed = guaranteed;
 856
 857         spin_lock_init(&drvdata->spinlock);
 858
 859         stm_init_default_data(drvdata);
 860         stm_init_generic_data(drvdata);
 861
 862         if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
 863                 dev_info(dev,
 864                          "stm_register_device failed, probing deffered\n");
 865                 return -EPROBE_DEFER;
 866         }
 867
 868         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
 869         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
 870         desc.ops = &stm_cs_ops;
 871         desc.pdata = pdata;
 872         desc.dev = dev;
 873         desc.groups = coresight_stm_groups;
 874         drvdata->csdev = coresight_register(&desc);
 875         if (IS_ERR(drvdata->csdev)) {
 876                 ret = PTR_ERR(drvdata->csdev);
 877                 goto stm_unregister;
 878         }
 879
 880         pm_runtime_put(&adev->dev);
 881
 882         dev_info(dev, "%s initialized\n", (char *)id->data);
 883         return 0;
 884
 885 stm_unregister:
 886         stm_unregister_device(&drvdata->stm);
 887         return ret;
 888 }
 889
 890 #ifdef CONFIG_PM
 891 static int stm_runtime_suspend(struct device *dev)
 892 {
 893         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 894
 895         if (drvdata && !IS_ERR(drvdata->atclk))
 896                 clk_disable_unprepare(drvdata->atclk);
 897
 898         return 0;
 899 }
 900
 901 static int stm_runtime_resume(struct device *dev)
 902 {
 903         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 904
 905         if (drvdata && !IS_ERR(drvdata->atclk))
 906                 clk_prepare_enable(drvdata->atclk);
 907
 908         return 0;
 909 }
 910 #endif
 911
 912 static const struct dev_pm_ops stm_dev_pm_ops = {
 913         SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
 914 };
 915
 916 static struct amba_id stm_ids[] = {
 917         {
 918                 .id     = 0x0003b962,
 919                 .mask   = 0x0003ffff,
 920                 .data   = "STM32",
 921         },
 922         { 0, 0},
 923 };
 924
 925 static struct amba_driver stm_driver = {
 926         .drv = {
 927                 .name   = "coresight-stm",
 928                 .owner  = THIS_MODULE,
 929                 .pm     = &stm_dev_pm_ops,
 930                 .suppress_bind_attrs = true,
 931         },
 932         .probe          = stm_probe,
 933         .id_table       = stm_ids,
 934 };
 935
 936 builtin_amba_driver(stm_driver);