drivers/i2c/busses/i2c-davinci.c

   1 /*
   2  * TI DAVINCI I2C adapter driver.
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  * Copyright (C) 2007 MontaVista Software Inc.
   6  *
   7  * Updated by Vinod & Sudhakar Feb 2005
   8  *
   9  * ----------------------------------------------------------------------------
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  * ----------------------------------------------------------------------------
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/delay.h>
  26 #include <linux/i2c.h>
  27 #include <linux/clk.h>
  28 #include <linux/errno.h>
  29 #include <linux/sched.h>
  30 #include <linux/err.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/io.h>
  34 #include <linux/slab.h>
  35 #include <linux/cpufreq.h>
  36 #include <linux/gpio.h>
  37 #include <linux/of_device.h>
  38 #include <linux/platform_data/i2c-davinci.h>
  39
  40 /* ----- global defines ----------------------------------------------- */
  41
  42 #define DAVINCI_I2C_TIMEOUT     (1*HZ)
  43 #define DAVINCI_I2C_MAX_TRIES   2
  44 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
  45                                  DAVINCI_I2C_IMR_SCD | \
  46                                  DAVINCI_I2C_IMR_ARDY | \
  47                                  DAVINCI_I2C_IMR_NACK | \
  48                                  DAVINCI_I2C_IMR_AL)
  49
  50 #define DAVINCI_I2C_OAR_REG     0x00
  51 #define DAVINCI_I2C_IMR_REG     0x04
  52 #define DAVINCI_I2C_STR_REG     0x08
  53 #define DAVINCI_I2C_CLKL_REG    0x0c
  54 #define DAVINCI_I2C_CLKH_REG    0x10
  55 #define DAVINCI_I2C_CNT_REG     0x14
  56 #define DAVINCI_I2C_DRR_REG     0x18
  57 #define DAVINCI_I2C_SAR_REG     0x1c
  58 #define DAVINCI_I2C_DXR_REG     0x20
  59 #define DAVINCI_I2C_MDR_REG     0x24
  60 #define DAVINCI_I2C_IVR_REG     0x28
  61 #define DAVINCI_I2C_EMDR_REG    0x2c
  62 #define DAVINCI_I2C_PSC_REG     0x30
  63
  64 #define DAVINCI_I2C_IVR_AAS     0x07
  65 #define DAVINCI_I2C_IVR_SCD     0x06
  66 #define DAVINCI_I2C_IVR_XRDY    0x05
  67 #define DAVINCI_I2C_IVR_RDR     0x04
  68 #define DAVINCI_I2C_IVR_ARDY    0x03
  69 #define DAVINCI_I2C_IVR_NACK    0x02
  70 #define DAVINCI_I2C_IVR_AL      0x01
  71
  72 #define DAVINCI_I2C_STR_BB      BIT(12)
  73 #define DAVINCI_I2C_STR_RSFULL  BIT(11)
  74 #define DAVINCI_I2C_STR_SCD     BIT(5)
  75 #define DAVINCI_I2C_STR_ARDY    BIT(2)
  76 #define DAVINCI_I2C_STR_NACK    BIT(1)
  77 #define DAVINCI_I2C_STR_AL      BIT(0)
  78
  79 #define DAVINCI_I2C_MDR_NACK    BIT(15)
  80 #define DAVINCI_I2C_MDR_STT     BIT(13)
  81 #define DAVINCI_I2C_MDR_STP     BIT(11)
  82 #define DAVINCI_I2C_MDR_MST     BIT(10)
  83 #define DAVINCI_I2C_MDR_TRX     BIT(9)
  84 #define DAVINCI_I2C_MDR_XA      BIT(8)
  85 #define DAVINCI_I2C_MDR_RM      BIT(7)
  86 #define DAVINCI_I2C_MDR_IRS     BIT(5)
  87
  88 #define DAVINCI_I2C_IMR_AAS     BIT(6)
  89 #define DAVINCI_I2C_IMR_SCD     BIT(5)
  90 #define DAVINCI_I2C_IMR_XRDY    BIT(4)
  91 #define DAVINCI_I2C_IMR_RRDY    BIT(3)
  92 #define DAVINCI_I2C_IMR_ARDY    BIT(2)
  93 #define DAVINCI_I2C_IMR_NACK    BIT(1)
  94 #define DAVINCI_I2C_IMR_AL      BIT(0)
  95
  96 struct davinci_i2c_dev {
  97         struct device           *dev;
  98         void __iomem            *base;
  99         struct completion       cmd_complete;
 100         struct clk              *clk;
 101         int                     cmd_err;
 102         u8                      *buf;
 103         size_t                  buf_len;
 104         int                     irq;
 105         int                     stop;
 106         u8                      terminate;
 107         struct i2c_adapter      adapter;
 108 #ifdef CONFIG_CPU_FREQ
 109         struct completion       xfr_complete;
 110         struct notifier_block   freq_transition;
 111 #endif
 112         struct davinci_i2c_platform_data *pdata;
 113 };
 114
 115 /* default platform data to use if not supplied in the platform_device */
 116 static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
 117         .bus_freq       = 100,
 118         .bus_delay      = 0,
 119 };
 120
 121 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
 122                                          int reg, u16 val)
 123 {
 124         writew_relaxed(val, i2c_dev->base + reg);
 125 }
 126
 127 static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 128 {
 129         return readw_relaxed(i2c_dev->base + reg);
 130 }
 131
 132 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
 133                                                                 int val)
 134 {
 135         u16 w;
 136
 137         w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
 138         if (!val)       /* put I2C into reset */
 139                 w &= ~DAVINCI_I2C_MDR_IRS;
 140         else            /* take I2C out of reset */
 141                 w |= DAVINCI_I2C_MDR_IRS;
 142
 143         davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 144 }
 145
 146 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 147 {
 148         struct davinci_i2c_platform_data *pdata = dev->pdata;
 149         u16 psc;
 150         u32 clk;
 151         u32 d;
 152         u32 clkh;
 153         u32 clkl;
 154         u32 input_clock = clk_get_rate(dev->clk);
 155
 156         /* NOTE: I2C Clock divider programming info
 157          * As per I2C specs the following formulas provide prescaler
 158          * and low/high divider values
 159          * input clk --> PSC Div -----------> ICCL/H Div --> output clock
 160          *                       module clk
 161          *
 162          * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
 163          *
 164          * Thus,
 165          * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
 166          *
 167          * where if PSC == 0, d = 7,
 168          *       if PSC == 1, d = 6
 169          *       if PSC > 1 , d = 5
 170          */
 171
 172         /* get minimum of 7 MHz clock, but max of 12 MHz */
 173         psc = (input_clock / 7000000) - 1;
 174         if ((input_clock / (psc + 1)) > 12000000)
 175                 psc++;  /* better to run under spec than over */
 176         d = (psc >= 2) ? 5 : 7 - psc;
 177
 178         clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)) - (d << 1);
 179         clkh = clk >> 1;
 180         clkl = clk - clkh;
 181
 182         davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
 183         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
 184         davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 185
 186         dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
 187 }
 188
 189 /*
 190  * This function configures I2C and brings I2C out of reset.
 191  * This function is called during I2C init function. This function
 192  * also gets called if I2C encounters any errors.
 193  */
 194 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 195 {
 196         struct davinci_i2c_platform_data *pdata = dev->pdata;
 197
 198         /* put I2C into reset */
 199         davinci_i2c_reset_ctrl(dev, 0);
 200
 201         /* compute clock dividers */
 202         i2c_davinci_calc_clk_dividers(dev);
 203
 204         /* Respond at reserved "SMBus Host" slave address" (and zero);
 205          * we seem to have no option to not respond...
 206          */
 207         davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 208
 209         dev_dbg(dev->dev, "PSC  = %d\n",
 210                 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
 211         dev_dbg(dev->dev, "CLKL = %d\n",
 212                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
 213         dev_dbg(dev->dev, "CLKH = %d\n",
 214                 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
 215         dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
 216                 pdata->bus_freq, pdata->bus_delay);
 217
 218
 219         /* Take the I2C module out of reset: */
 220         davinci_i2c_reset_ctrl(dev, 1);
 221
 222         /* Enable interrupts */
 223         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 224
 225         return 0;
 226 }
 227
 228 /*
 229  * This routine does i2c bus recovery by using i2c_generic_gpio_recovery
 230  * which is provided by I2C Bus recovery infrastructure.
 231  */
 232 static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
 233 {
 234         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 235
 236         /* Disable interrupts */
 237         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
 238
 239         /* put I2C into reset */
 240         davinci_i2c_reset_ctrl(dev, 0);
 241 }
 242
 243 static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
 244 {
 245         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 246
 247         i2c_davinci_init(dev);
 248 }
 249
 250 static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
 251         .recover_bus = i2c_generic_gpio_recovery,
 252         .prepare_recovery = davinci_i2c_prepare_recovery,
 253         .unprepare_recovery = davinci_i2c_unprepare_recovery,
 254 };
 255
 256 /*
 257  * Waiting for bus not busy
 258  */
 259 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 260                                          char allow_sleep)
 261 {
 262         unsigned long timeout;
 263         static u16 to_cnt;
 264
 265         timeout = jiffies + dev->adapter.timeout;
 266         while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
 267                & DAVINCI_I2C_STR_BB) {
 268                 if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
 269                         if (time_after(jiffies, timeout)) {
 270                                 dev_warn(dev->dev,
 271                                 "timeout waiting for bus ready\n");
 272                                 to_cnt++;
 273                                 return -ETIMEDOUT;
 274                         } else {
 275                                 to_cnt = 0;
 276                                 i2c_recover_bus(&dev->adapter);
 277                         }
 278                 }
 279                 if (allow_sleep)
 280                         schedule_timeout(1);
 281         }
 282
 283         return 0;
 284 }
 285
 286 /*
 287  * Low level master read/write transaction. This function is called
 288  * from i2c_davinci_xfer.
 289  */
 290 static int
 291 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
 292 {
 293         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 294         struct davinci_i2c_platform_data *pdata = dev->pdata;
 295         u32 flag;
 296         u16 w;
 297         unsigned long time_left;
 298
 299         /* Introduce a delay, required for some boards (e.g Davinci EVM) */
 300         if (pdata->bus_delay)
 301                 udelay(pdata->bus_delay);
 302
 303         /* set the slave address */
 304         davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 305
 306         dev->buf = msg->buf;
 307         dev->buf_len = msg->len;
 308         dev->stop = stop;
 309
 310         davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 311
 312         reinit_completion(&dev->cmd_complete);
 313         dev->cmd_err = 0;
 314
 315         /* Take I2C out of reset and configure it as master */
 316         flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 317
 318         /* if the slave address is ten bit address, enable XA bit */
 319         if (msg->flags & I2C_M_TEN)
 320                 flag |= DAVINCI_I2C_MDR_XA;
 321         if (!(msg->flags & I2C_M_RD))
 322                 flag |= DAVINCI_I2C_MDR_TRX;
 323         if (msg->len == 0)
 324                 flag |= DAVINCI_I2C_MDR_RM;
 325
 326         /* Enable receive or transmit interrupts */
 327         w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
 328         if (msg->flags & I2C_M_RD)
 329                 w |= DAVINCI_I2C_IMR_RRDY;
 330         else
 331                 w |= DAVINCI_I2C_IMR_XRDY;
 332         davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 333
 334         dev->terminate = 0;
 335
 336         /*
 337          * Write mode register first as needed for correct behaviour
 338          * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
 339          * occurring before we have loaded DXR
 340          */
 341         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 342
 343         /*
 344          * First byte should be set here, not after interrupt,
 345          * because transmit-data-ready interrupt can come before
 346          * NACK-interrupt during sending of previous message and
 347          * ICDXR may have wrong data
 348          * It also saves us one interrupt, slightly faster
 349          */
 350         if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
 351                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
 352                 dev->buf_len--;
 353         }
 354
 355         /* Set STT to begin transmit now DXR is loaded */
 356         flag |= DAVINCI_I2C_MDR_STT;
 357         if (stop && msg->len != 0)
 358                 flag |= DAVINCI_I2C_MDR_STP;
 359         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 360
 361         time_left = wait_for_completion_timeout(&dev->cmd_complete,
 362                                                 dev->adapter.timeout);
 363         if (!time_left) {
 364                 dev_err(dev->dev, "controller timed out\n");
 365                 i2c_recover_bus(adap);
 366                 dev->buf_len = 0;
 367                 return -ETIMEDOUT;
 368         }
 369         if (dev->buf_len) {
 370                 /* This should be 0 if all bytes were transferred
 371                  * or dev->cmd_err denotes an error.
 372                  */
 373                 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
 374                         dev->buf_len);
 375                 dev->terminate = 1;
 376                 wmb();
 377                 dev->buf_len = 0;
 378                 return -EREMOTEIO;
 379         }
 380
 381         /* no error */
 382         if (likely(!dev->cmd_err))
 383                 return msg->len;
 384
 385         /* We have an error */
 386         if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
 387                 i2c_davinci_init(dev);
 388                 return -EIO;
 389         }
 390
 391         if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
 392                 if (msg->flags & I2C_M_IGNORE_NAK)
 393                         return msg->len;
 394                 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 395                 w |= DAVINCI_I2C_MDR_STP;
 396                 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 397                 return -EREMOTEIO;
 398         }
 399         return -EIO;
 400 }
 401
 402 /*
 403  * Prepare controller for a transaction and call i2c_davinci_xfer_msg
 404  */
 405 static int
 406 i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 407 {
 408         struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
 409         int i;
 410         int ret;
 411
 412         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 413
 414         ret = i2c_davinci_wait_bus_not_busy(dev, 1);
 415         if (ret < 0) {
 416                 dev_warn(dev->dev, "timeout waiting for bus ready\n");
 417                 return ret;
 418         }
 419
 420         for (i = 0; i < num; i++) {
 421                 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 422                 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
 423                         ret);
 424                 if (ret < 0)
 425                         return ret;
 426         }
 427
 428 #ifdef CONFIG_CPU_FREQ
 429         complete(&dev->xfr_complete);
 430 #endif
 431
 432         return num;
 433 }
 434
 435 static u32 i2c_davinci_func(struct i2c_adapter *adap)
 436 {
 437         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 438 }
 439
 440 static void terminate_read(struct davinci_i2c_dev *dev)
 441 {
 442         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 443         w |= DAVINCI_I2C_MDR_NACK;
 444         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 445
 446         /* Throw away data */
 447         davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
 448         if (!dev->terminate)
 449                 dev_err(dev->dev, "RDR IRQ while no data requested\n");
 450 }
 451 static void terminate_write(struct davinci_i2c_dev *dev)
 452 {
 453         u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
 454         w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
 455         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 456
 457         if (!dev->terminate)
 458                 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
 459 }
 460
 461 /*
 462  * Interrupt service routine. This gets called whenever an I2C interrupt
 463  * occurs.
 464  */
 465 static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
 466 {
 467         struct davinci_i2c_dev *dev = dev_id;
 468         u32 stat;
 469         int count = 0;
 470         u16 w;
 471
 472         while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
 473                 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
 474                 if (count++ == 100) {
 475                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 476                         break;
 477                 }
 478
 479                 switch (stat) {
 480                 case DAVINCI_I2C_IVR_AL:
 481                         /* Arbitration lost, must retry */
 482                         dev->cmd_err |= DAVINCI_I2C_STR_AL;
 483                         dev->buf_len = 0;
 484                         complete(&dev->cmd_complete);
 485                         break;
 486
 487                 case DAVINCI_I2C_IVR_NACK:
 488                         dev->cmd_err |= DAVINCI_I2C_STR_NACK;
 489                         dev->buf_len = 0;
 490                         complete(&dev->cmd_complete);
 491                         break;
 492
 493                 case DAVINCI_I2C_IVR_ARDY:
 494                         davinci_i2c_write_reg(dev,
 495                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
 496                         if (((dev->buf_len == 0) && (dev->stop != 0)) ||
 497                             (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
 498                                 w = davinci_i2c_read_reg(dev,
 499                                                          DAVINCI_I2C_MDR_REG);
 500                                 w |= DAVINCI_I2C_MDR_STP;
 501                                 davinci_i2c_write_reg(dev,
 502                                                       DAVINCI_I2C_MDR_REG, w);
 503                         }
 504                         complete(&dev->cmd_complete);
 505                         break;
 506
 507                 case DAVINCI_I2C_IVR_RDR:
 508                         if (dev->buf_len) {
 509                                 *dev->buf++ =
 510                                     davinci_i2c_read_reg(dev,
 511                                                          DAVINCI_I2C_DRR_REG);
 512                                 dev->buf_len--;
 513                                 if (dev->buf_len)
 514                                         continue;
 515
 516                                 davinci_i2c_write_reg(dev,
 517                                         DAVINCI_I2C_STR_REG,
 518                                         DAVINCI_I2C_IMR_RRDY);
 519                         } else {
 520                                 /* signal can terminate transfer */
 521                                 terminate_read(dev);
 522                         }
 523                         break;
 524
 525                 case DAVINCI_I2C_IVR_XRDY:
 526                         if (dev->buf_len) {
 527                                 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
 528                                                       *dev->buf++);
 529                                 dev->buf_len--;
 530                                 if (dev->buf_len)
 531                                         continue;
 532
 533                                 w = davinci_i2c_read_reg(dev,
 534                                                          DAVINCI_I2C_IMR_REG);
 535                                 w &= ~DAVINCI_I2C_IMR_XRDY;
 536                                 davinci_i2c_write_reg(dev,
 537                                                       DAVINCI_I2C_IMR_REG,
 538                                                       w);
 539                         } else {
 540                                 /* signal can terminate transfer */
 541                                 terminate_write(dev);
 542                         }
 543                         break;
 544
 545                 case DAVINCI_I2C_IVR_SCD:
 546                         davinci_i2c_write_reg(dev,
 547                                 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
 548                         complete(&dev->cmd_complete);
 549                         break;
 550
 551                 case DAVINCI_I2C_IVR_AAS:
 552                         dev_dbg(dev->dev, "Address as slave interrupt\n");
 553                         break;
 554
 555                 default:
 556                         dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
 557                         break;
 558                 }
 559         }
 560
 561         return count ? IRQ_HANDLED : IRQ_NONE;
 562 }
 563
 564 #ifdef CONFIG_CPU_FREQ
 565 static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
 566                                      unsigned long val, void *data)
 567 {
 568         struct davinci_i2c_dev *dev;
 569
 570         dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
 571         if (val == CPUFREQ_PRECHANGE) {
 572                 wait_for_completion(&dev->xfr_complete);
 573                 davinci_i2c_reset_ctrl(dev, 0);
 574         } else if (val == CPUFREQ_POSTCHANGE) {
 575                 i2c_davinci_calc_clk_dividers(dev);
 576                 davinci_i2c_reset_ctrl(dev, 1);
 577         }
 578
 579         return 0;
 580 }
 581
 582 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 583 {
 584         dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
 585
 586         return cpufreq_register_notifier(&dev->freq_transition,
 587                                          CPUFREQ_TRANSITION_NOTIFIER);
 588 }
 589
 590 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 591 {
 592         cpufreq_unregister_notifier(&dev->freq_transition,
 593                                     CPUFREQ_TRANSITION_NOTIFIER);
 594 }
 595 #else
 596 static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
 597 {
 598         return 0;
 599 }
 600
 601 static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
 602 {
 603 }
 604 #endif
 605
 606 static struct i2c_algorithm i2c_davinci_algo = {
 607         .master_xfer    = i2c_davinci_xfer,
 608         .functionality  = i2c_davinci_func,
 609 };
 610
 611 static const struct of_device_id davinci_i2c_of_match[] = {
 612         {.compatible = "ti,davinci-i2c", },
 613         {},
 614 };
 615 MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
 616
 617 static int davinci_i2c_probe(struct platform_device *pdev)
 618 {
 619         struct davinci_i2c_dev *dev;
 620         struct i2c_adapter *adap;
 621         struct resource *mem;
 622         int r, irq;
 623
 624         irq = platform_get_irq(pdev, 0);
 625         if (irq <= 0) {
 626                 if (!irq)
 627                         irq = -ENXIO;
 628                 if (irq != -EPROBE_DEFER)
 629                         dev_err(&pdev->dev,
 630                                 "can't get irq resource ret=%d\n", irq);
 631                 return irq;
 632         }
 633
 634         dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
 635                         GFP_KERNEL);
 636         if (!dev) {
 637                 dev_err(&pdev->dev, "Memory allocation failed\n");
 638                 return -ENOMEM;
 639         }
 640
 641         init_completion(&dev->cmd_complete);
 642 #ifdef CONFIG_CPU_FREQ
 643         init_completion(&dev->xfr_complete);
 644 #endif
 645         dev->dev = &pdev->dev;
 646         dev->irq = irq;
 647         dev->pdata = dev_get_platdata(&pdev->dev);
 648         platform_set_drvdata(pdev, dev);
 649
 650         if (!dev->pdata && pdev->dev.of_node) {
 651                 u32 prop;
 652
 653                 dev->pdata = devm_kzalloc(&pdev->dev,
 654                         sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
 655                 if (!dev->pdata)
 656                         return -ENOMEM;
 657
 658                 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
 659                         sizeof(struct davinci_i2c_platform_data));
 660                 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
 661                         &prop))
 662                         dev->pdata->bus_freq = prop / 1000;
 663         } else if (!dev->pdata) {
 664                 dev->pdata = &davinci_i2c_platform_data_default;
 665         }
 666
 667         dev->clk = devm_clk_get(&pdev->dev, NULL);
 668         if (IS_ERR(dev->clk))
 669                 return -ENODEV;
 670         clk_prepare_enable(dev->clk);
 671
 672         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 673         dev->base = devm_ioremap_resource(&pdev->dev, mem);
 674         if (IS_ERR(dev->base)) {
 675                 r = PTR_ERR(dev->base);
 676                 goto err_unuse_clocks;
 677         }
 678
 679         i2c_davinci_init(dev);
 680
 681         r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
 682                         pdev->name, dev);
 683         if (r) {
 684                 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
 685                 goto err_unuse_clocks;
 686         }
 687
 688         r = i2c_davinci_cpufreq_register(dev);
 689         if (r) {
 690                 dev_err(&pdev->dev, "failed to register cpufreq\n");
 691                 goto err_unuse_clocks;
 692         }
 693
 694         adap = &dev->adapter;
 695         i2c_set_adapdata(adap, dev);
 696         adap->owner = THIS_MODULE;
 697         adap->class = I2C_CLASS_DEPRECATED;
 698         strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
 699         adap->algo = &i2c_davinci_algo;
 700         adap->dev.parent = &pdev->dev;
 701         adap->timeout = DAVINCI_I2C_TIMEOUT;
 702         adap->dev.of_node = pdev->dev.of_node;
 703
 704         if (dev->pdata->scl_pin) {
 705                 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
 706                 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
 707                 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
 708         }
 709
 710         adap->nr = pdev->id;
 711         r = i2c_add_numbered_adapter(adap);
 712         if (r) {
 713                 dev_err(&pdev->dev, "failure adding adapter\n");
 714                 goto err_unuse_clocks;
 715         }
 716
 717         return 0;
 718
 719 err_unuse_clocks:
 720         clk_disable_unprepare(dev->clk);
 721         dev->clk = NULL;
 722         return r;
 723 }
 724
 725 static int davinci_i2c_remove(struct platform_device *pdev)
 726 {
 727         struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
 728
 729         i2c_davinci_cpufreq_deregister(dev);
 730
 731         i2c_del_adapter(&dev->adapter);
 732
 733         clk_disable_unprepare(dev->clk);
 734         dev->clk = NULL;
 735
 736         davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
 737
 738         return 0;
 739 }
 740
 741 #ifdef CONFIG_PM
 742 static int davinci_i2c_suspend(struct device *dev)
 743 {
 744         struct platform_device *pdev = to_platform_device(dev);
 745         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 746
 747         /* put I2C into reset */
 748         davinci_i2c_reset_ctrl(i2c_dev, 0);
 749         clk_disable_unprepare(i2c_dev->clk);
 750
 751         return 0;
 752 }
 753
 754 static int davinci_i2c_resume(struct device *dev)
 755 {
 756         struct platform_device *pdev = to_platform_device(dev);
 757         struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 758
 759         clk_prepare_enable(i2c_dev->clk);
 760         /* take I2C out of reset */
 761         davinci_i2c_reset_ctrl(i2c_dev, 1);
 762
 763         return 0;
 764 }
 765
 766 static const struct dev_pm_ops davinci_i2c_pm = {
 767         .suspend        = davinci_i2c_suspend,
 768         .resume         = davinci_i2c_resume,
 769 };
 770
 771 #define davinci_i2c_pm_ops (&davinci_i2c_pm)
 772 #else
 773 #define davinci_i2c_pm_ops NULL
 774 #endif
 775
 776 /* work with hotplug and coldplug */
 777 MODULE_ALIAS("platform:i2c_davinci");
 778
 779 static struct platform_driver davinci_i2c_driver = {
 780         .probe          = davinci_i2c_probe,
 781         .remove         = davinci_i2c_remove,
 782         .driver         = {
 783                 .name   = "i2c_davinci",
 784                 .pm     = davinci_i2c_pm_ops,
 785                 .of_match_table = davinci_i2c_of_match,
 786         },
 787 };
 788
 789 /* I2C may be needed to bring up other drivers */
 790 static int __init davinci_i2c_init_driver(void)
 791 {
 792         return platform_driver_register(&davinci_i2c_driver);
 793 }
 794 subsys_initcall(davinci_i2c_init_driver);
 795
 796 static void __exit davinci_i2c_exit_driver(void)
 797 {
 798         platform_driver_unregister(&davinci_i2c_driver);
 799 }
 800 module_exit(davinci_i2c_exit_driver);
 801
 802 MODULE_AUTHOR("Texas Instruments India");
 803 MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
 804 MODULE_LICENSE("GPL");