2 * Synopsys DesignWare I2C adapter driver (master only).
4 * Based on the TI DAVINCI I2C adapter driver.
6 * Copyright (C) 2006 Texas Instruments.
7 * Copyright (C) 2007 MontaVista Software Inc.
8 * Copyright (C) 2009 Provigent Ltd.
10 * ----------------------------------------------------------------------------
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 * ----------------------------------------------------------------------------
24 #include <linux/export.h>
25 #include <linux/errno.h>
26 #include <linux/err.h>
27 #include <linux/i2c.h>
28 #include <linux/interrupt.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/delay.h>
32 #include <linux/module.h>
33 #include "i2c-designware-core.h"
40 #define DW_IC_DATA_CMD 0x10
41 #define DW_IC_SS_SCL_HCNT 0x14
42 #define DW_IC_SS_SCL_LCNT 0x18
43 #define DW_IC_FS_SCL_HCNT 0x1c
44 #define DW_IC_FS_SCL_LCNT 0x20
45 #define DW_IC_INTR_STAT 0x2c
46 #define DW_IC_INTR_MASK 0x30
47 #define DW_IC_RAW_INTR_STAT 0x34
48 #define DW_IC_RX_TL 0x38
49 #define DW_IC_TX_TL 0x3c
50 #define DW_IC_CLR_INTR 0x40
51 #define DW_IC_CLR_RX_UNDER 0x44
52 #define DW_IC_CLR_RX_OVER 0x48
53 #define DW_IC_CLR_TX_OVER 0x4c
54 #define DW_IC_CLR_RD_REQ 0x50
55 #define DW_IC_CLR_TX_ABRT 0x54
56 #define DW_IC_CLR_RX_DONE 0x58
57 #define DW_IC_CLR_ACTIVITY 0x5c
58 #define DW_IC_CLR_STOP_DET 0x60
59 #define DW_IC_CLR_START_DET 0x64
60 #define DW_IC_CLR_GEN_CALL 0x68
61 #define DW_IC_ENABLE 0x6c
62 #define DW_IC_STATUS 0x70
63 #define DW_IC_TXFLR 0x74
64 #define DW_IC_RXFLR 0x78
65 #define DW_IC_SDA_HOLD 0x7c
66 #define DW_IC_TX_ABRT_SOURCE 0x80
67 #define DW_IC_ENABLE_STATUS 0x9c
68 #define DW_IC_COMP_PARAM_1 0xf4
69 #define DW_IC_COMP_VERSION 0xf8
70 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
71 #define DW_IC_COMP_TYPE 0xfc
72 #define DW_IC_COMP_TYPE_VALUE 0x44570140
74 #define DW_IC_INTR_RX_UNDER 0x001
75 #define DW_IC_INTR_RX_OVER 0x002
76 #define DW_IC_INTR_RX_FULL 0x004
77 #define DW_IC_INTR_TX_OVER 0x008
78 #define DW_IC_INTR_TX_EMPTY 0x010
79 #define DW_IC_INTR_RD_REQ 0x020
80 #define DW_IC_INTR_TX_ABRT 0x040
81 #define DW_IC_INTR_RX_DONE 0x080
82 #define DW_IC_INTR_ACTIVITY 0x100
83 #define DW_IC_INTR_STOP_DET 0x200
84 #define DW_IC_INTR_START_DET 0x400
85 #define DW_IC_INTR_GEN_CALL 0x800
87 #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
88 DW_IC_INTR_TX_EMPTY | \
89 DW_IC_INTR_TX_ABRT | \
92 #define DW_IC_STATUS_ACTIVITY 0x1
94 #define DW_IC_ERR_TX_ABRT 0x1
96 #define DW_IC_TAR_10BITADDR_MASTER BIT(12)
101 #define STATUS_IDLE 0x0
102 #define STATUS_WRITE_IN_PROGRESS 0x1
103 #define STATUS_READ_IN_PROGRESS 0x2
105 #define TIMEOUT 20 /* ms */
108 * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
110 * only expected abort codes are listed here
111 * refer to the datasheet for the full list
113 #define ABRT_7B_ADDR_NOACK 0
114 #define ABRT_10ADDR1_NOACK 1
115 #define ABRT_10ADDR2_NOACK 2
116 #define ABRT_TXDATA_NOACK 3
117 #define ABRT_GCALL_NOACK 4
118 #define ABRT_GCALL_READ 5
119 #define ABRT_SBYTE_ACKDET 7
120 #define ABRT_SBYTE_NORSTRT 9
121 #define ABRT_10B_RD_NORSTRT 10
122 #define ABRT_MASTER_DIS 11
125 #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK)
126 #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK)
127 #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK)
128 #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK)
129 #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK)
130 #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ)
131 #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET)
132 #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT)
133 #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT)
134 #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS)
135 #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST)
137 #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
138 DW_IC_TX_ABRT_10ADDR1_NOACK | \
139 DW_IC_TX_ABRT_10ADDR2_NOACK | \
140 DW_IC_TX_ABRT_TXDATA_NOACK | \
141 DW_IC_TX_ABRT_GCALL_NOACK)
143 static char *abort_sources[] = {
144 [ABRT_7B_ADDR_NOACK] =
145 "slave address not acknowledged (7bit mode)",
146 [ABRT_10ADDR1_NOACK] =
147 "first address byte not acknowledged (10bit mode)",
148 [ABRT_10ADDR2_NOACK] =
149 "second address byte not acknowledged (10bit mode)",
150 [ABRT_TXDATA_NOACK] =
151 "data not acknowledged",
153 "no acknowledgement for a general call",
155 "read after general call",
156 [ABRT_SBYTE_ACKDET] =
157 "start byte acknowledged",
158 [ABRT_SBYTE_NORSTRT] =
159 "trying to send start byte when restart is disabled",
160 [ABRT_10B_RD_NORSTRT] =
161 "trying to read when restart is disabled (10bit mode)",
163 "trying to use disabled adapter",
168 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
172 if (dev->accessor_flags & ACCESS_16BIT)
173 value = readw_relaxed(dev->base + offset) |
174 (readw_relaxed(dev->base + offset + 2) << 16);
176 value = readl_relaxed(dev->base + offset);
178 if (dev->accessor_flags & ACCESS_SWAP)
179 return swab32(value);
184 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
186 if (dev->accessor_flags & ACCESS_SWAP)
189 if (dev->accessor_flags & ACCESS_16BIT) {
190 writew_relaxed((u16)b, dev->base + offset);
191 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
193 writel_relaxed(b, dev->base + offset);
198 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
201 * DesignWare I2C core doesn't seem to have solid strategy to meet
202 * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
203 * will result in violation of the tHD;STA spec.
207 * Conditional expression:
209 * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
211 * This is based on the DW manuals, and represents an ideal
212 * configuration. The resulting I2C bus speed will be
213 * faster than any of the others.
215 * If your hardware is free from tHD;STA issue, try this one.
217 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
220 * Conditional expression:
222 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
224 * This is just experimental rule; the tHD;STA period turned
225 * out to be proportinal to (_HCNT + 3). With this setting,
226 * we could meet both tHIGH and tHD;STA timing specs.
228 * If unsure, you'd better to take this alternative.
230 * The reason why we need to take into account "tf" here,
231 * is the same as described in i2c_dw_scl_lcnt().
233 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
237 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
240 * Conditional expression:
242 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
244 * DW I2C core starts counting the SCL CNTs for the LOW period
245 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
246 * In order to meet the tLOW timing spec, we need to take into
247 * account the fall time of SCL signal (tf). Default tf value
248 * should be 0.3 us, for safety.
250 return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
253 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
258 dw_writel(dev, enable, DW_IC_ENABLE);
259 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
263 * Wait 10 times the signaling period of the highest I2C
264 * transfer supported by the driver (for 400KHz this is
265 * 25us) as described in the DesignWare I2C databook.
267 usleep_range(25, 250);
270 dev_warn(dev->dev, "timeout in %sabling adapter\n",
271 enable ? "en" : "dis");
274 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
277 * Clock is not necessary if we got LCNT/HCNT values directly from
280 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
282 return dev->get_clk_rate_khz(dev);
286 * i2c_dw_init() - initialize the designware i2c master hardware
287 * @dev: device private data
289 * This functions configures and enables the I2C master.
290 * This function is called during I2C init function, and in case of timeout at
293 int i2c_dw_init(struct dw_i2c_dev *dev)
297 u32 sda_falling_time, scl_falling_time;
300 if (dev->acquire_lock) {
301 ret = dev->acquire_lock(dev);
303 dev_err(dev->dev, "couldn't acquire bus ownership\n");
308 reg = dw_readl(dev, DW_IC_COMP_TYPE);
309 if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
310 /* Configure register endianess access */
311 dev->accessor_flags |= ACCESS_SWAP;
312 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
313 /* Configure register access mode 16bit */
314 dev->accessor_flags |= ACCESS_16BIT;
315 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
316 dev_err(dev->dev, "Unknown Synopsys component type: "
318 if (dev->release_lock)
319 dev->release_lock(dev);
323 /* Disable the adapter */
324 __i2c_dw_enable(dev, false);
326 /* set standard and fast speed deviders for high/low periods */
328 sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
329 scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
331 /* Set SCL timing parameters for standard-mode */
332 if (dev->ss_hcnt && dev->ss_lcnt) {
336 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
337 4000, /* tHD;STA = tHIGH = 4.0 us */
339 0, /* 0: DW default, 1: Ideal */
341 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
342 4700, /* tLOW = 4.7 us */
346 dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
347 dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
348 dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
350 /* Set SCL timing parameters for fast-mode */
351 if (dev->fs_hcnt && dev->fs_lcnt) {
355 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
356 600, /* tHD;STA = tHIGH = 0.6 us */
358 0, /* 0: DW default, 1: Ideal */
360 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
361 1300, /* tLOW = 1.3 us */
365 dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
366 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
367 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
369 /* Configure SDA Hold Time if required */
370 if (dev->sda_hold_time) {
371 reg = dw_readl(dev, DW_IC_COMP_VERSION);
372 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
373 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
376 "Hardware too old to adjust SDA hold time.");
379 /* Configure Tx/Rx FIFO threshold levels */
380 dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
381 dw_writel(dev, 0, DW_IC_RX_TL);
383 /* configure the i2c master */
384 dw_writel(dev, dev->master_cfg , DW_IC_CON);
386 if (dev->release_lock)
387 dev->release_lock(dev);
390 EXPORT_SYMBOL_GPL(i2c_dw_init);
393 * Waiting for bus not busy
395 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
397 int timeout = TIMEOUT;
399 while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
401 dev_warn(dev->dev, "timeout waiting for bus ready\n");
405 usleep_range(1000, 1100);
411 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
413 struct i2c_msg *msgs = dev->msgs;
414 u32 ic_con, ic_tar = 0;
416 /* Disable the adapter */
417 __i2c_dw_enable(dev, false);
419 /* if the slave address is ten bit address, enable 10BITADDR */
420 ic_con = dw_readl(dev, DW_IC_CON);
421 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
422 ic_con |= DW_IC_CON_10BITADDR_MASTER;
424 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
425 * mode has to be enabled via bit 12 of IC_TAR register.
426 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
427 * detected from registers.
429 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
431 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
434 dw_writel(dev, ic_con, DW_IC_CON);
437 * Set the slave (target) address and enable 10-bit addressing mode
440 dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
442 /* enforce disabled interrupts (due to HW issues) */
443 i2c_dw_disable_int(dev);
445 /* Enable the adapter */
446 __i2c_dw_enable(dev, true);
448 /* Clear and enable interrupts */
449 dw_readl(dev, DW_IC_CLR_INTR);
450 dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK);
454 * Initiate (and continue) low level master read/write transaction.
455 * This function is only called from i2c_dw_isr, and pumping i2c_msg
456 * messages into the tx buffer. Even if the size of i2c_msg data is
457 * longer than the size of the tx buffer, it handles everything.
460 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
462 struct i2c_msg *msgs = dev->msgs;
464 int tx_limit, rx_limit;
465 u32 addr = msgs[dev->msg_write_idx].addr;
466 u32 buf_len = dev->tx_buf_len;
467 u8 *buf = dev->tx_buf;
468 bool need_restart = false;
470 intr_mask = DW_IC_INTR_DEFAULT_MASK;
472 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
474 * if target address has changed, we need to
475 * reprogram the target address in the i2c
476 * adapter when we are done with this transfer
478 if (msgs[dev->msg_write_idx].addr != addr) {
480 "%s: invalid target address\n", __func__);
481 dev->msg_err = -EINVAL;
485 if (msgs[dev->msg_write_idx].len == 0) {
487 "%s: invalid message length\n", __func__);
488 dev->msg_err = -EINVAL;
492 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
494 buf = msgs[dev->msg_write_idx].buf;
495 buf_len = msgs[dev->msg_write_idx].len;
497 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
498 * IC_RESTART_EN are set, we must manually
499 * set restart bit between messages.
501 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
502 (dev->msg_write_idx > 0))
506 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
507 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
509 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
513 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
514 * manually set the stop bit. However, it cannot be
515 * detected from the registers so we set it always
516 * when writing/reading the last byte.
518 if (dev->msg_write_idx == dev->msgs_num - 1 &&
524 need_restart = false;
527 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
529 /* avoid rx buffer overrun */
530 if (rx_limit - dev->rx_outstanding <= 0)
533 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
535 dev->rx_outstanding++;
537 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
538 tx_limit--; buf_len--;
542 dev->tx_buf_len = buf_len;
545 /* more bytes to be written */
546 dev->status |= STATUS_WRITE_IN_PROGRESS;
549 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
553 * If i2c_msg index search is completed, we don't need TX_EMPTY
554 * interrupt any more.
556 if (dev->msg_write_idx == dev->msgs_num)
557 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
562 dw_writel(dev, intr_mask, DW_IC_INTR_MASK);
566 i2c_dw_read(struct dw_i2c_dev *dev)
568 struct i2c_msg *msgs = dev->msgs;
571 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
575 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
578 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
579 len = msgs[dev->msg_read_idx].len;
580 buf = msgs[dev->msg_read_idx].buf;
582 len = dev->rx_buf_len;
586 rx_valid = dw_readl(dev, DW_IC_RXFLR);
588 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
589 *buf++ = dw_readl(dev, DW_IC_DATA_CMD);
590 dev->rx_outstanding--;
594 dev->status |= STATUS_READ_IN_PROGRESS;
595 dev->rx_buf_len = len;
599 dev->status &= ~STATUS_READ_IN_PROGRESS;
603 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
605 unsigned long abort_source = dev->abort_source;
608 if (abort_source & DW_IC_TX_ABRT_NOACK) {
609 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
611 "%s: %s\n", __func__, abort_sources[i]);
615 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
616 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
618 if (abort_source & DW_IC_TX_ARB_LOST)
620 else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
621 return -EINVAL; /* wrong msgs[] data */
627 * Prepare controller for a transaction and call i2c_dw_xfer_msg
630 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
632 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
635 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
637 mutex_lock(&dev->lock);
638 pm_runtime_get_sync(dev->dev);
640 reinit_completion(&dev->cmd_complete);
644 dev->msg_write_idx = 0;
645 dev->msg_read_idx = 0;
647 dev->status = STATUS_IDLE;
648 dev->abort_source = 0;
649 dev->rx_outstanding = 0;
651 if (dev->acquire_lock) {
652 ret = dev->acquire_lock(dev);
654 dev_err(dev->dev, "couldn't acquire bus ownership\n");
659 ret = i2c_dw_wait_bus_not_busy(dev);
663 /* start the transfers */
664 i2c_dw_xfer_init(dev);
666 /* wait for tx to complete */
667 if (!wait_for_completion_timeout(&dev->cmd_complete, HZ)) {
668 dev_err(dev->dev, "controller timed out\n");
669 /* i2c_dw_init implicitly disables the adapter */
676 * We must disable the adapter before unlocking the &dev->lock mutex
677 * below. Otherwise the hardware might continue generating interrupts
678 * which in turn causes a race condition with the following transfer.
679 * Needs some more investigation if the additional interrupts are
680 * a hardware bug or this driver doesn't handle them correctly yet.
682 __i2c_dw_enable(dev, false);
690 if (likely(!dev->cmd_err)) {
695 /* We have an error */
696 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
697 ret = i2c_dw_handle_tx_abort(dev);
703 if (dev->release_lock)
704 dev->release_lock(dev);
707 pm_runtime_mark_last_busy(dev->dev);
708 pm_runtime_put_autosuspend(dev->dev);
709 mutex_unlock(&dev->lock);
714 static u32 i2c_dw_func(struct i2c_adapter *adap)
716 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
717 return dev->functionality;
720 static struct i2c_algorithm i2c_dw_algo = {
721 .master_xfer = i2c_dw_xfer,
722 .functionality = i2c_dw_func,
725 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
730 * The IC_INTR_STAT register just indicates "enabled" interrupts.
731 * Ths unmasked raw version of interrupt status bits are available
732 * in the IC_RAW_INTR_STAT register.
735 * stat = dw_readl(IC_INTR_STAT);
737 * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
739 * The raw version might be useful for debugging purposes.
741 stat = dw_readl(dev, DW_IC_INTR_STAT);
744 * Do not use the IC_CLR_INTR register to clear interrupts, or
745 * you'll miss some interrupts, triggered during the period from
746 * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
748 * Instead, use the separately-prepared IC_CLR_* registers.
750 if (stat & DW_IC_INTR_RX_UNDER)
751 dw_readl(dev, DW_IC_CLR_RX_UNDER);
752 if (stat & DW_IC_INTR_RX_OVER)
753 dw_readl(dev, DW_IC_CLR_RX_OVER);
754 if (stat & DW_IC_INTR_TX_OVER)
755 dw_readl(dev, DW_IC_CLR_TX_OVER);
756 if (stat & DW_IC_INTR_RD_REQ)
757 dw_readl(dev, DW_IC_CLR_RD_REQ);
758 if (stat & DW_IC_INTR_TX_ABRT) {
760 * The IC_TX_ABRT_SOURCE register is cleared whenever
761 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
763 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
764 dw_readl(dev, DW_IC_CLR_TX_ABRT);
766 if (stat & DW_IC_INTR_RX_DONE)
767 dw_readl(dev, DW_IC_CLR_RX_DONE);
768 if (stat & DW_IC_INTR_ACTIVITY)
769 dw_readl(dev, DW_IC_CLR_ACTIVITY);
770 if (stat & DW_IC_INTR_STOP_DET)
771 dw_readl(dev, DW_IC_CLR_STOP_DET);
772 if (stat & DW_IC_INTR_START_DET)
773 dw_readl(dev, DW_IC_CLR_START_DET);
774 if (stat & DW_IC_INTR_GEN_CALL)
775 dw_readl(dev, DW_IC_CLR_GEN_CALL);
781 * Interrupt service routine. This gets called whenever an I2C interrupt
784 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
786 struct dw_i2c_dev *dev = dev_id;
789 enabled = dw_readl(dev, DW_IC_ENABLE);
790 stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
791 dev_dbg(dev->dev, "%s: enabled=%#x stat=%#x\n", __func__, enabled, stat);
792 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
795 stat = i2c_dw_read_clear_intrbits(dev);
797 if (stat & DW_IC_INTR_TX_ABRT) {
798 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
799 dev->status = STATUS_IDLE;
802 * Anytime TX_ABRT is set, the contents of the tx/rx
803 * buffers are flushed. Make sure to skip them.
805 dw_writel(dev, 0, DW_IC_INTR_MASK);
809 if (stat & DW_IC_INTR_RX_FULL)
812 if (stat & DW_IC_INTR_TX_EMPTY)
813 i2c_dw_xfer_msg(dev);
816 * No need to modify or disable the interrupt mask here.
817 * i2c_dw_xfer_msg() will take care of it according to
818 * the current transmit status.
822 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
823 complete(&dev->cmd_complete);
824 else if (unlikely(dev->accessor_flags & ACCESS_INTR_MASK)) {
825 /* workaround to trigger pending interrupt */
826 stat = dw_readl(dev, DW_IC_INTR_MASK);
827 i2c_dw_disable_int(dev);
828 dw_writel(dev, stat, DW_IC_INTR_MASK);
834 void i2c_dw_disable(struct dw_i2c_dev *dev)
836 /* Disable controller */
837 __i2c_dw_enable(dev, false);
839 /* Disable all interupts */
840 dw_writel(dev, 0, DW_IC_INTR_MASK);
841 dw_readl(dev, DW_IC_CLR_INTR);
843 EXPORT_SYMBOL_GPL(i2c_dw_disable);
845 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
847 dw_writel(dev, 0, DW_IC_INTR_MASK);
849 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
851 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
853 return dw_readl(dev, DW_IC_COMP_PARAM_1);
855 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
857 int i2c_dw_probe(struct dw_i2c_dev *dev)
859 struct i2c_adapter *adap = &dev->adapter;
862 init_completion(&dev->cmd_complete);
863 mutex_init(&dev->lock);
865 r = i2c_dw_init(dev);
869 snprintf(adap->name, sizeof(adap->name),
870 "Synopsys DesignWare I2C adapter");
872 adap->algo = &i2c_dw_algo;
873 adap->dev.parent = dev->dev;
874 i2c_set_adapdata(adap, dev);
876 i2c_dw_disable_int(dev);
877 r = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
878 IRQF_SHARED | IRQF_COND_SUSPEND,
879 dev_name(dev->dev), dev);
881 dev_err(dev->dev, "failure requesting irq %i: %d\n",
886 r = i2c_add_numbered_adapter(adap);
888 dev_err(dev->dev, "failure adding adapter: %d\n", r);
892 EXPORT_SYMBOL_GPL(i2c_dw_probe);
894 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
895 MODULE_LICENSE("GPL");